CN102123337B - Noise gate circuit system and designing method thereof - Google Patents
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Abstract
The invention provides a noise gate circuit system which comprises a head amplifier circuit for amplifying an electric signal and a signal processing circuit unit for processing the electric signal, wherein the signal processing circuit unit is provided with a full-wave rectification circuit unit, a filter circuit unit, a comparer circuit unit and a reference voltage generating circuit unit. The invention also provides a designing method based on the noise gate circuit system. Compared with relevant technologies, the noise gate circuit system and the designing method thereof have the advantages of low power consumption, low production cost, easiness in integration and high control accuracy.
Description
[technical field]
The present invention relates to a kind of Circuits System and method for designing thereof, relate in particular to a kind of Noise gate Circuits System and method for designing thereof that applies to microelectronic device.
[background technology]
Development along with wireless telecommunications, Global Mobile Phone Users is more and more, and the user not only is satisfied with conversation to the requirement of mobile phone, and wants high-quality communication effect can be provided, especially at present the development of mobile multimedia technology, the speech quality of mobile phone becomes more important.
Because the existence of a large amount of ambient noises, the general signal to noise ratio of the voice signal that the microphone of communication apparatus such as mobile phone collects is not high enough, particularly in high-noise environments such as street automobile, needs to improve volume the other side is not heard.So need promote the signal to noise ratio of input voice by the method that voice strengthen, improve communication quality.Correlation technique is the monolithic of being made by bipolar process, the circuit of simple function in order to the Noise gate Circuits System of de-noising, and sort circuit has low maladjustment voltage, low noise and other advantages.But because himself power consumption is big, be unfavorable for promoting the scale of circuit.When described Noise gate Circuits System need be integrated with other functional circuit, then adopt BiCOMS technological design Noise gate Circuits System, can have the flexibility of design like this.Yet, if will realize accurate Noise gate control, need the complicated low noise precision operational-amplifier of design, eliminate offset voltage as adopting the chopped mode method.The Noise gate Circuits System complex process of BiCOMS technological design, the production cost height is unfavorable for promoting at the consumer level circuit.
Therefore, be necessary to provide a kind of new Noise gate Circuits System to overcome the problems referred to above.
[summary of the invention]
The technical problem that the present invention need solve provides a kind of low in energy consumption, production cost is low, it is integrated to be easy to and control precision is high Noise gate Circuits System.
According to above-mentioned technical problem, designed a kind of Noise gate Circuits System, its objective is such realization: a kind of Noise gate Circuits System, it comprises the signal of telecommunication is amplified the preamplifier circuit of processing and the signal processing circuit unit that the signal of telecommunication after amplifying is handled.Wherein, described signal processing circuit unit is provided with:
The full-wave rectifying circuit unit comprises first operational amplifier, the make an uproar signal of telecommunication and it is play isolate and the buffering effect of the hum bar that be used for to receive described preamplifier circuit output; Second operational amplifier and the resistance and the diode that are electrically connected with second operational amplifier are used for the hum bar of described first operational amplifier output signal of telecommunication of making an uproar is carried out full-wave rectification and handles, and obtain the direct current band signal of telecommunication of making an uproar.
The filter circuit unit comprises the 3rd operational amplifier and the RC filter circuit that is electrically connected with described the 3rd operational amplifier, carries out the root mean square effective value for the signal of telecommunication that the direct current band of described full-wave rectifying circuit unit output is made an uproar and extracts.
The comparator circuit unit comprises the delay cell that first clock circuit, the second clock circuit with the first clock non-overlapping copies, first d type flip flop that the sampling trigger impulse is provided and second d type flip flop, the sampled signal that described second d type flip flop is exported postpone and the XOR gate of the signal that postpones being carried out the XOR processing.Described first clock circuit provides clock pulse for described first d type flip flop, and described second clock circuit provides clock pulse for described second d type flip flop.Be used for realizing the accurate comparison of signal.
The generating circuit from reference voltage unit, comprise resistance that even number is chained together and form noise threshold switch in parallel with each described resistance, for generation of reference voltage and export to described comparator circuit unit, also provide direct current biasing for the comparator circuit unit.
Preferably, described first operational amplifier, second operational amplifier and the 3rd operational amplifier are made by CMOS technology.
Preferably, described comparator circuit unit adopts the high-precision and low-offset voltage comparator, and its offset voltage is less than 1mV.
The present invention also provides a kind of method for designing based on Noise gate Circuits System of the present invention, and this method comprises the steps:
Step 1, provide a microphone, receiving belt noise tone signal converts thereof into hum bar the make an uproar signal of telecommunication and output.
The make an uproar signal of telecommunication and it is amplified processing of step 2, the hum bar that receives the output of described microphone by described preamplifier circuit, the hum bar after obtaining the amplifying signal of telecommunication of making an uproar.
Step 3, receive the make an uproar signal of telecommunication and it is carried out full-wave rectification handle of hum bar after the described amplification by described full-wave rectifying circuit unit, obtain direct current band after the rectification signal of telecommunication of making an uproar.
Step 4, receive the make an uproar signal of telecommunication and it is carried out the root mean square effective value extract of described direct current band by the filter circuit unit, obtain effective dc signal, comprise the steps:
Steps A 001, described signal processing circuit unit is carried out middle survey, the DC offset voltage that obtains described preamplifier circuit, full-wave rectifying circuit unit and filter circuit unit is made as Δ 1, Δ 2, Δ 3 respectively, total DC offset voltage on the described signal link is made as Δ offset, then has:
Δoffset＝Δa+Δ1+Δ2
If described effective dc signal is Vrms, supply voltage is V
DD, when described preamplifier circuit does not have the signal input, then have:
Vrms＝Δoffset+V
DD/2
Steps A 002, judge whether to be effective dc signal that the noise upper threshold value that described noise Circuits System is set is Vnth_h, then work as
Judge this moment effective dc signal that need pick up, the voice audio signals of control output;
It is Vnth_1 that the noise lower threshold value is set, and then works as
Judging this moment does not have effective dc signal that need pick up, and forbids exporting voice audio signals;
Step 5, described effective dc signal is exported to described comparator circuit unit it is accurately handled: it is Vref that a reference voltage is set, the offset voltage of comparator circuit unit is | Voffset|, reference voltage Vref is switched between noise upper threshold value Vnth_h and noise lower threshold value Vnth_1 according to the state in steps A 002 of effective dc signal Vrms, wherein Vnth_h＞Vnth_1.
Preferably, the mode switched between noise upper threshold value Vnth_h and noise lower threshold value Vnth_1 of the described effective dc signal Vrms in the step 5 is:
When Vrms＞Vref=Vnth_h, described comparator circuit unit is output as high level signal, when the described first rising edge clock pulse arrived, described first d type flip flop sampled the high level signal of described comparator circuit unit output and exports first high level signal.When the rising edge pulse of described second clock arrived, described second d type flip flop sampled first high level signal of described first d type flip flop.Described first high level signal is divided into two paths of signals through after the described delay units delay, and wherein one road signal is again through forming narrow pulse signal with another road signal through after the described XOR gate calculation process after the delay units delay;
When Vrms＜Vref=Vnth_1, described comparator circuit unit is output as low level signal, when the described first rising edge clock pulse arrived, described first d type flip flop sampled the low level signal of described comparator circuit unit output and exports first low level signal.When the rising edge pulse of described second clock arrived, described second d type flip flop sampled first low level signal of described first d type flip flop.Described first low level signal is divided into two paths of signals through after the described delay units delay, and wherein one road signal is again through forming narrow pulse signal with another road signal through after the described XOR gate calculation process after the delay units delay.
Preferably, described generating circuit from reference voltage unit to the method to set up of reference voltage is: supply voltage is made as V
DD, power supply is to connecing n resistance between the ground, and n is even number, and then the dividing potential drop of each resistance is V
DD/ n, n/2 electric resistance partial pressure is V
DD/ 2, V
DD/ 2 the whole Noise gate Circuits System that namely can be provides direct current biasing.When surveying in to signal processing circuit unit, the offset voltage that then can get described whole Noise gate Circuits System is Vnoffset=|Vrms-V
DD/ 2|+|Voffset|, and satisfy-Vos＜Vnoffset＜+Vos, Vos is reference voltage.
Compare with correlation technique, Noise gate Circuits System of the present invention and method for designing thereof it adopted cmos circuit to realize noise gate function, overcome the bigger shortcoming of cmos circuit offset voltage simultaneously, and circuit power consumption is low, and production cost is easy to integrated.
[description of drawings]
Fig. 1 is the structured flowchart of Noise gate Circuits System of the present invention.
Fig. 2 is the full-wave rectifying circuit of Noise gate Circuits System of the present invention and the schematic diagram of filter circuit.
Fig. 3 is the schematic diagram of the comparator circuit of Noise gate Circuits System of the present invention.
Fig. 4 produces the schematic diagram of circuit for the reference level of Noise gate Circuits System of the present invention
[embodiment]
The invention will be further described below in conjunction with drawings and embodiments.
The effect of Noise gate circuit is such, and noise source enters microphone generally away from microphone after the noise signal process air borne that it sends, the decay; And useful signal, the voice signal that sends as the people is then near microphone, so it is very little to the attenuation degree of microphone through air borne.Therefore, the energy amplitude difference of noise signal and wanted sound signal is bigger, when circuit only detects more low-level signal energy, thinks and has only ambient noise, and this moment, the output of shut-off circuit signal realized zero output; When electric circuit inspection arrives the signal energy of higher level, think wanted sound signal to occur, open circuit output this moment.Therefore, the Noise gate circuit is set energy compare threshold, i.e. a reference voltage.
Shown in Fig. 1-4, a kind of Noise gate Circuits System, it comprises the signal of telecommunication is amplified the preamplifier circuit of processing and the signal processing circuit unit that the signal of telecommunication after amplifying is handled.Wherein, described signal processing circuit unit is provided with:
The full-wave rectifying circuit unit comprises first operational amplifier, the make an uproar signal of telecommunication and it is play isolate and the buffering effect of the hum bar that be used for to receive described preamplifier circuit output; Second operational amplifier and the resistance and the diode that are electrically connected with second operational amplifier are used for the hum bar of described first operational amplifier output signal of telecommunication of making an uproar is carried out full-wave rectification and handles, and obtain the direct current band signal of telecommunication of making an uproar.
The filter circuit unit comprises the 3rd operational amplifier and the RC filter circuit that is electrically connected with described the 3rd operational amplifier, carries out the root mean square effective value for the signal of telecommunication that the direct current band of described full-wave rectifying circuit unit output is made an uproar and extracts.More excellent, described first operational amplifier, second operational amplifier and the 3rd operational amplifier are made by CMOS technology.
The comparator circuit unit comprises the delay cell that first clock circuit, the second clock circuit with the first clock non-overlapping copies, first d type flip flop that the sampling trigger impulse is provided and second d type flip flop, the sampled signal that described second d type flip flop is exported postpone and the XOR gate of the signal that postpones being carried out the XOR processing.Described first clock circuit provides clock pulse for described first d type flip flop, and described second clock circuit provides clock pulse for described second d type flip flop.Be used for realizing the accurate comparison of signal.Described comparator circuit unit adopts high-precision and low-offset voltage comparator structure to realize that its offset voltage is less than 1mV.
The generating circuit from reference voltage unit, comprise resistance that even number is chained together and form noise threshold switch in parallel with each described resistance, for generation of reference voltage and export to described comparator circuit unit, also provide direct current biasing for the comparator circuit unit.
The hum bar of the described preamplifier circuit output signal of telecommunication of making an uproar is exported to the normal phase input end of described first operational amplifier, is electrically connected with the described second moving amplifier's inverting input of calculating behind the output series resistor of described first operational amplifier.Described direct current biasing is exported to the normal phase input end of described second operational amplifier, after will handling behind diode of the output positive of described second operational amplifier serial connection with described full-wave rectifying circuit unit to the direct current band signal of telecommunication of making an uproar output to the normal phase input end of described the 3rd operational amplifier, and a resistance in parallel between the inverting input of described second operational amplifier and diode is exported behind RC filter circuit of output polyphone of described the 3rd operational amplifier.
The present invention also provides a kind of method for designing based on Noise gate Circuits System of the present invention, and this method comprises the steps:
Step 1, provide a microphone, receiving belt noise tone signal converts thereof into hum bar the make an uproar signal of telecommunication and output.
The make an uproar signal of telecommunication and it is amplified processing of step 2, the hum bar that receives the output of described microphone by described preamplifier circuit, the hum bar after obtaining the amplifying signal of telecommunication of making an uproar.
Step 3, receive the make an uproar signal of telecommunication and it is carried out full-wave rectification handle of hum bar after the described amplification by described full-wave rectifying circuit unit, obtain direct current band after the rectification signal of telecommunication of making an uproar.
Step 4, receive the make an uproar signal of telecommunication and it is carried out the root mean square effective value extract of described direct current band by the filter circuit unit, obtain effective dc signal, comprise the steps:
Steps A 001, described signal processing circuit unit is carried out middle survey, the DC offset voltage that obtains described preamplifier circuit, full-wave rectifying circuit unit and filter circuit unit is made as Δ 1, Δ 2, Δ 3 respectively, total DC offset voltage on the described signal link is made as Δ offset, then has:
Δoffset＝Δa+Δ1+Δ2
In the present embodiment, the scope of Δ offset is between 3mV-15mV.
If described effective dc signal is Vrms, supply voltage is V
DD, when described preamplifier circuit does not have the signal input, then have:
Vrms＝Δoffset+V
DD/2
Steps A 002, judge whether to be effective dc signal that the noise upper threshold value that described noise Circuits System is set is Vnth_h, then work as
Judge this moment effective dc signal that need pick up, the voice audio signals of control output;
It is Vnth_1 that the noise lower threshold value is set, and then works as
Judging this moment does not have effective dc signal that need pick up, and forbids exporting voice audio signals.
When signal processing circuit unit is used, need when no input signal, measure the Vrms value and obtain Δ offset.After obtaining Δ offset, adjust Vnth_h and Vnth_1, can make thoroughly deserving with more accurate setting of the upper and lower threshold value of noise like this.
Step 5, described effective dc signal is exported to described comparator circuit unit it is accurately handled: the offset voltage that described comparator circuit unit is set is | Voffset|, it is Vref that one reference voltage is set, reference voltage Vref is switched between noise upper threshold value Vnth_h and noise lower threshold value Vnth_1 according to the state in steps A 002 of effective dc signal Vrms, wherein Vnth_h＞Vnth_1.Concrete, the mode that described effective dc signal Vrms switches between noise upper threshold value Vnth_h and noise lower threshold value Vnth_1 is:
When Vrms＞Vref=Vnth_h, described comparator circuit unit is output as high level signal, when the described first rising edge clock pulse arrived, described first d type flip flop sampled the high level signal of described comparator circuit unit output and exports first high level signal.When the rising edge pulse of described second clock arrived, described second d type flip flop sampled first high level signal of described first d type flip flop.Described first high level signal is divided into two paths of signals through after the described delay units delay, and wherein one road signal is again through forming narrow pulse signal with another road signal through after the described XOR gate calculation process after the delay units delay;
When Vrms＜Vref=Vnth_1, described comparator circuit unit is output as low level signal, when the described first rising edge clock pulse arrived, described first d type flip flop sampled the low level signal of described comparator circuit unit output and exports first low level signal.When the rising edge pulse of described second clock arrived, described second d type flip flop sampled first low level signal of described first d type flip flop.Described first low level signal is divided into two paths of signals through after the described delay units delay, and wherein one road signal is again through forming narrow pulse signal with another road signal through after the described XOR gate calculation process after the delay units delay.
Described generating circuit from reference voltage unit to the method to set up of reference voltage is: supply voltage is made as V
DD, power supply is to connecing n resistance between the ground, and n is even number, and then the dividing potential drop of each resistance is V
DD/ n, n/2 electric resistance partial pressure is V
DD/ 2, V
DD/ 2 the whole Noise gate Circuits System that namely can be provides direct current biasing.When surveying in to signal processing circuit unit, total offset voltage that then can get described whole Noise gate Circuits System is Vnoffset=|Vrms-V
DD/ 2|+|Voffset|, and satisfy-Vos＜Vnoffset＜+Vos, Vos is reference voltage.Vnth_1 can be 0 for the scope of repairing accent～-Vos, Vnth_h can be 0 for the scope of repairing accent～+ Vos, Vos=12mV.
In the present embodiment, concrete, generating circuit from reference voltage is set the value of Vnth_h and Vnth_1 earlier with multiselect one switch when surveying in to Noise gate circuit offset voltage.The value of setting several Vnth_h and Vnth_1 is adjusted the stepping accuracy of Vnth_h and Vnth_1.
Because operational amplifier and comparator imbalance voltage ratio that CMOS technology is made are bigger, offset voltage is between 2～5mv usually, and after the microphone electrical signal entered from preamplifier, it was superimposed upon on the dc level signal.Ideal situation, the DC current gain of operational amplifier are more than 100dB, and according to the empty short characteristic of amplifier, the AC signal value of its output should equal through AC signal and direct current biasing sum after the preamplifier amplification output.
The situation of introducing offset voltage mainly contains two kinds: one, the systematicness imbalance of introducing is set in two stage amplifer inner tube working point, can revise when design.Photoetching error when two, importing pipe manufacturer owing to the difference of operational amplifier, the etching environment is inconsistent, and the imbalance of introducing can reduce the pipe area by increasing the difference input, but can not eliminate.Thereby after being with the signal of telecommunication of making an uproar through preamplifier circuit unit, full-wave rectifying circuit unit and filter circuit unit, its offset voltage adds up step by step, and the total offset voltage of actual output that A is ordered among Fig. 1 is Vnoffse:
Vnoffse=Vrms+ direct current biasing V
DDTotal DC offset voltage Δ offset on the/2+ signal link
If the total offset voltage on the signal link reaches+10mv, and noise threshold is set at 10mv, the Noise gate circuit will can not play effect so.
Compare with correlation technique, the present invention is with common cmos operational amplifier, the simple logic circuit, and by the flat skew of detection comparator anode input dc power, going to change relatively then, reference level value Vref realizes accurate noise gate function.Not only method is simple for Noise gate Circuits System of the present invention and method for designing thereof, overcome the bigger shortcoming of cmos circuit offset voltage simultaneously, and circuit power consumption is low, and production cost is easy to integrated.
Above-described only is embodiments of the present invention, should be pointed out that for the person of ordinary skill of the art at this, under the prerequisite that does not break away from the invention design, can also make improvement, but these all belongs to protection scope of the present invention.
Claims (6)
1. Noise gate Circuits System, it comprises the signal of telecommunication is amplified the preamplifier circuit of processing and the signal processing circuit unit that the signal of telecommunication after amplifying is handled that it is characterized in that: described signal processing circuit unit is provided with:
The full-wave rectifying circuit unit comprises first operational amplifier, the make an uproar signal of telecommunication and it is play isolate and the buffering effect of the hum bar that be used for to receive described preamplifier circuit output; Second operational amplifier, the resistance and the diode that are electrically connected with second operational amplifier are used for the hum bar of described first operational amplifier output signal of telecommunication of making an uproar is carried out full-wave rectification and handles, and obtain the direct current band signal of telecommunication of making an uproar;
The filter circuit unit comprises the 3rd operational amplifier and the RC filter circuit that is electrically connected with described the 3rd operational amplifier, carries out the root mean square effective value for the signal of telecommunication that the direct current band of described full-wave rectifying circuit unit output is made an uproar and extracts;
The comparator circuit unit, comprise the delay cell that first clock circuit, the second clock circuit with the first clock non-overlapping copies, first d type flip flop that the sampling trigger impulse is provided and second d type flip flop, the sampled signal that described second d type flip flop is exported postpone and the XOR gate of the signal that postpones being carried out the XOR processing, described first clock circuit provides clock pulse for described first d type flip flop, described second clock circuit provides clock pulse for described second d type flip flop, is used for realizing the accurate comparison of signal;
The generating circuit from reference voltage unit, comprise resistance that even number is chained together and form noise threshold switch in parallel with each described resistance, for generation of reference voltage and export to described comparator circuit unit, also second operational amplifier for the comparator circuit unit provides direct current biasing.
2. Noise gate Circuits System according to claim 1, it is characterized in that: described first operational amplifier, second operational amplifier and the 3rd operational amplifier are made by CMOS technology.
3. Noise gate Circuits System according to claim 2 is characterized in that: described comparator circuit unit adopts the high-precision and low-offset voltage comparator, and its offset voltage is less than 1mV.
4. method for designing as right 3 described Noise gate Circuits System, it is characterized in that: this method comprises the steps:
Step 1, provide a microphone, receiving belt noise tone signal converts thereof into hum bar the make an uproar signal of telecommunication and output;
The make an uproar signal of telecommunication and it is amplified processing of step 2, the hum bar that receives the output of described microphone by described preamplifier circuit, the hum bar after obtaining the amplifying signal of telecommunication of making an uproar;
Step 3, receive the make an uproar signal of telecommunication and it is carried out full-wave rectification handle of hum bar after the described amplification by described full-wave rectifying circuit unit, obtain direct current band after the rectification signal of telecommunication of making an uproar;
Step 4, receive the make an uproar signal of telecommunication and it is carried out the root mean square effective value extract of described direct current band by the filter circuit unit, obtain effective dc signal, comprise the steps:
Steps A 001, described signal processing circuit unit is carried out middle survey, the DC offset voltage that obtains described preamplifier circuit, full-wave rectifying circuit unit and filter circuit unit is made as Δ 1, Δ 2, Δ 3 respectively, total DC offset voltage on the described signal link is made as Δ offset, then has:
Δoffset＝Δa+Δ1+Δ2
If described effective dc signal is Vrms, supply voltage is V
DD, when described preamplifier circuit does not have the signal input, then have:
Vrms＝Δoffset+V
DD/2
Steps A 002, judge whether to be effective dc signal that the noise upper threshold value that described noise Circuits System is set is Vnth_h, then work as
Judge this moment effective dc signal that need pick up, the voice audio signals of control output;
It is Vnth_l that the noise lower threshold value is set, and then works as
Judging this moment does not have effective dc signal that need pick up, and forbids exporting voice audio signals;
Step 5, described effective dc signal is exported to described comparator circuit unit it is accurately handled: the offset voltage that described comparator circuit unit is set is | Voffset|, it is Vref that one reference voltage is set, reference voltage Vref is switched between noise upper threshold value Vnth_h and noise lower threshold value Vnth_l according to the state in steps A 002 of effective dc signal Vrms, wherein Vnth_h＞Vnth_l.
5. the method for designing of Noise gate Circuits System according to claim 4, it is characterized in that: the mode that the described effective dc signal Vrms in the step 5 switches between noise upper threshold value Vnth_h and noise lower threshold value Vnth_l is:
As Vrms〉during Vref=Vnth_h, described comparator circuit unit is output as high level signal, when the described first rising edge clock pulse arrives, described first d type flip flop samples the high level signal of described comparator circuit unit output and exports first high level signal, when the rising edge pulse of described second clock arrives, described second d type flip flop samples first high level signal of described first d type flip flop, described first high level signal is divided into two paths of signals through after the described delay units delay, and wherein one road signal is again through forming narrow pulse signal with another road signal through after the described XOR gate calculation process after the delay units delay;
When Vrms＜Vref=Vnth_l, described comparator circuit unit is output as low level signal, when the described first rising edge clock pulse arrives, described first d type flip flop samples the low level signal of described comparator circuit unit output and exports first low level signal, when the rising edge pulse of described second clock arrives, described second d type flip flop samples first low level signal of described first d type flip flop, described first low level signal is divided into two paths of signals through after the described delay units delay, and wherein one road signal is again through forming narrow pulse signal with another road signal through after the described XOR gate calculation process after the delay units delay.
6. the method for designing of Noise gate Circuits System according to claim 5, it is characterized in that: described generating circuit from reference voltage unit to the method to set up of reference voltage is: supply voltage is made as V
DD, power supply is to connecing n resistance between the ground, and n is even number, and then the dividing potential drop of each resistance is V
DD/ n, n/2 electric resistance partial pressure is V
DD/ 2, V
DD/ 2 the whole Noise gate Circuits System that namely can be provides direct current biasing, and when surveying in to signal processing circuit unit, the offset voltage that then can get described whole Noise gate Circuits System is Vnoffset=|Vrms-V
DD/ 2|+|Voffset|, and satisfy-Vos＜Vnoffset＜+Vos, Vos is reference voltage.
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| CN102868956B (en) * | 2012-09-24 | 2015-02-11 | 深圳市纳芯威科技有限公司 | Noise gate circuit and voice frequency power amplification equipment |
| CN104703094B (en) * | 2014-12-26 | 2018-01-23 | 南京信息工程大学 | Utter long and high-pitched sounds detection suppression system and its control method based on MAX262 and FPGA |
| CN106331947B (en) * | 2015-06-30 | 2019-09-24 | 展讯通信（上海）有限公司 | A kind of codec chip and its method removing microphone DC level |
| KR102399724B1 (en) * | 2015-09-24 | 2022-05-20 | 삼성전자주식회사 | Display apparatus, Door and Refrigerator having the same |
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| JP4075167B2 (en) * | 1998-10-09 | 2008-04-16 | ソニー株式会社 | Digital signal reproduction apparatus and processing apparatus |
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2011
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1167391C (en) * | 1995-06-07 | 2004-09-22 | 加里·K·米切尔森 | Lordotic interbody spinal fusion implants |
| CN201285290Y (en) * | 2008-06-20 | 2009-08-05 | 伊玛精密电子（苏州）有限公司 | Signal processing circuit |
| CN101610140A (en) * | 2008-06-20 | 2009-12-23 | 华为技术有限公司 | Signal amplitude detection circuit and method |
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