CN102122092A - Display panel - Google Patents
Display panel Download PDFInfo
- Publication number
- CN102122092A CN102122092A CN 201110052305 CN201110052305A CN102122092A CN 102122092 A CN102122092 A CN 102122092A CN 201110052305 CN201110052305 CN 201110052305 CN 201110052305 A CN201110052305 A CN 201110052305A CN 102122092 A CN102122092 A CN 102122092A
- Authority
- CN
- China
- Prior art keywords
- weld pad
- testing weld
- layer
- loading end
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims description 63
- 238000009413 insulation Methods 0.000 claims description 33
- 230000001681 protective effect Effects 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- 239000000523 sample Substances 0.000 description 17
- 239000010409 thin film Substances 0.000 description 17
- 230000000694 effects Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 235000019994 cava Nutrition 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Images
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
A display panel comprises a substrate, a pixel array and a test pad. The substrate has a carrying surface, and the substrate has a display area and a peripheral circuit area located at the periphery of the display area. The pixel array is configured on the bearing surface and is positioned in the display area. The test pad is configured on the bearing surface and is positioned in the peripheral circuit area. The test pad is electrically connected to the pixel array. The test pad includes a central portion and a peripheral portion surrounding the central portion, wherein the height of the peripheral portion is greater than the height of the central portion, and the peripheral portion has a plurality of first trenches. The first groove exposes the carrying surface.
Description
Technical field
The invention relates to a kind of display panel, and particularly relevant for a kind of display panel with testing weld pad.
Background technology
Common on the market now display panel, as display panels, can be divided into viewing area (displayregion) and perimeter circuit district (peripheral circuit region), wherein in the viewing area, dispose a plurality of pixel cells of arrayed, to show the picture frame picture by pixel cell.The driver that electrically connects those pixel cells and measurement circuit etc. are set, to drive those pixel cells or those pixel cells are carried out electrical detection in the perimeter circuit district.By electrical detection, can judge that pixel cell could normal operation.When pixel cell can't normal operation, just can repair for bad element (as thin film transistor (TFT) or pixel electrode etc.) or circuit.
The mode of electrical detection is normally with the testing weld pad of probe engaged test circuit, to each pixel cell, and observes the whether normal operation of each pixel cell with input test signal.Yet, be limited to existing test pad structure, when probe contacts with testing weld pad, probe is shifted out outside the testing weld pad at testing weld pad surface slip beat, cause the element of substrate surface to be damaged by the probe bump or the circuit of substrate surface by accidents such as probe scratches.
Summary of the invention
The invention provides a kind of display panel, is that the structure of testing weld pad is changed, and stablizing the position of probe on testing weld pad, and helps to improve test yield and test accuracy.
Hold for specifically describing within the present invention, propose a kind of display panel, comprise a substrate, a pel array and a testing weld pad at this.Substrate has a loading end, and the substrate one perimeter circuit district that can divide a viewing area and be positioned at the periphery, viewing area.Pixel array configuration and is positioned at the viewing area on loading end.Testing weld pad is disposed on the loading end, and is positioned at the perimeter circuit district.Testing weld pad is electrically connected to pel array.Testing weld pad comprises a middle body and around a periphery of middle body, and wherein the height of periphery is greater than the height of middle body, and periphery has a plurality of first grooves (trench).First groove exposes loading end.
In one of the present invention embodiment, described display panel more comprises a plurality of backstop ribs, is disposed on the loading end, and is positioned at the outside of testing weld pad.In one of the present invention embodiment, the height of backstop rib is greater than the height of the periphery of testing weld pad.In one of the present invention embodiment, have one second groove between each backstop rib that testing weld pad is adjacent, and second groove exposes loading end.In one of the present invention embodiment, the backstop rib is parallel to each other, and along a side setting of testing weld pad.In one of the present invention embodiment, have one the 3rd groove between two backstop ribs that are parallel to each other and expose loading end.In one of the present invention embodiment, testing weld pad comprises a first metal layer, a gate insulation layer, one second metal level and a transparent electrode layer.The first metal layer is disposed on the loading end, and the first metal layer comprises a first and a second portion that centers on first.Gate insulation layer is disposed on the second portion of the first metal layer, and exposes the first of the first metal layer.Second metal level is disposed on the gate insulation layer.Transparent electrode layer covers the first of second metal level and the first metal layer.In one of the present invention embodiment, the backstop rib comprises a first metal layer, a gate insulation layer, semi-conductor layer, one second metal level, a protective seam and a transparent electrode layer.The first metal layer is disposed on the loading end.Gate insulation layer is disposed on the first metal layer.Semiconductor layer is disposed on the gate insulation layer.Second metal level is disposed on the semiconductor layer.Protective seam is disposed on second metal level.Transparent electrode layer covers second metal level.In one of the present invention embodiment, the gate insulation layer of described backstop rib more extends two opposing sidewalls and the outer part loading end of two opposite side walls that covers the first metal layer.In one of the present invention embodiment, the protective seam of described backstop rib more extend two opposing sidewalls covering second metal level, semiconductor layer two opposing sidewalls, be positioned at the gate insulation layer on two opposing sidewalls of the first metal layer and be positioned at gate insulation layer on the loading end.
Based on above-mentioned, the present invention is provided with first groove of a plurality of exposure loading ends at the periphery of testing weld pad, skids off when avoiding probe to contact with contact mat outside the contact mat and destroys other elements on the substrate.In addition, the present invention can also be at a plurality of backstop ribs of the arranged outside of testing weld pad, to strengthen the contained effect to probe by the height offset between backstop rib and the testing weld pad and second groove between backstop rib and testing weld pad and the 3rd groove.Therefore, can effectively improve test yield and test accuracy.
State feature and advantage on the present invention and can become apparent for allowing, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Fig. 1 is the synoptic diagram and the partial enlarged drawing thereof of a kind of display panels of embodiment one of according to the present invention.
Fig. 2 A is the top view of the testing weld pad of Fig. 1.
Fig. 2 B is the sectional view of the testing weld pad of Fig. 1.
Fig. 3 A and Fig. 3 B illustrate the top view and the sectional view of the testing weld pad of another embodiment according to the present invention respectively.
[main element symbol description]
100: display panels 102: viewing area
104: perimeter circuit district 110: pel array
112: pixel cell 120: testing weld pad
122: the middle body 124 of testing weld pad: the periphery of testing weld pad
130: 152: the first grooves of backstop rib
156: the three grooves of 154: the second grooves
190: substrate 192: the loading end of substrate
H1: the height of the middle body of testing weld pad
H2: the height of the periphery of testing weld pad
H3: the height P of backstop rib: probe
210: the first metal layer 220: gate insulation layer
250: semiconductor layer 260: protective seam
320: testing weld pad 330: the backstop rib
390: substrate 392: the loading end of substrate
410: the first metal layer 412: the sidewall of the first metal layer
420: 430: the second metal levels of gate insulation layer
The sidewall 450 of 432: the second metal levels: semiconductor layer
452: the sidewall 460 of semiconductor layer: protective seam
Embodiment
Display panel of the present invention can be display panels, organic electroluminescence panel etc. show the picture frame picture by pel array all types of display panels.Below will be that example illustrates the actual framework that testing weld pad design of the present invention is applied thereon with the display panels.
Fig. 1 is according to the synoptic diagram of a kind of display panels of one of the present invention embodiment and partial enlarged drawing thereof.As shown in Figure 1, the display panels 100 perimeter circuit district 104 that has viewing area 102 and be positioned at 102 peripheries, viewing area.Have the pel array 110 that constitutes by a plurality of pixel cells 112 in the viewing area 102, and have one or more testing weld pad 120 that is electrically connected to pel array 110 in the perimeter circuit district 104.
Generally speaking, display panels 100 is made up of thin-film transistor array base-plate, subtend substrate and the liquid crystal layer that is folded between two substrates, and aforesaid pixel cell 112 can comprise thin film transistor (TFT), pixel electrode, the liquid crystal molecule of liquid crystal layer and the common electrode on the subtend substrate etc. that are positioned on the thin-film transistor array base-plate.Those skilled in the art of the present technique should understand the structure of aforementioned component element and make flowing mode, do not give unnecessary details one by one herein.
When detecting, probe P engaged test pad 120 with input test signal each pixel cell 112 to the pel array 110, and is observed whether normal operation of each pixel cell 112.
Hereinafter be described further with single testing weld pad 120.Fig. 2 A is the top view of the testing weld pad 120 of Fig. 1, and Fig. 2 B is the sectional view of testing weld pad 120.Shown in Fig. 2 A and 2B, testing weld pad 120 is disposed at the loading end 192 of substrate 190.This substrate 190 for example is the glass substrate of thin-film transistor array base-plate side, and described testing weld pad 120 for example be with thin-film transistor array base-plate on each element make jointly.In other words, on substrate 190, deposit a plurality of material layers and those material layers are carried out patterning (light shield) processing procedure, in the time of with formation thin film transistor (TFT) and pixel electrode, also in perimeter circuit district 104, optionally stack those material layers, to constitute the testing weld pad 120 of present embodiment.
Refer again to Fig. 2 A and 2B, the testing weld pad 120 of present embodiment comprises a middle body 122 and a periphery 124 that centers on middle body 122.The height H 2 of periphery 124 is greater than the height H 1 of middle body 122, and with the structure of formation concavity, and periphery 124 has a plurality of first grooves 152.Those first grooves 152 can run through the periphery 124 of testing weld pad 120, and expose the loading end 192 of substrate 190.
The position that the testing weld pad 120 that middle body 122 caves in relatively can be stablized probe P to a certain extent, and because present embodiment is provided with a plurality of first grooves 152 at the periphery 124 of testing weld pad 120, and the degree of depth of first groove 152 is directed reach the loading end 192 of substrate 190, therefore can form enough differences in height on the topographical surface of testing weld pad 120.When probe P outwards slided on contact mat 120 surfaces, the tip of probe P can enter in first groove 152, and by first groove, 152 generations contained effect to a certain degree.
In addition, present embodiment more optionally is provided with a plurality of backstop ribs 130 on the loading end 192 in testing weld pad 120 outsides.The height H 3 of described backstop rib 130 is at least more than or equal to the height H 2 of the periphery 124 of testing weld pad 120, even therefore probe P has overcome the contained effect of first groove 152, still can stop probe P to continue by backstop rib 130 to testing weld pad 120 outside moving.Moreover, have second groove 154 between the backstop rib 130 that testing weld pad 120 is adjacent.This second groove 154 also can expose the loading end 192 of substrate 190, similarly restrains effect to provide with aforementioned first groove 152.
On the other hand, the not position and the quantity of limit stop rib 130 of the present invention.In the present embodiment, the bearing of trend of backstop rib 130 can be parallel to each other in fact with the edge of testing weld pad 120, and the backstop rib 130 that is provided with more than two and is parallel to each other on the same side of testing weld pad 120.Wherein, can form the 3rd groove 156 between two backstop ribs 130 that are parallel to each other.Described the 3rd groove 156 also can expose the loading end 192 of substrate 190, similarly restrains effect to provide with aforementioned first groove 152 and second groove 154.
In addition, carry as preamble, the testing weld pad 120 of present embodiment can be made jointly with each element on the thin-film transistor array base-plate, to save technological process.That is, the testing weld pad 120 of present embodiment can be made up of each material layer in the existing thin-film transistor array base-plate processing procedure.For example, the testing weld pad 120 of present embodiment has just comprised the first metal layer 210, gate insulation layer 220, second metal level 230 and transparent electrode layer 240.The first metal layer 210 is disposed on the loading end 192 of substrate 190 corresponding to the gate material layers in the thin film transistor (TFT).The first metal layer 210 comprises first 212 and the second portion 214 that centers on first 212.Gate insulation layer 220 is corresponding to the gate insulation layer of cover gate in the thin film transistor (TFT).Gate insulation layer 220 is disposed on the second portion 214 of the first metal layer 210, and exposes the first 212 of the first metal layer 210.Second metal level 230 is corresponding to the source electrode material layer in the thin film transistor (TFT), and second metal level 230 is disposed on the gate insulation layer 220.Transparent electrode layer 240 is corresponding to the pixel electrode layer on the thin-film transistor array base-plate, and transparent electrode layer 240 covers the first 212 of second metal level 230 and the first metal layer 210.Therefore, can constitute testing weld pad 120.In other words, the middle body 122 of testing weld pad 120 is to be stacked by the first metal layer 210 and transparent electrode layer 240 to form, and the periphery 124 of testing weld pad 120 is to be stacked by the first metal layer 210, gate insulation layer 220, second metal level 230 and transparent electrode layer 240 to form, so both have different height.
In addition, backstop rib 130 also can be made jointly with each element on the thin-film transistor array base-plate, and is made up of each material layer in the existing thin-film transistor array base-plate processing procedure.The backstop rib 130 of present embodiment comprises aforementioned the first metal layer 210, aforementioned gate insulation layer 220, semi-conductor layer 250, second metal layers 230, a protective seam 260 and aforementioned transparent electrode layer 240.For the height H 3 that improves backstop rib 130, present embodiment has more increased semiconductor layer 250 and protective seam 260 in laminated except the rete that the periphery 124 of testing weld pad 120 is had.Semiconductor layer 250 is corresponding to the active layers in the thin film transistor (TFT), and semiconductor layer 250 is disposed between the gate insulation layer 220 and second metal level 230.Protective seam 260 corresponding in the thin-film transistor array base-plate in order to the transistorized protective seam of cover film, and protective seam 260 is disposed between second metal level 230 and the transparent electrode layer 240.
The periphery 124 of the testing weld pad 120 of present embodiment has first groove 152 of a plurality of exposure loading ends 192, skids off when avoiding probe P to contact with contact mat 120 outside the contact mat 120 and destroys other elements on the substrate 190.In addition, present embodiment also can be at a plurality of backstop ribs 130 of the arranged outside of testing weld pad 120, to strengthen the contained effect to probe P by the height offset between backstop rib 130 and the testing weld pad 120 and second groove 154 between backstop rib 130 and testing weld pad 120 and the 3rd groove 156.Therefore, can effectively improve test yield and test accuracy.
Fig. 3 A and Fig. 3 B illustrate top view and the sectional view according to the testing weld pad of another embodiment of the present invention more respectively.The testing weld pad 320 of present embodiment is similar with the testing weld pad 120 of previous embodiment; except: present embodiment causes the metal level oxidation of backstop rib 330 or other retes to go bad for fear of extraneous aqueous vapor or foreign matter; when gate insulation layer 420 that defines backstop rib 330 and protective seam 460, more make gate insulation layer 420 and protective seam 460 cover the sidewall of below rete respectively.More specifically, the gate insulation layer 420 of backstop rib 330 can extend the part loading end 392 of the outer substrate 390 of two opposing sidewalls 412 covering the first metal layers 410 and two opposite side walls 412.In addition, the protective seam 460 of backstop rib 330 can extend two opposing sidewalls 432 covering second metal level 430, semiconductor layer 450 two opposing sidewalls 452, be positioned at the gate insulation layer 420 on two opposing sidewalls 412 of the first metal layer 410 and be positioned at gate insulation layer 420 on the loading end 392 of substrate 390.
Extension by gate insulation layer 420 and protective seam 460 can make the first metal layer 410, second metal level 430 and semiconductor layer 450 be isolated from the outside, with protection backstop rib 330.
Certainly, other parts of the testing weld pad 320 of present embodiment also can adopt identical design, gate insulation layer 420 and protective seam 460 are extended cover the specific rete that needs protection, to keep the normal operation of testing weld pad 320.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the invention; when doing a little change and retouching, so the present invention's protection domain attached claim person of defining after looking is as the criterion.
Claims (10)
1. display panel comprises:
One substrate has a loading end, the perimeter circuit district that this substrate has a viewing area and is positioned at this periphery, viewing area;
One pel array is disposed on this loading end, and is positioned at this viewing area; And
One testing weld pad, be disposed on this loading end, and be positioned at this perimeter circuit district, this testing weld pad is electrically connected to this pel array, this testing weld pad comprises a middle body and a periphery that centers on this middle body, wherein the height of this periphery is greater than the height of this middle body, and this periphery has a plurality of first grooves, and described first groove exposes this loading end.
2. display panel as claimed in claim 1 is characterized in that further comprising a plurality of backstop ribs, is disposed on this loading end, and is positioned at the outside of this testing weld pad.
3. display panel as claimed in claim 2 is characterized in that: the height of described backstop rib is greater than the height of this periphery of testing weld pad.
4. display panel as claimed in claim 2 is characterized in that: have one second groove between each backstop rib that this testing weld pad is adjacent, this second groove exposes this loading end.
5. display panel as claimed in claim 2 is characterized in that: the described backstop rib of part is parallel to each other, and along a side setting of this testing weld pad.
6. display panel as claimed in claim 5 is characterized in that: have one the 3rd groove between two backstop ribs that are parallel to each other and expose this loading end.
7. display panel as claimed in claim 1 is characterized in that: this testing weld pad comprises:
One the first metal layer is disposed on this loading end, and this first metal layer comprises a first and a second portion that centers on this first;
One gate insulation layer is disposed on this second portion of this first metal layer, and exposes this first of this first metal layer;
One second metal level is disposed on this gate insulation layer; And
One transparent electrode layer covers this first of this second metal level and this first metal layer.
8. display panel as claimed in claim 2 is characterized in that: this backstop rib comprises:
One the first metal layer is disposed on this loading end;
One gate insulation layer is disposed on this first metal layer;
Semi-conductor layer is disposed on this gate insulation layer;
One second metal level is disposed on this semiconductor layer;
One protective seam is disposed on this second metal level; And
One transparent electrode layer covers this second metal level.
9. display panel as claimed in claim 8 is characterized in that: this gate insulation layer further extends two opposing sidewalls and outer this loading end of part of this two opposite side walls that covers this first metal layer.
10. display panel as claimed in claim 9 is characterized in that: this protective seam more extend two opposing sidewalls covering this second metal level, this semiconductor layer two opposing sidewalls, be positioned at this gate insulation layer on these two opposing sidewalls of this first metal layer and be positioned at this gate insulation layer on this loading end.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099145913 | 2010-12-24 | ||
| TW99145913A TWI416233B (en) | 2010-12-24 | 2010-12-24 | Display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102122092A true CN102122092A (en) | 2011-07-13 |
| CN102122092B CN102122092B (en) | 2013-04-03 |
Family
ID=44250672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110052305 Expired - Fee Related CN102122092B (en) | 2010-12-24 | 2011-03-02 | Display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102122092B (en) |
| TW (1) | TWI416233B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187017A (en) * | 2011-12-30 | 2013-07-03 | 三星显示有限公司 | Aging system used for display device and aging method employing aging system |
| CN107390114A (en) * | 2017-08-31 | 2017-11-24 | 惠科股份有限公司 | Circuit board and test point structure thereof |
| CN109671757A (en) * | 2018-12-18 | 2019-04-23 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN110402014A (en) * | 2019-07-22 | 2019-11-01 | Oppo（重庆）智能科技有限公司 | The circuit board and electronic equipment of electronic equipment |
| CN112230483A (en) * | 2020-09-23 | 2021-01-15 | 惠科股份有限公司 | Array substrate, display panel and large glass panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11183920A (en) * | 1997-10-14 | 1999-07-09 | Canon Inc | Color liquid crystal element and manufacturing method thereof |
| US20020085169A1 (en) * | 2000-12-30 | 2002-07-04 | Choi Gyo Un | Liquid crystal display for testing defects of wiring in panel |
| US20030122975A1 (en) * | 2001-12-29 | 2003-07-03 | Jeong-Rok Kim | Liquid crystal display device formed on glass substrate having improved efficiency |
| US7129520B2 (en) * | 2000-12-29 | 2006-10-31 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device with a test pad for testing plural shorting bars |
| JP2008026497A (en) * | 2006-07-19 | 2008-02-07 | Seiko Epson Corp | Optical panel, inspection probe, inspection device, and inspection method |
| US7692753B2 (en) * | 2005-10-25 | 2010-04-06 | Lg. Display Co., Ltd. | Flat panel display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020016070A1 (en) * | 2000-04-05 | 2002-02-07 | Gerald Friese | Power pads for application of high current per bond pad in silicon technology |
| TWI368779B (en) * | 2008-02-15 | 2012-07-21 | Chunghwa Picture Tubes Ltd | Peripheral circuit |
| TWI366019B (en) * | 2008-03-21 | 2012-06-11 | Au Optronics Corp | A panel test circuit structure |
| TW201022772A (en) * | 2008-12-01 | 2010-06-16 | Chi Mei Optoelectronics Corp | Liquid crystal display substrate and electrical testing method thereof |
-
2010
- 2010-12-24 TW TW99145913A patent/TWI416233B/en not_active IP Right Cessation
-
2011
- 2011-03-02 CN CN 201110052305 patent/CN102122092B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11183920A (en) * | 1997-10-14 | 1999-07-09 | Canon Inc | Color liquid crystal element and manufacturing method thereof |
| US7129520B2 (en) * | 2000-12-29 | 2006-10-31 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device with a test pad for testing plural shorting bars |
| US20020085169A1 (en) * | 2000-12-30 | 2002-07-04 | Choi Gyo Un | Liquid crystal display for testing defects of wiring in panel |
| US20030122975A1 (en) * | 2001-12-29 | 2003-07-03 | Jeong-Rok Kim | Liquid crystal display device formed on glass substrate having improved efficiency |
| US7692753B2 (en) * | 2005-10-25 | 2010-04-06 | Lg. Display Co., Ltd. | Flat panel display device |
| JP2008026497A (en) * | 2006-07-19 | 2008-02-07 | Seiko Epson Corp | Optical panel, inspection probe, inspection device, and inspection method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187017A (en) * | 2011-12-30 | 2013-07-03 | 三星显示有限公司 | Aging system used for display device and aging method employing aging system |
| CN107390114A (en) * | 2017-08-31 | 2017-11-24 | 惠科股份有限公司 | Circuit board and test point structure thereof |
| CN109671757A (en) * | 2018-12-18 | 2019-04-23 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| US10923554B2 (en) | 2018-12-18 | 2021-02-16 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and display device |
| CN110402014A (en) * | 2019-07-22 | 2019-11-01 | Oppo（重庆）智能科技有限公司 | The circuit board and electronic equipment of electronic equipment |
| CN112230483A (en) * | 2020-09-23 | 2021-01-15 | 惠科股份有限公司 | Array substrate, display panel and large glass panel |
| CN112230483B (en) * | 2020-09-23 | 2021-10-01 | 惠科股份有限公司 | Array substrate, display panel and large glass panel |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201227113A (en) | 2012-07-01 |
| TWI416233B (en) | 2013-11-21 |
| CN102122092B (en) | 2013-04-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20090174681A1 (en) | Liquid crystal display panel and touch panel therefor | |
| JP7370375B2 (en) | Display devices and semiconductor devices | |
| CN102122092B (en) | Display panel | |
| US20180373079A1 (en) | Display panel and manufacturing method thereof | |
| US9035317B2 (en) | Pixel structure, display panel and method for fabricating pixel structure | |
| US7724019B2 (en) | Active device array substrate | |
| US8508709B2 (en) | Method of repairing pixel structure, repaired pixel structure and pixel array | |
| US9638963B2 (en) | Display device | |
| US10281772B2 (en) | Liquid crystal display panel | |
| US10282005B2 (en) | Touch display panel, manufacturing method and detecting method for the same | |
| US7999265B2 (en) | Photoelectric conversion device, electro-optic device, and electronic device | |
| CN109725450B (en) | Display panel and manufacturing method thereof | |
| GB2517806A (en) | Liquid crystal display device and method of fabricating the same | |
| JP2007226176A (en) | Thin-film transistor array substrate and electronic ink display device | |
| EP3229067A1 (en) | Array substrate, repairing patch, display panel, and method for repairing array substrate | |
| US10783840B2 (en) | Display panel having a test line therein | |
| US20120262658A1 (en) | Lead line structure and display panel having the same | |
| US20180224684A1 (en) | Touch display device | |
| TW201606407A (en) | Array substrate and display having the same | |
| KR20160056389A (en) | Array substrate having photo sensor and display device using the same | |
| JP2007140440A (en) | Electronic ink display device | |
| US20140362303A1 (en) | Touch display panel and manufacturing method thereof | |
| US20220223627A1 (en) | Display panel | |
| TWI531837B (en) | Device substrate and aligning method thereof | |
| KR20140086395A (en) | Liquid crystal display device and Method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130403 Termination date: 20210302 |