A kind of protective circuit with bound function
Technical field
The present invention relates to a kind of motor in electric automobile control device, especially relate to a kind of protective circuit on this device with bound function.
Background technology
Along with the contradiction of energy resource structure and fuel-engined vehicle air pollution aspect becomes increasingly conspicuous, electric automobile is more and more accepted by people with advantages such as its zero discharge, low noises.As electric automobile, its fail safe can not be lower than orthodox car, ensures the core component of electric automobile cruising, and it is particularly important that the reliability of electric machine controller and fail safe just become.
At present, electric automobile extensively adopts permagnetic synchronous motor as drive motors, the rotating band motor-car body that motor controller controls permagnetic synchronous motor travels, but because certain foeign element such as system's overvoltage, overcurrent or fault such as under-voltage are when taking place, directly damaging the three-phase brachium pontis sometimes makes the motor three-phase be in off state, this is extremely dangerous for the electric automobile of running at high speed, and handles timely and certainly will will threaten to traffic safety and even personal safety if controller can not be made.
At present, prior art is still far from perfect for the defencive function of electric machine controller, mainly has following several respects deficiency:
1. existing product has all only been done restriction processing, not overcurrent, overvoltage and under-voltage fault turn-off function by DSP to system power, voltage in software.
2. the software current limliting only is fit to FEEDBACK CONTROL usefulness, but unusual over-current signal can not be caught and good restraining timely.
3. what the seizure during at present to current anomaly was adopted is that positive half cycle crest detects, and promptly the upper limit that the overcurrent of AC signal is only got positive half cycle crest can not process the negative half period trough of AC signal as processing.
4. the logical circuit that has pair the problems referred to above to handle it in the existing scheme, but complex structure, device is many, has increased fault point and cost on the contrary.
5. existing product can not be done abnormal failure and latch demonstration at present, often can not judge concrete what fault when disappearing again after system breaks down moment, and it is unfavorable that product maintenance analysis is brought.
The content of invention
The present invention provides the protective circuit with bound function on a kind of motor in electric automobile control device in order to overcome deficiency of the prior art.
The present invention solves the technical scheme that its technical problem takes: the present invention is by A (DSP minimum system), B (U phase current transducer), C (V phase current transducer), D (W phase current transducer), E (voltage sensor), F (U phase current bound fault logic circuits), G (V phase current bound fault logic circuits), H (W phase current bound fault logic circuits), I (voltage bound fault logic circuits), J (CPLD logical device), K (failure indicating circuit), L (three-phase brachium pontis drive circuit) 12 parts are formed.The present invention has realized the quick response and the processing of faults such as overvoltage, under-voltage, overcurrent by devices at full hardware, avoided software to occur in time following the tracks of or the hidden danger such as deadlock during system exception.Improved protection class simultaneously, made security of system higher.
Described a kind of protective circuit with bound function; the three-phase current signal of permagnetic synchronous motor obtains analog signal by three current sensors (B, C, D); deliver to three electric current bound fault logic circuits (F, G, H) that circuit form is identical respectively, over-current signal is delivered to CPLD (J) after being converted into high-low level (1,2,3,4,5,6).The system voltage signal by voltage sensor (E) deliver to circuit form with voltage bound fault logic circuits (I) the output overvoltage signal of electric current bound fault logic circuits and under-voltage signal (7,8) to CPLD (J).All fault-signals that CPLD (J) will import carry out exporting three road signals behind the logical AND, and the fault that one road signal (10) does limit priority for DSP task manager (PDPINT) is interrupted; Another road signal (16) is a three-phase brachium pontis SHUTDOWN signal, does road shutoff processing up and down for the drive circuit (L) of three-phase brachium pontis, avoids permagnetic synchronous motor triple line risk of short-circuits situation to take place; Last road signal (11,12,13,14,15) is given failure indicating circuit (K), CPLD can handle and LED by failure indicating circuit shows fault latch when any fault takes place, import reset signal (17) up to DSP to CPLD, CPLD just can remove the fault-signal that latchs.The whole protecting circuit is not when moving, and in the time of need exporting SHUTDOWN (9) signal as DSP for the control purposes, CPLD only can finish control with this signal on three-phase brachium pontis SHUTDOWN signal.
Described a kind of protective circuit with bound function, crest OIU, trough OIU, crest OIV, trough OIV, crest OIW, trough OIW, OVER V, UNDER V.These signals are sent into CPLD and are done logical AND, promptly the delay circuit that the 44 pin output low level R2 of CPLD and C5 constitute when any one the has fault PDPINT pin of delivering to DSP is done the fault Interrupt Process, and the SHUTDOWN pin that the high level of 43 pin of CPLD output is simultaneously delivered to three-phase brachium pontis drive circuit turn-offs three-phase brachium pontis power drive part.When 13 pin of CPLD were received SHUTDOWN signal from DSP, 43 pin of CPLD can be exported high level equally and turn-off three-phase brachium pontis power drive part to the SHUTDOWN pin of three-phase brachium pontis drive circuit.The different faults signal of receiving according to 14,15,18,19,20,21,22,23 pin of CPLD, CPLD judges and to belong to what fault, and the LED (D1, D2, D3, D4, D5) of 2,3,5,6,8 pin by being connected on CPLD behind this fault latch is shown.When receiving reset signal from DSP, remove on 12 pin of CPLD the malfunction that latchs.
The present invention compared with prior art, the performance of its beneficial effect is as follows:
1, realizes the quick response and the processing of faults such as overvoltage, under-voltage, overcurrent by devices at full hardware, avoided software to occur in time to follow the tracks of or the hidden danger such as deadlock during system exception.
2, the bound function protection circuit all detects the positive-negative half-cycle of AC signal, promptly all can catch processing at the full-time territory of electric current overcurrent, has improved protection class, and security of system is higher.
3, the whole protecting circuit is only formed with 4 comparators and 1 44 pin CPLD Programmable Logic Device, and circuit is simple and reliable, and cost is low, failure rate is few.
4, occur when unusual in system, even the very fast removing of fault, this protective circuit also can continue before the indication what fault to have taken place, and receives reset signal up to this faulty circuit and just removes the faulty indication that latchs, and greatly facilitates production debugging and maintenance.
Description of drawings
Fig. 1 is the schematic diagram with bound function protection circuit of the present invention;
Fig. 2 is bound fault logic circuits figure of the present invention;
Fig. 3 is the peripheral concrete schematic diagram of implementing of CPLD of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described further:
As Fig. 1, planning principle figure, it is made up of A (DSP minimum system), B (U phase current transducer), C (V phase current transducer), D (W phase current transducer), E (voltage sensor), F (U phase current bound fault logic circuits), G (V phase current bound fault logic circuits), H (W phase current bound fault logic circuits), I (voltage bound fault logic circuits), J (CPLD logical device), K (failure indicating circuit), L (three-phase brachium pontis drive circuit) 12 parts.
The three-phase current signal of permagnetic synchronous motor obtains analog signal by three current sensors (B, C, D among Fig. 1), deliver to three electric current bound fault logic circuits (F, G, H among Fig. 1) that circuit form is identical respectively, over-current signal is delivered to CPLD (J) after being converted into high-low level (among Fig. 11,2,3,4,5,6).The system voltage signal by voltage sensor (E) deliver to circuit form with voltage bound fault logic circuits (I) the output overvoltage signal of electric current bound fault logic circuits and under-voltage signal (among Fig. 17,8) to CPLD (J).All fault-signals that CPLD (J) will import carry out output three road signals behind the logical AND, and the fault that one road signal (among Fig. 1 10) does limit priority for DSP task manager (PDPINT) is interrupted; Another road signal (among Fig. 1 16) is a three-phase brachium pontis SHUTDOWN signal, does up and down the road for the drive circuit (L) of three-phase brachium pontis and turn-offs and handle, and avoids permagnetic synchronous motor triple line risk of short-circuits situation to take place; Last road signal (among Fig. 1 11,12,13,14,15) is given failure indicating circuit (K), CPLD can handle and LED by failure indicating circuit shows fault latch when any fault takes place, import reset signal (17) up to DSP to CPLD, CPLD just can remove the fault-signal that latchs.The whole protecting circuit is not when moving, and in the time of need exporting SHUTDOWN (9) signal as DSP for the control purposes, CPLD only can finish control with this signal on three-phase brachium pontis SHUTDOWN signal.
As Fig. 2, this bound fault logic circuits can be used on the detection of the peak value and the valley of any same signal source, and the upper and lower bound value is judged.As shown in Figure 1, this circuit has been used in four places (F, G, H, I) simultaneously, and F is that U phase current bound is judged, G is that V phase current bound is judged, H is that W phase current bound is judged, I judges for the voltage bound.
Concrete operation principle is as follows: the dividing potential drop of R1 and R2 is set on the higher limit of current sensor output valve, delivers to in-phase input end 5 pin of comparator U1A; The dividing potential drop of R6 and R7 is set on the lower limit of current sensor output valve, delivers to in-phase input end 7 pin of another comparator U1B; The output of current sensor divides two-way, and inverting input 4 pin of U1A are delivered in one tunnel process R5, C2 filtering; Inverting input 6 pin of U1B are delivered on another road through R10, C4 filtering; When the input signal of current sensor is higher than the higher limit of R1 and the setting of R2 dividing potential drop; the inverting input 4 pin current potentials of U1A are than the in-phase end 5 pin height of U1A; comparator U1A output pin 2 upset output low levels then; 2 pin of U1A are with the end ground connection of R3 at this moment; the other end is connected on the dividing point of R1 and R2, and the higher limit of current sensor output valve is reduced, and has further widened the pressure reduction of comparator U1A input; make output level more stable, protect more reliable.When the input signal of current sensor is lower than the lower limit of R6 and the setting of R7 dividing potential drop; the inverting input 6 pin current potentials of U1B are lower than in-phase end 7 pin of U1B; then high level is exported in 1 upset of comparator U1B output pin; 1 pin of U1B is with the end ground connection of R8 at this moment; the other end is connected on the dividing point of R6 and R7; the lower limit of current sensor output valve is reduced; further widened the pressure reduction of comparator U1B input; make output level more stable; protect more reliably, misoperation can not take place and be interfered.
Learn that from top principle when measured signal was in normal interval, U1A exported high level, U1B output low level; When prescribing a time limit U1A output low level, U1B output low level above last; When being lower than down in limited time, U1A exports high level, and U1B exports high level; The logic level of U1A output pin and U1B output pin is delivered to respectively among the CPLD, and in like manner, voltage bound decision circuitry principle is same as above, and also the decision logic level is sent among the CPLD.
As Fig. 3, be the peripheral concrete schematic diagram of implementing of CPLD, bound fault logic circuits recited above one shared 4, wherein every all produces two-way decision logic level, one is upper limit fault, one is the lower limit fault, always has 8 the tunnel, is respectively crest OIU, trough OIU, crest OIV, trough OIV, crest OIW, trough OIW, OVERV, UNDER V.These signals are sent into CPLD and are done logical AND, promptly the delay circuit that the 44 pin output low level R2 of CPLD and C5 constitute when any one the has fault PDPINT pin of delivering to DSP is done the fault Interrupt Process, and the SHUTDOWN pin that the high level of 43 pin of CPLD output is simultaneously delivered to three-phase brachium pontis drive circuit turn-offs three-phase brachium pontis power drive part.When 13 pin of CPLD were received SHUTDOWN signal from DSP, 43 pin of CPLD can be exported high level equally and turn-off three-phase brachium pontis power drive part to the SHUTDOWN pin of three-phase brachium pontis drive circuit.The different faults signal of receiving according to 14,15,18,19,20,21,22,23 pin of CPLD, CPLD judges and to belong to what fault, and the LED (D1, D2, D3, D4, D5) of 2,3,5,6,8 pin by being connected on CPLD behind this fault latch is shown.When receiving reset signal from DSP, remove on 12 pin of CPLD the malfunction that latchs.
Utilize technical solutions according to the invention, or those skilled in the art designing the similar techniques scheme under the inspiration of technical solution of the present invention, and reach above-mentioned technique effect, all is to fall into protection scope of the present invention.