CN102110474A - Device and method for performing erasing operation on storage integrated circuit - Google Patents
Device and method for performing erasing operation on storage integrated circuit Download PDFInfo
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- CN102110474A CN102110474A CN2009102656141A CN200910265614A CN102110474A CN 102110474 A CN102110474 A CN 102110474A CN 2009102656141 A CN2009102656141 A CN 2009102656141A CN 200910265614 A CN200910265614 A CN 200910265614A CN 102110474 A CN102110474 A CN 102110474A
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Abstract
The invention discloses a device and a method for performing erasing operation on a nonvolatile storage integrated circuit. The method comprises the following steps of: performing erasing verification during the erasing operation; and performing grouping improvement on edge word lines and central word lines of an erasing group during erasing sub-operation. In another scheme, voltage classes of the edge word lines are changed to solve the problem of excessive erasing of the erasing group, and the expression of erasing time can be improved. In other solutions, pseudo bit lines are used.
Description
Technical field
The invention relates to the storage technical field of integrated circuits, particularly about a kind of device and method that on the non-volatile memory integrated circuit, carries out erase operation.
Background technology
The over-erasure effect of improving in the erase operation has become a crucial problem.Because more and more higher storage array density, floating grid coupling effect just become more and more important.
Yet the scheme of handling the nonvolatile memory cell erase operation at present is also effective inadequately.The over-erasure that for example, can cause storage unit to the erase operation shown in Fig. 5 at Fig. 1.In another example, as U.S. Patent Application Publication No. the 20080175069th, wipe one because the mistake of erase verification takes place and optionally to be divided into two groups in the section, again it further is divided into more group afterwards, so can cause relative complex ground erase operation.And in another example,, use false word line and false storage unit can waste many available storage unit in large quantities as U.S. Patent number the 7417895th.
Summary of the invention
Embodiments of the invention are to solve and the relevant over-erasure problem of edge word lines floating grid coupling effect.The scheme that discuss in this place even can use not needing to increase under the situation of array sizes, the storage unit persistence of improvement and erasing time performance can be when solving erase operation over-erasure and produce.
Erase verification when the different schemes that discuss in this place comprises an erase operation and wipe the edge word lines of wiping group of child-operation and the improvement grouping of central word line.In another kind of scheme, the voltage class that changes edge word lines to be solving the over-erasure problem that this wipes group, and also can improve its erasing time performance.Other solution is used false bit line.
A purpose of the present invention comprises for a kind of device is provided: a storage integrated circuit, it comprises a plurality of storage unit, many these a plurality of storage unit of word line access, and control circuit.
These word lines are divided into a plurality of groups of wiping, and so response is chosen an erase command of wiping group from this a plurality of wiping in the group, and control circuit carries out an erase operation to this storage unit of wiping the word line institute access of group.These are wiped group and are commonly referred to section or block.These those word lines of wiping group (for example: edge word lines comprise outside word line, first and last word line), this wipes the outside storage unit of group access, and inboard word line (for example: between first and last word line between central word line), this wipes the inboard storage unit of group access.Those inboard storage unit are surrounded by those outside storage unit, separate with these a plurality of storage unit of wiping the word line institute access that not choosing in the group wipe group.
This control circuit has to be chosen this this erase command of wiping group by this control circuit and carries out this erase operation for response, this erase operation be included in the one second erase verification child-operation carried out on word lines in these those outsides of wiping group before, wipe the one first erase verification child-operation of carrying out on those inboard word lines of group at this.
In certain embodiments, this first erase verification child-operation is that mode with a group puts on those inboard word lines.
In certain embodiments, this second erase verification child-operation is that mode with a group puts on those outside word lines.
In certain embodiments, the performed erase verification in those outside word lines of this control circuit is to carry out in the mode of multiple group, comprise that one first outside group wipes one first side of group in this, and one second side of group is wiped in this by one second outside group.
In certain embodiments, this erase operation comprises and wipes child-operation.For a failure result of this second erase verification child-operation of responding this control circuit, wipe child-operation and wipe those word lines of group and carry out this in this, and apply one non-wipe to adjust be biased into those inboard word lines.
In another embodiment, the performed erase verification in those outside word lines of this control circuit is to carry out in the mode of multiple group, comprise that one first outside group wipes one first side of group in this, and one second side of group is wiped in this by one second outside group.Be included in by this performed erase operation of this control circuit this second outside group that carries out those outside word lines one the 3rd erase verification child-operation before, carry out one second erase verification child-operation this first outside group in those outside word lines.Failure result for this second erase verification child-operation of responding this control circuit, and carry out this and wipe child-operation, and apply non-wiping and adjust this second outside group that is biased into those outside word lines in this this second outside group of wiping those outside word lines of group.
And in another embodiment, the performed erase verification in those outside word lines of this control circuit is to carry out in the mode of multiple group, comprise that one first outside group wipes one first side of group in this, and one second side of group is wiped in this by one second outside group.Be included in by this performed erase operation of this control circuit those outside word lines of carrying out this second outside group one the 3rd erase verification child-operation before, carry out one second erase verification child-operation this first outside group in those outside word lines.Failure result for this second erase verification child-operation of responding this control circuit, and carry out this and wipe child-operation, and apply non-wiping and adjust this second outside group and those the inboard word lines that is biased into those outside word lines in this this second outside group of wiping those outside word lines of group.
And In yet another embodiment, the performed erase verification in those outside word lines of this control circuit is to carry out in the mode of multiple group, comprise that one first outside group wipes one first side of group in this, and one second side of group is wiped in this by one second outside group.Be included in by this performed erase operation of this control circuit this second outside group that carries out those outside word lines one the 3rd erase verification child-operation before, carry out one second erase verification child-operation this first outside group in those outside word lines.Failure result for the 3rd erase verification child-operation that responds this control circuit, and carry out this and wipe child-operation, and apply non-wiping and adjust the 3rd outside group that is biased into those outside word lines in this this second outside group of wiping those outside word lines of group.
And in another embodiment, the performed erase verification in those outside word lines of this control circuit is to carry out in the mode of multiple group, comprise that one first outside group wipes one first side of group in this, and one second side of group is wiped in this by one second outside group.Be included in by this performed erase operation of this control circuit this second outside group that carries out those outside word lines one the 3rd erase verification child-operation before, carry out one second erase verification child-operation this first outside group in those outside word lines.For the 3rd erase verification child-operation that responds this control circuit-failure result, and carry out this and wipe child-operation, and apply non-wiping and adjust the 3rd outside group and those the inboard word lines that is biased into those outside word lines in this this second outside group of wiping those outside word lines of group.
Another object of the present invention is for providing the method that comprises following steps:
Have the storage integrated circuit that are divided into a plurality of many word lines wiping group in one and carry out and choose an erase command of wiping group, comprising:
In this wipe the one second erase verification child-operation carried out on the outside word line of group before, wipe the one first erase verification child-operation of carrying out on the inboard word line of group at this, and those inboard word lines wherein, this wipes the inboard storage unit of group access, those inboard storage unit are surrounded by those outside storage unit, separate with these a plurality of storage unit of wiping the word line institute access that not choosing in the group wipe group.
Many other different embodiment are discussed below.
Another purpose of the present invention comprises for a kind of device is provided: a storage integrated circuit, it comprises a plurality of storage unit, many these a plurality of storage unit of word line access, and control circuit.
These many word lines are divided into a plurality of groups of wiping, and so choose an erase command of wiping group with response in the group from this a plurality of wiping, and control circuit carries out an erase operation to this storage unit of wiping the word line institute access of group.
These those word lines of wiping group comprise outside word line, and this wipes the outside storage unit of group access.Those outside storage unit are used for storage data (not being to have only dummy unit) when this storage integrated circuit normal running.Those inboard storage unit are surrounded by those outside storage unit, separate with these a plurality of storage unit of wiping the word line institute access that not choosing in the group wipe group.
This control circuit has by this control circuit to be chosen this this erase command of wiping group and carries out this erase operation in order to respond, this erase operation comprises that putting on one first on these those inboard word lines of wiping group wipes to adjust bias voltage and put on one second on these those outside word lines of wiping group and wipe the adjustment bias voltage, and this first is wiped and adjust bias voltage second to wipe the adjustment bias voltage different with this.
In certain embodiments, this that this control circuit applied first wiped and adjusted bias voltage and comprise that one first word line voltage is at least one of those inboard word lines, this that this control circuit applied second wiped and adjusted bias voltage and comprise one second word line voltage at least one of those outside word lines, and this first wipes that to adjust bias voltage be second to wipe the negative voltage of adjusting the littler absolute value of bias voltage than this.
In certain embodiments, these many word lines more comprise many false word lines, and those outside word lines comprise one first outside word line and a false word line adjacency.
In certain embodiments, these many word lines more comprise many false word lines, and those outside word lines comprise one first outside word line and a false word line adjacency, reach one second outside word line and be not selected wipe group be not selected the word line adjacency.This that this control circuit applied second wiped the adjustment bias voltage and comprised one first word line voltage to this first outside word line, reach one second word line voltage to this second outside word line, and this first word line voltage is the negative voltage than the littler absolute value of this second word line voltage.
In certain embodiments, this control circuit applies positive voltage and is not selected the word line that is not selected of wiping group in the group to this a plurality of wiping, and applies negative voltage and extremely wiped word line in the group by selected this of this erase command.
A further object of the present invention is for providing the method that comprises following steps:
Have the storage integrated circuit that are divided into a plurality of many word lines wiping group in one and carry out and choose an erase command of wiping group, comprising:
Putting on one first on these those inboard word lines of wiping group wipes to adjust bias voltage and put on one second on these those outside word lines of wiping group and wipes the adjustment bias voltage, this first is wiped and adjusts bias voltage second to wipe the adjustment bias voltage different with this, and wherein those outside word line accesses this wipe the outside storage unit of group, wherein those inboard word line accesses this wipe the inboard storage unit of group, so those inboard storage unit are surrounded by those outside storage unit, separate with these a plurality of storage unit of wiping the word line institute access that not choosing in the group wipe group, and those outside storage unit are used for storage data (not being to have only dummy unit) when this storage integrated circuit normal running.
Many other different embodiment are discussed below.
Description of drawings
The present invention is defined by the claim scope.These and other objects, feature, and embodiment, graphic being described of can in the chapters and sections of following embodiment, arranging in pairs or groups, wherein:
Fig. 1 shows that one has the multiple block schematic diagram of wiping the storage array part of group, shows the floating grid coupling effect of wiping between the group between adjacent therein.
Fig. 2 and Fig. 3 show the floating grid coupling effect, it compares by being applied to the different adjustment bias voltage of adjacent word line, Fig. 2 shows that adjacent word line receives identical negative voltage, and Fig. 3 shows that adjacent word line receives different voltage, comprises that a negative voltage is applied to be selected the word line of wiping group and a positive voltage and to be applied to and not to be selected the word line of wiping group.
Fig. 4 shows the equation of considering the floating grid voltage after the floating grid coupling effect, and utilizes this equation to come the floating grid coupling effect that different adjustment bias voltages is produced among displayed map 2 and Fig. 3.
Fig. 5 shows that one has the multiple step of wiping with an erase operation of erase-verifying child-operation, with be shown in this erase-verifying child-operation dependence of wiping an edge word line of group, to carry out the child-operation of wiping of these all word lines of wiping group, the result is this over-erasure of wiping the central word line of group.
Fig. 6 shows that one has the multiple block schematic diagram of wiping the storage array part of group, it is wiped group with one and cuts apart a plurality of groups, comprise edge word lines group, the central word line group between the edge word lines group, so the edge word lines group can separate central word line group and other word line of wiping group and hold.
Fig. 7 shows that one has the multiple step of wiping with an erase operation of erase-verifying child-operation, with the erase-verifying child-operation dependence that is shown in this central word line groups of wiping group, to carry out the child-operation of wiping of these all word lines of wiping group, afterwards again in this wipe the erase-verifying child-operation dependence of the edge word lines group of group, to carry out the child-operation of wiping of this edge word lines group of wiping group, the result is that this central word line of wiping group does not have over-erasure.
Fig. 8 shows the process flow diagram that carries out an erase operation, and it is divided into many child-operations, and so the multiple group of edge word lines is processed separately.
Fig. 9 shows the process flow diagram that carries out an erase operation, and it is divided into many child-operations, and so the multiple group of edge word lines is handled together.
Figure 10 shows that one has the multiple block schematic diagram of wiping the storage array part of group, show the floating grid coupling effect of wiping between the group therein between adjacent, and to cut apart the word line of wiping group be many groups, comprise edge word lines group, and these word lines of one group of central authorities' word line, be between edge word lines group, so the edge word lines group can separate central word line group and other word line of wiping group and hold, it can be biased into central word line groups and edge word lines group by applying different adjustment, to solve the floating grid coupling effect.
Figure 11 and Figure 12 show the floating grid coupling effect, it compares by being applied to the different adjustment bias voltage of adjacent word line, Figure 11 shows that the identical negative voltage of adjacent word line reception is applied to one and is selected the central word line of wiping in the group, and Figure 12 shows that adjacent word line receives different voltage, comprising that a positive voltage is applied to is not selected the word line of wiping group and a negative voltage and is applied to and is selected the edge word lines of wiping group, so is selected the edge word lines of wiping group and is selected the negative voltage that the central word line of wiping group receives bigger absolute value than this.
Figure 13 shows the equation of considering the floating grid voltage after the floating grid coupling effect, and utilizes this equation to show to apply among Figure 11 and Figure 12 different adjustment to be biased in central word line groups and edge word lines group with solution floating grid coupling effect.
Figure 14 shows that one has the multiple block schematic diagram of wiping the storage array part of group, comprises false word line therein and wipes between the group to solve the floating grid coupling effect in difference.
Figure 15 shows that one has the multiple step of wiping with an erase operation of erase-verifying child-operation, comprises false word line with demonstration and wipes between the group in difference, and the result is that this central word line of wiping group does not have over-erasure.
Figure 16 is the block schematic diagram that can use the integrated circuit of the storage array that the present invention has described arbitrary Improvement type erase operation.
[main element symbol description]
102: sequential circuit
104: class's commutation circuit
106: latch circuit
108: feedback signal
110: clock signal
112: reference value is switched in class
114: the sequential circuit reference value
116: produce circuit with signal temperature compensation class switching reference value and sequential circuit reference value
118: the circuit that couples with noise optionally
202A, 202B, 302A, 302B, 802A, 802B, 1102A, 1102B, 1602A, 1602B: sequential circuit
204A, 204B: negative circuit
206,306,806,1106,1606: latch circuit
304A, 304B, 804A, 804B, 1104A, 1104B, 1604A, 1604B: class's commutation circuit
422,522: power regulator
816A, 816B: reference circuit is switched in class
1116A, 1116B, 1616A, 1616B: the reference value generator is switched in frequency power supply and class
1236: power supply
1246,1301: the frequency power supply
1248,1302: reference value is switched in class
1303: power supply and reference value
1620A, 1620B, 1620A, 1620B: change-over switch
1650 integrated circuit
1600 non-volatile memory array
1601 column decoders and word line driver
1602 word lines
1603 line decoders
1604 bit lines
1605,1607 buses
1606 induction amplifiers and data input structure
1611 Data In-Lines
1615 DOL Data Output Line
1608 bias voltage adjustment supply voltage
1609 programme, wipe and read bias voltage adjusts state machine
Embodiment
Fig. 1 shows that one has the multiple block schematic diagram of wiping the storage array part of group, shows the floating grid coupling effect of wiping between the group between adjacent therein.The one common example of wiping group comprises wipes section and erase blocks, its comprise can access by the word line of eraseable memory unit together, the erase command that response one specifies a specific erase blocks or section promptly will wipe.
Particularly, Fig. 1 shows that consecutive storage unit can have coupling effect during by the word line WLs access of different voltage class at consecutive storage unit.Therefore, a word line of wiping the group edge has the floating grid coupling effect when an erase operation.This effect can adjacently be wiped the edge word lines of group and influenced the threshold voltage consistance behind the erase operation by false word line or.
Fig. 2 and Fig. 3 show the floating grid coupling effect, it compares by being applied to the different adjustment bias voltage of adjacent word line, Fig. 2 shows that adjacent word line receives identical negative voltage, and Fig. 3 shows that adjacent word line receives different voltage, comprises that a negative voltage is applied to be selected the word line of wiping group and a positive voltage and to be applied to and not to be selected the word line of wiping group.In Fig. 2 and Fig. 3, VFG is the floating grid voltage of a storage unit, and CFF then is the stray capacitance of this storage unit.
Fig. 4 shows the equation of considering the floating grid voltage after the floating grid coupling effect, and utilizes this equation to come the floating grid coupling effect that different adjustment bias voltages is produced among displayed map 2 and Fig. 3.
The value of this variable α is represented the coupling between a floating grid and an adjacent node.More particularly, α 1 is that coupling value, the α 2 of CFW (word line) are that coupling value, the α 3 of CFF (adjacent floating grid) is the coupling value of CFB (body) and α 4 is coupling values of CFD (drain electrode).Q is the electric charge that is stored in indivedual floating grids, and CT then is the capacitance in the floating grid.When the voltage of the voltage of WL1 and WL31 was identical, the voltage of WL32 also can be identical with the voltage of WL2, and then when voltage VFG1 was identical with voltage VFG31, (coupling capacitance QT=CFG*VFG) can not change CFG.But the voltage of the voltage ratio WL2 of WL32 is also big, so voltage VFG1 can be also littler than voltage VFG31.
Fig. 5 shows that one has the multiple step of wiping with an erase operation of erase-verifying child-operation, to be shown in the erase-verifying child-operation dependence that this wipes an edge word line of group, this is wiped the child-operation of wiping that all word lines of group carry out, the result is this over-erasure of wiping the central word line of group.
510, these word lines that this shown in the figure is wiped the central word line of group are to wipe between the edge word lines of group between this.520, show the threshold voltage distribution of central word line and edge word lines.530, all word lines are carried out erase operation n time.In the threshold voltage distribution of 540 shown central word lines and edge word lines, this central word line of wiping group is by erase verification, but edge word lines is because the relation of floating grid coupling effect but can't be passed through erase verification.550, all word lines are carried out erase operation m time.In the threshold voltage distribution of 560 shown central word lines and edge word lines, though edge word lines has been passed through erase verification, central word line regions is over-erasure but.Therefore, the floating grid coupling effect has caused the over-erasure of threshold voltage distribution to central word line regions.
Fig. 6 shows that one has the multiple block schematic diagram of wiping the storage array part of group, it is wiped group with one and cuts apart a plurality of groups, comprise edge word lines group, the central word line groups between edge word lines group, so edge word lines group can separate central word line groups and other word line of wiping group and hold.
When Fig. 6 is presented at an erase operation edge word lines group is divided into A of group and the C of group, central word line groups then is the B of group.These groups can verify when erase operation respectively.
Fig. 7 shows that one has the multiple step of wiping with an erase operation of erase-verifying child-operation, to be shown in the erase-verifying child-operation dependence of this central word line groups of wiping group, this is wiped the child-operation of wiping that all word lines of group carry out, wipe the erase-verifying child-operation dependence of the edge word lines group of group, wipe child-operation with what the edge word lines group of this being wiped group carried out in this more afterwards, the result is that this central word line of wiping group does not have over-erasure.
710, these word lines that this shown in the figure is wiped the central word line of group are to wipe between the edge word lines of group between this.720, show the threshold voltage distribution of central word line and edge word lines.730, all word lines are carried out erase operation n time, but only central word line is carried out erase verification.In the threshold voltage distribution of 740 shown central word lines and edge word lines, this central word line of wiping group is by erase verification, but edge word lines is not carried out erase verification as yet.750, edge word lines is carried out erase operation m time.In the threshold voltage distribution of 760 shown central word lines and edge word lines, this edge word lines of wiping group is by erase verification, and central word line regions is not by over-erasure.Therefore, the floating grid coupling effect has not caused the over-erasure of threshold voltage distribution to central word line regions.
Use another kind of describing mode, the erase verification that central word line groups B is carried out, and when failure, all word line groups are wiped.When central word line groups by erase verification, edge word line groups A and C are carried out erase verification and wipe after then.
Fig. 8 shows the process flow diagram that carries out an erase operation, and it is divided into many child-operations, and so the multiple group of edge word lines is processed separately.
In this process flow diagram, A of edge word lines group and C carry out erase verification respectively and wipe.After pre-programmed, the erase verification that first B of group carries out.If the erase verification failure is then wiped all word line groups.When the B of group passes through erase verification, then afterwards edge word line groups A is carried out erase verification.If the erase verification failure is then only wiped the A of group; Afterwards the B of group and C are denoted as to wipe and suppress group, so when wiping child-operation, apply the 2V that suppresses word line class and wipe inhibition zone (even be selected wipe in the group) to these.When the A of group passes through erase verification, then the C of group is carried out erase verification.If the erase verification failure is then only wiped the C of group; Afterwards the A of group and B are denoted as to wipe and suppress group, so when wiping child-operation, apply the 2V that suppresses word line class and wipe inhibition zone (even be selected wipe in the group) to these.At last, soft programming finishes this erase operation.
Fig. 9 shows the process flow diagram that carries out an erase operation, and it is divided into many child-operations, and so the multiple group of edge word lines is handled together.
In this process flow diagram, edge word lines group merges to handle.Though similar with the process flow diagram among Fig. 8, A of edge word lines group and C carry out erase verification together.When the B of group by after the erase verification, then only have the B of group is denoted as to wipe and suppress group.
Figure 10 shows that one has the multiple block schematic diagram of wiping the storage array part of group, show the floating grid coupling effect of wiping between the group therein between adjacent, and to cut apart the word line of wiping group be many groups, comprise edge word lines group, and these word lines of one group of central authorities' word line, be between edge word lines group, so the edge word lines group can separate central word line group and other word line of wiping group and hold, it can be biased into central word line groups and edge word lines group by applying different adjustment, to solve the floating grid coupling effect.
Because one wipes the relation of floating grid coupling effect of the edge word lines of group, its | VFG| pressure drop meeting reduces.Therefore, the negative voltage of edge word lines size can increase the change with VFG between the compensation adjacent word line.
Figure 11 and Figure 12 show the floating grid coupling effect, it compares by being applied to the different adjustment bias voltage of adjacent word line, Figure 11 shows that the identical negative voltage of adjacent word line reception is applied to one and is selected the central word line of wiping in the group, and Figure 12 shows that adjacent word line receives different voltage, comprising that a positive voltage is applied to is not selected the word line of wiping group and a negative voltage and is applied to and is selected the edge word lines of wiping group, so is selected the edge word lines of wiping group and is selected the negative voltage that the central word line of wiping group receives bigger absolute value than this.
Figure 13 shows the equation of considering the floating grid voltage after the floating grid coupling effect, and utilizes this equation to show to apply among Figure 11 and Figure 12 different adjustment to be biased in central word line groups and edge word lines group with solution floating grid coupling effect.
Voltage VFG31 and edge word lines WL32 couple.In changing WL31 voltage class to compensate this VFG coupling effect, this (α 1*VWL1+ α 1 α 2*VWL2) value can equate with (α 1*VWL31+ α 1 α 2*VWL32) value.So VFG1 can equate with VFG31.Therefore the voltage class of edge word lines changes the floating grid coupling effect that can eliminate in the erase operation.
Figure 14 shows that one has the multiple block schematic diagram of wiping the storage array part of group, comprises false word line therein and wipes between the group to solve the floating grid coupling effect in difference.
False word line is eliminated the floating grid coupling effect.In erase operation, the voltage class of false word line is identical with the voltage class of an edge word line, so edge word lines can't be subjected to the influence of coupling effect.
Figure 15 shows that one has the multiple step of wiping with an erase operation of erase-verifying child-operation, comprises false word line with demonstration and wipes between the group in difference, and the result is that this central word line of wiping group does not have over-erasure.
1510, these word lines that this shown in the figure is wiped the central word line of group are to wipe between the edge word lines of group between this.1520, show the threshold voltage distribution of central word line and edge word lines.1530, all word lines are carried out erase operation n time.In the threshold voltage distribution of 1540 shown central word lines and edge word lines, these all word lines of wiping group all do not pass through erase verification, and have identical threshold voltage class because there not being the floating grid coupling effect.1550, all word lines are carried out erase operation m time.In the threshold voltage distribution of 1560 shown central word lines and edge word lines, though this edge word lines of wiping group is passed through erase verification, central word line regions is not also by over-erasure.Therefore, this threshold voltage distribution over-erasure not.
Because the voltage class of edge word lines changes and be false from first line, threshold voltage distribution is over-erasure not.Because the floating grid coupling effect of edge word lines has been eliminated, all word lines can be verified and wipe, and have removed the over-erasure effect.
Figure 16 can use the block schematic diagram that the present invention has described arbitrary Improvement type integrated circuit.
Figure 16 is the concise and to the point block schematic diagram that comprises the integrated circuit 1660 of a memory array 1600.One word line (or row) and block are chosen code translator 1601 and are coupled to, and with it electrical communication are arranged, and many word lines 1602 and character string selection wire are to arrange along the column direction of memory array 1600 therebetween.One bit line (OK) code translator and driver 1603 are coupled to many bit lines of arranging along the row of memory array 1,600 1604, and with it electrical communication are arranged, and with from reading of data, or write data extremely, in the storage unit of memory cell array 1600.The address is to see through bus 1605 to provide to word-line decoder and driver 1601 and bit line decoder 1603.Induction amplifier in the square 1606 and data input structure, comprise as read, the current source of programming and erasing mode, be to see through bus 1607 to be coupled to bit line decoder 1003.Data are to see through the data input structure that Data In-Line 1611 is sent to square 1606 by the input/output end port on the integrated circuit 1650.Data are by the induction amplifier in the square 1606, see through DOL Data Output Line 1615, are sent to I/O end or other integrated circuit 1650 interior or outer data destinations on the integrated circuit 1650.State machine and improvement clock circuit are with control bias voltage adjustment supply voltage 1608 in circuit 1609.
Though the present invention is described with reference to embodiment, right the present invention's creation is not subject to its detailed description.Substitute mode and revise pattern and in previous description, advise, and other substitute mode and modification pattern will by those skilled in the art thought and.Particularly, all have be same as in fact member of the present invention in conjunction with and reach the identical result person in fact with the present invention, neither disengaging spiritual category of the present invention.Therefore, all these substitute modes and to revise pattern be to be intended to drop on the present invention among claim scope and category that equipollent defined thereof.
Claims (20)
1. a device that carries out erase operation on the non-volatile memory integrated circuit is characterized in that, comprises:
A plurality of storage unit;
Many these a plurality of storage unit of word line access, these many word lines are divided into a plurality of groups of wiping, and so response is chosen an erase command of wiping group from this a plurality of wiping in the group, and these those word lines of wiping group comprise:
Outside word line, this wipes the outside storage unit of group access; And
Inboard word line, this wipes the inboard storage unit of group access, and those inboard storage unit are surrounded by those outside storage unit, separate with these a plurality of storage unit of wiping the word line institute access that not choosing in the group wipe group;
Control circuit carries out an erase operation to this storage unit of wiping the word line institute access of group, wherein this erase operation be included in carry out on these those outside word lines of wiping group one second erase verification child-operation before, on this wipes those inboard word lines of group, carry out one first erase verification child-operation.
2. the device that on the non-volatile memory integrated circuit, carries out erase operation according to claim 1, it is characterized in that, this erase operation comprises wipes child-operation, wherein respond a failure result of this second erase verification child-operation of this control circuit, and carry out this and wipe child-operation in these those outside word lines of wiping group, and apply one non-wipe to adjust be biased into those inboard word lines.
3. the device that carries out erase operation on the non-volatile memory integrated circuit according to claim 1 is characterized in that, this erase operation comprises wipes child-operation,
Wherein the erase verification that is executed in those outside word lines by this control circuit is to carry out in the mode of multiple group, comprises that one first outside group wipes one first side of group in this, and one second outside group wipes one second side of group in this,
Wherein by this performed erase operation of this control circuit be included in this second outside group that carries out those outside word lines one the 3rd erase verification child-operation before, carry out this second erase verification child-operation this first outside group in those outside word lines, and
Wherein, respond a failure result of this second erase verification child-operation of this control circuit, and carry out this and wipe child-operation, and apply non-wiping and adjust this second outside group and those the inboard word lines that is biased into those outside word lines in this this first outside group of wiping those outside word lines of group.
4. the device that on the non-volatile memory integrated circuit, carries out erase operation according to claim 1, it is characterized in that, this erase operation applies one first and wipes to adjust and be biased into these those inboard word lines of wiping group and one second and wipe to adjust and be biased into those outside word lines that this wipes group, this first is wiped and adjusts bias voltage and second wipe that to adjust bias voltage different with this, and word lines are used for storage data outside those when the normal running of this memory storage.
5. the device that on the non-volatile memory integrated circuit, carries out erase operation according to claim 4, it is characterized in that, this that this control circuit applied first wiped and adjusted bias voltage and comprise that-first word line voltage is at least one of those inboard word lines, this that this control circuit applied second wiped and adjusted bias voltage and comprise one second word line voltage at least one of those outside word lines, and this first wipes that to adjust bias voltage be second to wipe the negative voltage of adjusting the littler absolute value of bias voltage than this.
6. the device that carries out erase operation on the non-volatile memory integrated circuit according to claim 4 is characterized in that, these many word lines more comprise many false word lines, and wherein those outside word lines comprise one first outside word line and a false word line adjacency.
7. the device that carries out erase operation on the non-volatile memory integrated circuit according to claim 4 is characterized in that, these many word lines more comprise many false word lines, and
Wherein those outside word lines comprise one first outside word line and a false word line adjacency, and one second outside word line and be not selected wipe group be not selected the word line adjacency, reach
Wherein this that this control circuit applied second wiped and adjusted bias voltage and comprise one first word line voltage to this first outside word line, and one second word line voltage is to this second outside word line, and
Wherein this first word line voltage is the negative voltage than the littler absolute value of this second word line voltage.
8. a method of carrying out erase operation on the non-volatile memory integrated circuit is characterized in that, comprises the following step:
Have the storage integrated circuit that are divided into a plurality of many word lines wiping group in one and carry out and choose an erase command of wiping group, comprising:
In this wipe carry out on the outside word line of group one second erase verification child-operation before, wipe at this and to carry out one first erase verification child-operation on inboard word line of group, wherein those outside word line accesses this wipe the outside storage unit of group, and wherein those inboard word line accesses this wipe the inboard storage unit of group, so those inboard storage unit are surrounded by those outside storage unit, separate with these a plurality of storage unit of wiping the word line institute access that not choosing in the group wipe group.
9. method according to claim 8 is characterized in that, the mode that this first erase verification child-operation is enough to a group puts on those inboard word lines.
10. method according to claim 8 is characterized in that, this second erase verification child-operation is that the mode with a group puts on those outside word lines.
11. method according to claim 8, it is characterized in that, the erase verification of carrying out those outside word lines is to carry out in the mode of multiple group, comprises that one first outside group wipes one first side of group in this, and one second side of group is wiped in this by one second outside group.
12. method according to claim 8 is characterized in that, this erase operation comprises wipes child-operation, and
Wherein, respond a failure result of this second erase verification child-operation, and carry out this and wipe child-operation in these those outside word lines of wiping group, and apply one non-wipe to adjust be biased into those inboard word lines.
13. method according to claim 8 is characterized in that, this erase operation comprises wipes child-operation,
The erase verification of wherein carrying out those outside word lines is to carry out in the mode of multiple group, comprises that one first outside group wipes one first side of group in this, and one second outside group wipes one second side of group in this,
Wherein by this performed erase operation of this control circuit be included in this second outside group that carries out those outside word lines one the 3rd erase verification child-operation before, carry out this second erase verification child-operation this first outside group in those outside word lines, and
Wherein, respond a failure result of this second erase verification child-operation, and carry out this and wipe child-operation, and apply non-wiping and adjust this second outside group that is biased into those outside word lines in this this first outside group of wiping those outside word lines of group.
14. method according to claim 8 is characterized in that, this erase operation comprises wipes child-operation,
The erase verification of wherein carrying out those outside word lines is to carry out in the mode of multiple group, comprises that one first outside group wipes one first side of group in this, and one second outside group wipes one second side of group in this,
Wherein this erase operation be included in this second outside group that carries out those outside word lines one the 3rd erase verification child-operation before, carry out this second erase verification child-operation this first outside group in those outside word lines, and
Wherein, respond a failure result of this second erase verification child-operation, and carry out this and wipe child-operation, and apply non-wiping and adjust this second outside group and those the inboard word lines that is biased into those outside word lines in this this first outside group of wiping those outside word lines of group.
15. method according to claim 8 is characterized in that, this erase operation comprises wipes child-operation,
The erase verification of wherein carrying out those outside word lines is to carry out in the mode of multiple group, comprises that one first outside group wipes one first side of group in this, and one second outside group wipes one second side of group in this,
Wherein by this performed erase operation of this control circuit be included in this second outside group that carries out those outside word lines one the 3rd erase verification child-operation before, carry out this second erase verification child-operation this first outside group in those outside word lines, and
Wherein, respond a failure result of the 3rd erase verification child-operation, and carry out this and wipe child-operation, and apply non-wiping and adjust one the 3rd outside group that is biased into those outside word lines in this this second outside group of wiping those outside word lines of group.
16. method according to claim 8 is characterized in that, this erase operation comprises wipes child-operation,
The erase verification of wherein carrying out those outside word lines is to carry out in the mode of multiple group, comprises that one first outside group wipes one first side of group in this, and one second outside group wipes one second side of group in this,
Wherein by this performed erase operation of this control circuit be included in this second outside group that carries out those outside word lines one the 3rd erase verification child-operation before, carry out this second erase verification child-operation this first outside group in those outside word lines, and
Wherein, respond a failure result of the 3rd erase verification child-operation of this control circuit, and carry out this and wipe child-operation, and apply non-wiping and adjust one the 3rd outside group and those the inboard word lines that is biased into those outside word lines in this this second outside group of wiping those outside word lines of group.
17. a method of carrying out erase operation on the non-volatile memory integrated circuit is characterized in that, comprises the following step:
Have the storage integrated circuit that are divided into a plurality of many word lines wiping group in one and carry out and choose an erase command of wiping group, comprising:
Putting on one first on these those inboard word lines of wiping group wipes to adjust bias voltage and put on one second on these those outside word lines of wiping group and wipes the adjustment bias voltage, this first is wiped and adjusts bias voltage second to wipe the adjustment bias voltage different with this, wherein those outside word line accesses this wipe the outside storage unit of group, and wherein those inboard word line accesses this wipe the inboard storage unit of group, so those inboard storage unit are surrounded by those outside storage unit, separate with these a plurality of storage unit of wiping the word line institute access that not choosing in the group wipe group, and those outside storage unit are used for storage data when this storage integrated circuit normal running.
18. method according to claim 17, it is characterized in that, applying this first wipes and adjusts bias voltage and comprise that one first word line voltage is at least one of those inboard word lines, this that this control circuit applied second wiped and adjusted bias voltage and comprise one second word line voltage at least one of those outside word lines, and this first wipes that to adjust bias voltage be second to wipe the negative voltage of adjusting the littler absolute value of bias voltage than this.
19. method according to claim 17 is characterized in that, these many word lines more comprise many false word lines, and wherein those outside word lines comprise one first outside word line and a false word line adjacency.
20. method according to claim 17 is characterized in that, these many word lines more comprise many false word lines, and
Wherein those outside word lines comprise one first outside word line and a false word line adjacency, and one second outside word line and be not selected wipe group be not selected the word line adjacency, reach
Wherein apply this and second wipe and adjust bias voltage and comprise one first word line voltage, and one second word line voltage is to this second outside word line to this first outside word line, and
Wherein this first word line voltage is the negative voltage than the littler absolute value of this second word line voltage.
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| CN 200910265614 CN102110474B (en) | 2009-12-28 | 2009-12-28 | Device and method for performing erasing operation on storage integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103198853A (en) * | 2012-01-10 | 2013-07-10 | 宜扬科技股份有限公司 | Semiconductor device and method for accelerating erase verification procedure by the same |
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| TWI642060B (en) * | 2017-11-07 | 2018-11-21 | 旺宏電子股份有限公司 | Erase-verify method for three-dimensional memories and memory system |
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| CN108206039A (en) * | 2016-12-19 | 2018-06-26 | 旺宏电子股份有限公司 | The relative control method of memory device |
| CN108206039B (en) * | 2016-12-19 | 2020-09-11 | 旺宏电子股份有限公司 | Memory device and related control method thereof |
| CN111951861A (en) * | 2019-05-14 | 2020-11-17 | 北京兆易创新科技股份有限公司 | Method and device for controlling erasing performance |
| CN112116935A (en) * | 2019-06-21 | 2020-12-22 | 晶豪科技股份有限公司 | Semiconductor memory device and word line enabling method |
| CN112116935B (en) * | 2019-06-21 | 2023-08-25 | 晶豪科技股份有限公司 | Semiconductor memory device and word line enabling method |
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