TWI642060B - Erase-verify method for three-dimensional memories and memory system - Google Patents

Abstract

An erase verification method for a three-dimensional memory and a memory system. The three-dimensional memory includes at least one memory string, and the at least one memory string includes a plurality of memory cells. The memory cell includes a first group of memory cells and a second group of memory cells. Each memory cell is coupled to a word line. The erase verification method includes the following steps. A first erase verify operation is performed on the first set of memory cells. After the first erase verify operation is performed on the first set of memory cells, a second erase verify operation is performed on the second set of memory cells in the case where the first set of memory cells is verified to be successfully erased.

Description

Erasing verification method for three-dimensional memory and memory system

The present invention relates to a three-dimensional memory, and more particularly to an erase verification method for a three-dimensional memory and a memory system.

In recent years, memory has become ubiquitous and widely used in various electronic devices such as personal computers, notebook computers, smart phones, tablets, digital cameras, and the like. To increase memory density, the memory design uses a three-dimensional architecture. Three-dimensional memory has more memory cells than two-dimensional memory. As the number of memory cells increases, so does the number of signal lines (such as bit lines and/or word lines).

Taking the substrate of the three-dimensional memory as the bottom layer, the radius of the upper structure of the three-dimensional memory may be larger than the radius of the lower structure of the three-dimensional memory, so in the erase verification operation, the erase verification voltage applied to the upper structure of the three-dimensional memory The electric field effect is different from the electric field effect of the erase verification voltage applied to the underlying structure of the three-dimensional memory. Furthermore, the residual charge will result in an erase verification error for the erase verification operation.

Therefore, there is a need for an erase verification method for a three-dimensional memory and a memory system.

The present invention relates to an erase verification method for a three-dimensional memory and a memory system. Through the present invention, multiple erase verify operations are performed on different sets of memory cells of a memory string, respectively. The probability of erasure verification errors due to residual charge will decrease.

According to a first aspect of the present invention, an erase verification method for a three-dimensional memory is proposed. The three-dimensional memory includes at least one memory string, and the at least one memory string includes a plurality of memory cells. The memory cell includes a first group of memory cells and a second group of memory cells. Each memory cell is coupled to a word line. The erase verification method includes the following steps. A first erase verify operation is performed on the first set of memory cells. After the first erase verify operation is performed on the first set of memory cells, a second erase verify operation is performed on the second set of memory cells in the case where the first set of memory cells are verified to be successfully erased.

According to a second aspect of the invention, a memory system is presented. The memory system includes a three-dimensional memory and a controller. The three-dimensional memory includes at least one memory string extending vertically through a plurality of layers of the three-dimensional memory. The at least one memory string comprises a plurality of memory cells, and the memory cells comprise a first group of memory cells and a second group of memory cells, or are divided into a plurality of groups of memory cells based on the number of memory cells on the memory cell string. Simplify operations with a packet erase verification method. Each memory cell is coupled to a word line. The controller is coupled to the three-dimensional memory for performing a first erase verification operation on the first group of memory cells, and after performing the first erase verification operation on the first group of memory cells, in the first group of memories When the cell is verified to be successfully erased, a second erase verify operation is performed on the second set of memory cells.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

102(1), 102(2), 102(3), 102(4), 102(5), 102(6)‧‧‧ memory cells

110‧‧‧Charge

112‧‧‧Residual charge

20‧‧‧ memory system

202‧‧‧ Controller

204‧‧‧Three-dimensional memory

S302~S318‧‧‧ Process steps

400, 500, 600, 700‧‧‧ memory cell series

402, 502, 602, 702‧‧‧ the first group of memory cells

404, 504, 604, 704‧‧‧ second group of memory cells

BL‧‧‧ bit line

CSL‧‧‧Common source line

GSL‧‧‧ Grounding selection line

DWLB‧‧‧ bottom virtual word line

DWLT‧‧‧ top virtual word line

SSL‧‧‧ tandem selection line

WL‧‧‧ character line

V _pass1 , V _pass2 , V _VFY ‧‧‧ voltage

FIG. 1A is a schematic diagram showing a memory cell sequence including a plurality of memory cells.

FIG. 1B is a schematic diagram showing that the programmed memory cell of the memory cell has a trapped charge.

FIG. 1C is a schematic diagram showing a memory cell series having residual charges.

2 is a block diagram of a memory system in accordance with an embodiment of the present invention.

FIG. 3 is a flow chart of a method for verifying erase of a three-dimensional memory according to an embodiment of the invention.

4A through 7D illustrate an erase verify operation including a first erase verify operation applied to a first set of memory cells and a second erase verify operation applied to a second set of memory cells in accordance with an embodiment of the present invention.

The various embodiments are described in detail below, however, the examples are intended to be illustrative only and not to limit the scope of the invention. Further, the drawings in the embodiments omits some of the elements to clearly show the technical features of the present invention. The same reference numerals will be used in the drawings to refer to the same or the like.

Please refer to Figures 1A, 1B and 1C. FIG. 1A is a schematic diagram showing a memory cell sequence including a plurality of memory cells. FIG. 1B is a schematic diagram showing that the programmed memory cell of the memory cell has a trapped charge. FIG. 1C is a schematic diagram showing a memory cell series having residual charges. FIG. 1A illustrates a memory cell array including a memory cell 102, which includes, for example, a memory cell 102 (1), a memory cell 102 (2), a memory cell 102 (3), a memory cell 102 (4), and a memory cell. 102(5) And memory cell 102 (6). After programming memory cell 102(4), charge 110 is captured in memory cell 102(4). However, prolonged exposure and exposure to high temperatures may cause the charge 110 in the memory cell 102(4) to be lost over time, no longer in the memory cell 102(4), and the lost charge will remain in the memory cell 102(4) In the adjacent region, it is located between the memory cell 102(3) and the memory cell 102(4) and/or between the memory cell 102(4) and the memory cell 102(5), as shown in FIG. 1B. Therefore, when an erase operation is performed on the memory string, the charge 110 in the memory 102(4) will be removed, but located between the memory cell 102(3) and the memory cell 102(4) and/or The charge between the memory cell 102 (4) and the memory cell 102 (5) is left behind. The remaining charge generates residual charge 112, as shown in Figure 1C. When the erase verify operation is performed on the memory cell string, the presence of residual charge 112 results in an erase verify error.

In order to eliminate the erase verification error caused by the residual charge, a pass voltage is applied to the word line connected to the memory cell 102 (3) and the memory cell 102 (5) beside the memory cell 102 (4) to "mask" The residual charge 112, and whether or not the verification memory cell 102(4) is applied, erases a successful erase voltage to the memory cell 102(4). The pass voltage is greater than the erase verify voltage. Therefore, the probability of erasure verification errors caused by residual charges will decrease. The term "shadowing" refers to the temporary ignoring of the residual charge 112 around the memory cell 102(4) based on the electric field of the passing voltage applied to the memory cell 102(3) and the memory cell 102(5). .

2 is a block diagram of a memory system in accordance with an embodiment of the present invention. The memory system includes a controller 202 and a three-dimensional memory 204. The three-dimensional memory 204 includes a plurality of memory cells arranged in a matrix. The memory cell string extends vertically through the various layer structures of the three-dimensional memory 204, and each memory cell string includes a plurality of memory cells. A memory cell of a memory string includes a first group of memory cells and a second group of memory cells. Each memory cell is coupled to a word line. The first set of memory cells are adjacent to each other and the second set of memory cells are adjacent to each other. In other embodiments of the present invention, the memory cells of a memory cell may include more than two sets of memory cells according to the number of memory cells on the memory cell string. The word line includes staggered even digital lines and odd digital lines. For example, the three-dimensional memory 204 can be a non-volatile memory, and can retain its information when the power is interrupted, such as a NAND Flash Memory or a variable resistance memory. Resistive Random-Access Memory (ReRAM).

The controller 202 is coupled to the three-dimensional memory 204. For example, the controller 202 can be, for example, by using a wafer, a circuit block within the wafer, a firmware circuit, a circuit board containing a plurality of electronic components and wires, or a storage medium storing a complex array of code. The implementation can also be implemented by executing a corresponding software, firmware or program by an electronic device such as a computer system, an embedded system, a handheld device, or a server. The controller 202 is configured to control the operation mode of the non-volatile memory array 204 in response to a partial external command from an interface (not shown in FIG. 2) via a bus. For example, the interface is an input/out interface. The operation mode is one of the programming (write) mode, the read mode, and the erase mode.

The controller 202 performs an erase operation by providing a erase voltage to erase the memory cells of the three-dimensional memory 204 and performing a erase verify operation to provide a erase verify voltage to verify whether the erased memory cells are successfully erased. For example, after the controller 202 performs an erase operation on a memory string of the three-dimensional memory 204, the controller 202 determines whether the memory string is successfully erased, and applies an erase in an erase verification operation. Verify the voltage (eg 0~1V) to the memory string. Applying erase voltage to memory string In the case of a column, when a sense current can flow through the memory string, the memory cell string can be regarded as a successful erase.

FIG. 3 is a flow chart of a method for verifying erase of a three-dimensional memory according to an embodiment of the invention. The flowchart of the erase verification method for three-dimensional memory shown in FIG. 3 can be applied to the memory system 20 as shown in FIG. In order to clearly explain the operation of the above various elements and the erasing verification method for three-dimensional memory of the embodiment of the present invention, the following description will be made in detail with reference to the flowchart of FIG. However, those skilled in the art to which the present invention pertains can understand that the method of the embodiment of the present invention is not limited to the memory system 20 of FIG. 2, nor is it limited to the steps of the flowchart of FIG. order.

Referring to FIG. 2 and FIG. 3, in accordance with an embodiment of the present invention, an erase verification method for a three-dimensional memory begins in step S302. In step S302, the controller 202 receives an erase operation command from an interface to change the operation mode of the three-dimensional memory 204 to the erase mode. The erase operation includes providing a word line that erases the voltage to the memory cells of at least one memory string connected to the three-dimensional memory 204 to erase the memory cells of the memory cell string. That is, the controller 202 erases these memory cells by providing a memory cell that erases the voltage to the memory cell string.

Next, control 202 performs a erase verify operation that includes a first erase verify operation and a second erase verify operation. At step S304, the controller 202 performs a first erase verify operation on the first set of memory cells of the memory cell string. Subsequently, in step S306, the controller 202 determines whether the first group of memory cells pass the first erase verification operation.

When the first group of memory cells fails the first erase verification operation (NO in step S306), step S308 is performed. At step S308, the controller 202 increases the erase voltage, Then, in step S310, the controller determines whether the increased erase voltage is greater than a erase threshold voltage.

When the increased erase voltage is less than or equal to the erase threshold voltage (NO in step S310), step S302 is performed again. The controller 202 performs an erase operation on the memory cell string again by applying the increased erase voltage to the memory cells of the memory cell string. When the increased erase voltage is greater than the erase threshold voltage (YES in step S310), step S312 is performed. In step S312, the controller 202 sets the memory cell of the memory cell string to be unsuccessful in erasing.

When the first group of memory cells passes the first erase verify operation (YES in step S306), step S314 is performed. In step S314, after performing the first erase verify operation on the first group of memory cells, the controller 202 performs a second erase verify operation on a second set of memory cells of the memory cell string. The controller 202 performs a second erase verify operation after the first set of memory cells passes the first erase verify operation. That is, in the case where the first group of memory cells is verified to be successfully erased, the controller 202 performs a second erase verify operation. Next, in step S316, the controller 202 determines whether the second group of memory cells passes the second erase verification operation.

When the second group of memory cells has not passed the second erase verify operation (NO in step S316), step S308 is performed. When the second group of memory cells passes the second erase verify operation (YES in step S316), step S318 is performed. In step S318, the controller 202 sets the memory cell of the memory cell string to be erased successfully. That is, in the case where the first group of memory cells and the second group of memory cells are respectively subjected to the first erase verify operation and the second erase verify operation, that is, the first group of memory cells and the second group of memory cells are respectively a wipe out of the verification operation and In the second erasing verification operation, it is verified that the erasing is successful, and the controller 202 sets the memory cell of the memory cell string to be successfully erased.

Hereinafter, the first erase verifying operation and the second erase verifying operation described above will be further described in detail with reference to the drawings. Please refer to Figures 4A to 7D. 4A to 7D illustrate an erase verify operation including a first erase verify operation applied to a first group of memory cells and a second erase verify applied to a second set of memory cells in accordance with an embodiment of the present invention. operating.

The memory cell strings 400, 500, 600, 700 in FIGS. 4A to 7D have the same or similar structural configurations. For example, each memory string 400, 500, 600, 700 includes 8 memory cells and is coupled to a bit line BL and two string select lines (SSL). SSL0 and SSL1, two top dummy word lines (DWLT) DWLT0 and DWLT1, eight word lines (WL line) WL0~WL7, two bottom dummy word lines (bottom dummy word line) , DWLB) DWLB0 and DWLB1, a ground select line (GSL) GSL and a common source line (CSL) CSL. It should be understood that the number of memory cells included in the memory cell series 400, 500, 600, and 700 may be any positive integer, and is not limited to eight.

Please refer to Figures 4A and 4B. In the present embodiment, the memory cells of the memory cell array 400 include a first group of memory cells 402 and a second group of memory cells 404. FIG. 4A illustrates that the first erase verify operation is performed only on the first set of memory cells 402, and FIG. 4B illustrates that the second erase verify operation is performed only on the second set of memory cells 402. The first set of memory cells 402 includes memory cells connected to word lines WL4, WL5, WL6, and WL7 and connected to the top dummy character The virtual memory cell of line DWLT0. The second set of memory cells 404 includes memory cells coupled to word lines WL0, WL1, WL2, and WL3 and virtual memory cells coupled to bottom dummy word line DWLB1.

When the controller 202 performs a first erase verify operation on the first set of memory cells 402, as shown in FIG. 4A, the controller 202 provides a positive voltage (eg, 1V) to the bit line BL and a voltage (eg, 0V) to Common source line CSL. The controller 202 applies a erase verify voltage V _VFY (for example, 0~1V) to the bit line connected to the first group of memory cells 402, that is, applies the erase verify voltage V _VFY to the word lines WL4 WL WL7 and the top dummy character. Line DWLT0. The controller 202 applies a first pass voltage _Vpass1 to the string select lines SSL0 and SSL1 and the top dummy word line _DWLT1 . Furthermore, the controller 202 applies a second pass voltage _Vpass2 to the word line connected to the second set of memory cells 404. A second pass voltage _{Vpass2 is} also applied to the bottom dummy word line DWLB0 and the ground select line GSL. A first verify voltage V _VFY pass voltage V _pass1 and V _pass2 greater than the second pass voltage erase. After applying the erase verify voltage V _VFY to the word line connecting the first group of memory cells 402 and the second pass voltage V _pass2 to the word line connecting the second set of memory cells 404, when a sense current flows through the memory cell In tandem 400, the first set of memory cells can be considered to be erased successfully and verified by the first erase verify operation. When a sense current fails to flow through the memory string 400, the first set of memory cells is considered to be unsuccessful in erasing and fails the first erase verify operation. The first pass voltage _{Vpass1 is} greater than the second pass voltage _Vpass2 .

When the first set of memory cells 402 pass the first verify erase operation, a second erase verify operation is performed on the second set of memory cells 404. That is, in the case where the first group of memory cells 402 are deemed to be erased successfully and the first erase verify operation is performed, a second erase verify operation is performed on the second set of memory cells 404. When the controller 202 performs a second erase verify operation on the second set of memory cells 404, as shown in FIG. 4B, the controller 202 provides a positive voltage (eg, 1V) to the bit line BL and a voltage (eg, 0V) to the common Source line CSL. The controller 202 applies an erase verify voltage V _VFY (eg, 0~1V) to the word line connecting the second group of memory cells 404, that is, applying the erase verify voltage V _VFY to the word lines WL0 WL WL3 and the bottom dummy word line. DWLB1. Furthermore, the controller 202 applies a first pass voltage _Vpass1 to the word line connecting the first set of memory cells 402. A first pass voltage Vpass1 is applied to the string select lines SSL0 and SSL1 and the top dummy word line _DWLT1 . A second pass voltage _{Vpass2 is} applied to the bottom dummy word line DWLB0 and the ground select line GSL. The second pass voltage V _pass2 greater than the erase verify voltage V _VFY. After applying the erase verify voltage V _VFY to the word line connecting the second group of memory cells 404 and the first pass voltage _Vpass1 to the word line connected to the first set of memory cells 402, when the sense current flows through the memory cell Tandem 400, the second set of memory cells can be considered as a successful erase and a second erase verify operation. When the sense current fails to flow through the memory string 400, the second set of memory cells is considered to be unsuccessful in erasing and fails the second erase verify operation. When the first set of memory cells 402 pass the first erase verify operation and the second set of memory cells 404 pass the second erase verify operation, the controller 202 sets the memory cell string 400 to be successfully erased.

Please refer to Figures 5A, 5B and 5C. In the present embodiment, the memory cells of the memory cell array 500 include a first group of memory cells 502 and a second group of memory cells 504. FIG. 5A illustrates a first stage of performing a first erase verify operation on only a first partial memory cell of the first group of memory cells 502, and FIG. 5B illustrates a first stage of only the first set of memory cells 502. The second part of the memory cell performs the second phase of the first erase verification operation. FIG. 5C illustrates performing a second erase verify operation on the second set of memory cells 504. The first set of memory cells 502 includes memory cells coupled to word lines WL4, WL5, WL6, and WL7 and virtual memory cells coupled to top virtual word line DWLT0. The second set of memory cells 504 includes memory cells coupled to word lines WL0, WL1, WL2, and WL3 and virtual memory cells coupled to bottom dummy word line DWLB1. When the controller 202 performs a first erase verify operation on the first set of memory cells 502 and a second erase verify operation on the second set of memory cells 504, the controller 202 provides a positive voltage (eg, 1V) to the bit line BL. And a voltage (for example, 0V) to the common source line CSL. At the same time, the serial selection lines SSL0 and SSL1 and the top virtual word line DWLT1 are applied with a first pass voltage _Vpass1 . The bottom dummy word line DWLB0 and the ground selection line GSL are applied with a second pass voltage _Vpass2 . The first pass voltage _{Vpass1 is} greater than the second pass voltage _Vpass2 .

In the present embodiment, the first erase verify operation includes two phases, a first phase of the first erase verify operation and a second phase of the first erase verify operation. When the controller 202 performs a first erase verify operation on the first group of memory cells 502, first, as shown in FIG. 5A, in the first stage of the first erase verify operation, the controller 202 applies only the erase verify voltage V. _{VFY is} coupled to word lines WL4 and WL6 of the first group of memory cells 502 and top dummy word line DWLT0. That is, in the first stage of the first erase verify operation, the controller 202 applies only the erase verify voltage V _VFY to the word line of a first portion of the memory cells coupled to the first set of memory cells 502. Moreover, in the first stage of the first erase verify operation, the controller 202 also applies the first pass voltage _Vpass1 to the word lines WL5 and WL7 connected to the first set of memory cells 502. That is, in the first stage of the first erase verify operation, the controller 202 applies the first pass voltage _Vpass1 to the word line of a second portion of the memory cells connected to the first set of memory cells 502. A first pass voltage V _pass1 greater than the erase verify voltage V _VFY.

Secondly, after the first stage of the first erase verify operation, as shown in FIG. 5B, in the second stage of the first erase verify operation, the controller 202 applies the first pass voltage _Vpass1 to connect the first set of memories. Word lines WL4 and WL6 of cell 502 and top virtual word line DWLT0. That is, in the second phase of the first erase verify operation, the controller 202 applies only the first pass voltage _Vpass1 to the word line of the first portion of the memory cells coupled to the first set of memory cells 502. Moreover, in the second phase of the first erase verify operation, the controller 202 also applies the erase verify voltage V _VFY to the word lines WL5 and WL7 connected to the first set of memory cells 502. That is, in the second phase of the first erase verify operation, the controller 202 applies the erase verify voltage V _VFY to the word line of the second portion of the memory cells coupled to the first set of memory cells 502. In two stages of the first erase verify operation, controller 202 applies a second pass voltage _Vpass2 to the word line connected to the second set of memory cells 504.

In the first phase of the first erase verify operation, when an induced current flows through the memory string 500, the first portion of the memory cells of the first set of memory cells 502 are considered to be erased successfully and verified by the first erase verify operation. The first stage. In the second phase of the first erase verify operation, when an induced current flows through the memory string 500, the second portion of the memory cells of the first set of memory cells 502 are deemed to be erased successfully and verified by the first erase verify operation. second stage.

The first stage of the first group of memory cells 502 passes through the first stage of the first erase verify operation and the second stage of the first set of memory cells 502 passes the second stage of the first erase verify operation In the case of the first group of memory cells 502, the first erase verification operation is performed. The first portion of the first group of memory cells 502 does not pass the first phase of the first erase verify operation and/or the second portion of the first set of memory cells 502 does not pass the first erase verify operation In the second phase of the case, the first set of memory cells 502 does not pass the first erase verify operation and is considered to be unsuccessful.

When the first set of memory cells 502 pass the two stages of the first erase verify operation, a second erase verify operation is performed on the second set of memory cells 504. In other words. After the two stages of the first erase verify operation, the first set of memory cells 502 are deemed to have successfully erased, and a second erase verify operation is performed on the second set of memory cells 504. When the controller 202 performs a second erase verify operation on the second group of memory cells 504, as shown in FIG. 5C, the controller 202 applies an erase verify voltage V _VFY (eg, 0~1V) to connect to the second group of memory cells. The word line of 504 applies the erase verify voltage V _VFY to the word lines WL0 WL WL3 and the bottom dummy word line DWLB1. The controller 202 also applies a first pass voltage _Vpass1 to the word line connected to the first set of memory cells 502. The second pass voltage V _pass2 greater than the erase verify voltage V _VFY. When the sense current flows through the memory string 500, the second set of memory cells 504 are deemed to be erased successfully and verified by the second erase verify operation. When the sense current does not flow through the memory string 500, the second set of memory cells 504 are deemed to be unsuccessful in erasing and fail the second erase verify operation. When the first group of memory cells 502 pass the first erase verify operation and the second set of memory cells 504 pass the second verify operation, the controller 202 sets the memory cell string 500 to be erased successfully, and the end includes the first erase verify operation. And the second erase verification operation of the verification operation.

Please refer to Figures 6A, 6B and 6C. In the present embodiment, the memory cells of the memory cell string 600 include a first group of memory cells 602 and a second group of memory cells 604. FIG. 6A illustrates performing a first erase verify operation on the first set of memory cells 602. FIG. 6B illustrates a first stage of performing a second erase verification operation only on a first partial memory cell of the second group of memory cells 604, and FIG. 6C illustrates a first stage of only the second set of memory cells 604 The second part of the memory cell performs the second phase of the second erase verification operation. The first set of memory cells 602 includes memory cells coupled to word lines WL4, WL5, WL6, and WL7 and virtual memory cells coupled to top dummy word line DWLT0. The second set of memory cells 604 includes memory cells coupled to word lines WL0, WL1, WL2, and WL3 and virtual memory cells coupled to bottom dummy word line DWLB1. When the controller 202 performs a first erase verify operation on the first set of memory cells 602 and a second erase verify operation on the second set of memory cells 604, the controller 202 provides a positive voltage (eg, 1V) to the bit line BL. And a voltage (for example, 0V) to the common source line CSL. At the same time, the serial selection lines SSL0 and SSL1 and the top virtual word line DWLT1 are applied with a first pass voltage _Vpass1 . The bottom dummy word line DWLB0 and the ground selection line GSL are applied with a second pass voltage _Vpass2 . The first pass voltage _{Vpass1 is} greater than the second pass voltage _Vpass2 .

When the controller 202 performs a first erase verify operation on the first group of memory cells 602, as shown in FIG. 6A, the controller 202 applies an erase verify voltage V _VFY (eg, 0~1V) to connect to the first group of memory cells. The word line of 602 applies the erase verify voltage V _VFY to the word lines WL4 WL WL7 and the top dummy word line DWLT0. Controller 202 also applies a second pass voltage _Vpass2 to the word line connected to the second set of memory cells 604. A first pass voltage V _pass1 greater than the erase verify voltage V _VFY. After applying the erase verify voltage V _VFY to the word line connecting the first group of memory cells 602 and the second pass voltage V _pass2 to the word line connected to the second group of memory cells 604, when an induced current flows through the memory cell In tandem 600, the first set of memory cells 602 is considered to be erased successfully and verified by the first erase. When the induced current fails to flow through the memory string 600, the first set of memory cells 602 is deemed to be unsuccessful in erasing and fails the first erase verify operation.

After the first set of memory cells 602 pass the first erase verify operation, a second erase verify operation is performed on the second set of memory cells 604. That is, in the case where the first group of memory cells 602 is deemed to be erased successfully and the first erase verify operation is performed, a second erase verify operation is performed on the second set of memory cells 604. In this embodiment, the second erase verification operation includes The two phases, the first phase of the second erase verify operation and the second phase of the second erase verify operation.

When the controller 202 performs a second erase verify operation on the second group of memory cells 604, first, as shown in FIG. 6B, in the first stage of the second erase verify operation, the controller 202 applies only the erase verify voltage V. _{The VFY is} coupled to the word lines WL1 and WL3 of the second group of memory cells 604 and the bottom dummy word line DWLB1. That is, in the first stage of the second erase verify operation, the controller 202 applies only the erase verify voltage V _VFY to the word line of the first portion of the memory cells connected to the second set of memory cells 604. Moreover, in the first phase of the second erase verify operation, the controller 202 also applies a second pass voltage _Vpass2 to the word lines WL0 and WL2 connected to the second set of memory cells 604. That is, in the first stage of the second erase verify operation, the controller 202 applies the second pass voltage _Vpass2 to the word line connecting the second portion of the memory cells of the second set of memory cells 604. The second pass voltage V _pass2 greater than the erase verify voltage V _VFY.

Secondly, after the first stage of the second erase verify operation, in the second stage of the second erase verify operation, as shown in FIG. 6C, the controller 202 applies the second pass voltage _Vpass2 to the second group. The word lines WL1 and WL3 of the memory cell 604 and the bottom dummy word line DWLB1. That is, in the second phase of the second erase verify operation, the controller 202 applies the second pass voltage _Vpass2 to the word line of the first portion of the memory cells coupled to the second set of memory cells 604. Moreover, in the second phase of the second erase verify operation, the controller 202 also applies the erase verify voltage V _VFY to the word lines WL0 and WL2 connected to the second set of memory cells 604. That is, in the second phase of the second erase verify operation, the controller 202 applies the erase verify voltage V _VFY to the word line of the second portion of the memory cells coupled to the second set of memory cells 604. In two stages of the second erase verify operation, the controller 202 applies a first pass voltage _Vpass1 to the word line connected to the first set of memory cells 602.

In the first stage of the second erase verification operation, when the induced current flows through the memory string 600, the first portion of the memory cells of the second group of memory cells are regarded as the erased successfully and the second erase verify operation is performed. One stage. In the second phase of the second erase verification operation, when the induced current flows through the memory string 600, the second portion of the memory cells of the second group of memory cells are regarded as the erase succeeding and the second erase verify operation is performed. Two stages.

The first stage of the second group of memory cells 604 passes through the first stage of the second erase verify operation and the second stage of the second set of memory cells 604 passes the second stage of the second erase verify operation In the case of the second memory cell 604, the second erase verify operation is performed. The first portion of the memory cell of the second group of memory cells 604 does not pass the first phase of the second erase verify operation and/or the second portion of the memory of the second set of memory cells 604 does not pass the second erase verify operation In the second phase of the case, the second memory cell 604 does not pass the second erase verify operation and is considered to be unsuccessful in erasing.

When the first group of memory cells 602 pass the first erase verify operation and the second set of memory cells 604 pass the second erase verify operation, the controller 202 sets the memory cell string 600 to be erased successfully, and the end includes the first erase. Verification operation and erase verification operation of the second erase verification operation.

Please refer to Figures 7A to 7D. In the present embodiment, the memory cells of the memory cell array 700 include a first group of memory cells 702 and a second group of memory cells 704. FIG. 7A illustrates a first stage of performing a first erasure verification operation only on a first partial memory cell of the first group of memory cells 702, and FIG. 7B illustrates a first stage of only the first group of memory cells 702. The second part of the memory cell performs the second phase of the first erase verification operation. FIG. 7C illustrates a first stage of performing a second erase verify operation on only a first portion of the memory cells of the second set of memory cells 704, and a 7D plot showing only one of the second set of memory cells 704 The second part of the memory cell performs the second phase of the second erase verification operation. The first set of memory cells 702 includes memory cells coupled to word lines WL4, WL5, WL6, and WL7 and virtual memory cells coupled to top virtual word line DWLT0. The second set of memory cells 704 includes memory cells coupled to word lines WL0, WL1, WL2, and WL3 and virtual memory cells coupled to bottom dummy word line DWLB1. When the controller 202 performs a first erase verify operation on the first set of memory cells 702 and a second erase verify operation on the second set of memory cells 704, the controller 202 provides a positive voltage (eg, 1V) to the bit line BL. And a voltage (for example, 0V) to the common source line CSL. At the same time, the serial selection lines SSL0 and SSL1 and the top virtual word line DWLT1 are applied with a first pass voltage _Vpass1 . The bottom dummy word line DWLB0 and the ground selection line GSL are applied with a second pass voltage _Vpass2 . The first pass voltage _{Vpass1 is} greater than the second pass voltage _Vpass2 .

In the present embodiment, the first erase verify operation includes two phases, a first phase of the first erase verify operation and a second phase of the first erase verify operation. When the controller 202 performs a first erase verify operation on the first group of memory cells 702, first, as shown in FIG. 7A, in the first stage of the first erase verify operation, the controller 202 applies only the erase verify voltage V. _{The VFY is} coupled to the word lines WL4 and WL6 of the first group of memory cells 702 and the top dummy word line DWLT0. That is, in the first stage of the first erase verify operation, the controller 202 applies only the erase verify voltage V _VFY to the word line of a first portion of the memory cells coupled to the first set of memory cells 702. Moreover, in the first stage of the first erase verify operation, the controller 202 also applies a first pass voltage _Vpass1 to the word lines WL5 and WL7 connected to the first set of memory cells 702. That is, in the first stage of the first erase verify operation, the controller 202 applies the first pass voltage _Vpass1 to the word line of a second portion of the memory cells connected to the first set of memory cells 702. A first pass voltage V _pass1 greater than the erase verify voltage V _VFY.

Secondly, after the first stage of the first erase verify operation, as shown in FIG. 7B, in the second stage of the first erase verify operation, the controller 202 applies the first pass voltage _Vpass1 to connect the first set of memories. Word lines WL4 and WL6 of cell 702 and top virtual word line DWLT0. That is, in the second phase of the first erase verify operation, the controller 202 applies only the first pass voltage _Vpass1 to the word line of the first portion of the memory cells coupled to the first set of memory cells 702. Moreover, in the second phase of the first erase verify operation, the controller 202 also applies the erase verify voltage V _VFY to the word lines WL5 and WL7 connected to the first set of memory cells 502. That is, in the second phase of the first erase verify operation, the controller 202 applies the erase verify voltage V _VFY to the word line of the second portion of the memory cells coupled to the first set of memory cells 702. In two stages of the first erase verify operation, controller 202 applies a second pass voltage _Vpass2 to the word line connected to the second set of memory cells 704.

In the first phase of the first erase verify operation, when an induced current flows through the memory string 700, the first portion of the memory cells of the first set of memory cells 702 are deemed to be erased successfully and verified by the first erase verify operation. The first stage. In the second phase of the first erase verify operation, when an induced current flows through the memory string 700, the second portion of the memory cells of the first set of memory cells 702 are deemed to be erased successfully and verified by the first erase verify operation. second stage.

The first stage of the first group of memory cells 702 passes through the first stage of the first erase verify operation and the second part of the first set of memory cells 702 passes the second stage of the first erase verify operation In the case of the first group of memory cells 702 through the first erase Verify the operation. The first portion of the first group of memory cells 702 does not pass the first phase of the first erase verify operation and/or the second portion of the first set of memory cells 702 does not pass the first erase verify operation In the second phase of the case, the first set of memory cells 702 does not pass the first erase verify operation and is considered to be unsuccessful.

After the first set of memory cells 702 pass the two stages of the first erase verify operation, a second erase verify operation is performed on the second set of memory cells 704. In other words. After the two stages of the first erase verify operation, the first set of memory cells 702 are deemed to be erased successfully and the first erase verify operation is performed on the second set of memory cells 704 by the first erase verify operation. . In the present embodiment, the second erase verify operation includes two phases, a first phase of the second erase verify operation and a second phase of the second erase verify operation.

When the controller 202 performs a second erase verify operation on the second group of memory cells 704, first, as shown in FIG. 7C, in the first stage of the second erase verify operation, the controller 202 applies only the erase verify voltage V. _{The VFY is} coupled to the word lines WL1 and WL3 of the second group of memory cells 704 and the bottom dummy word line DWLB1. That is, in the first stage of the second erase verify operation, the controller 202 applies only the erase verify voltage V _VFY to the word line of the first portion of the memory cells connected to the second set of memory cells 604. Moreover, in the first phase of the second erase verify operation, the controller 202 also applies a second pass voltage _Vpass2 to the word lines WL0 and WL2 connected to the second set of memory cells 604. That is, in the first stage of the second erase verify operation, the controller 202 applies the second pass voltage _Vpass2 to the word line connecting the second portion of the memory cells of the second set of memory cells 604. The second pass voltage V _pass2 greater than the erase verify voltage V _VFY.

Secondly, after the first stage of the second erase verify operation, in the second stage of the second erase verify operation, as shown in FIG. 7D, the controller 202 applies the second pass voltage _Vpass2 to the second group. The word lines WL1 and WL3 of the memory cell 604 and the bottom dummy word line DWLB1. That is, in the second phase of the second erase verify operation, the controller 202 applies the second pass voltage _Vpass2 to the word line of the first portion of the memory cells connected to the second set of memory cells 704. Moreover, in the second phase of the second erase verify operation, the controller 202 also applies the erase verify voltage V _VFY to the word lines WL0 and WL2 connected to the second set of memory cells 704. That is, in the second phase of the second erase verify operation, the controller 202 applies the erase verify voltage V _VFY to the word line of the second portion of the memory cells coupled to the second set of memory cells 604. In two stages of the second erase verify operation, the controller 202 applies a first pass voltage _Vpass1 to the word line connected to the first set of memory cells 702.

In the first phase of the second erase verify operation, when the induced current flows through the memory string 700, the first portion of the memory cells of the second set of memory cells 704 are deemed to be erased successfully and verified by the second erase verify operation. The first stage. In the second phase of the second erase verify operation, when the induced current flows through the memory string 700, the second portion of the memory cells of the second set of memory cells 704 are deemed to be erased successfully and verified by the second erase verify operation. second stage.

The first stage of the second group of memory cells 704 passes through the first stage of the second erase verify operation and the second stage of the second set of memory cells 704 passes the second stage of the second erase verify operation In the case of the second memory cell 704, the second erase verify operation is performed. The first portion of the memory cell of the second group of memory cells 704 does not pass the first phase of the second erase verify operation and/or the second portion of the second group of memory cells 704 fails to pass the first In the case of the second erase verify operation, the second memory cell 704 does not pass the second erase verify operation and is considered to be unsuccessful.

When the first group of memory cells 702 pass the first erase verify operation and the second set of memory cells 704 pass the second erase verify operation, the controller 202 sets the memory cell string 700 to be erased successfully, and the end includes the first erase Verification operation and erase verification operation of the second erase verification operation.

In some embodiments of the present invention, the first portion of the memory cells of the first group of memory cells/the second group of memory cells are connected to the odd lines of the word lines coupled to the first group of memory cells/the second group of memory cells. The digital element line, and the second portion of the memory of the first group of memory cells/the second group of memory cells is coupled to the even digital line of the word line coupled to the first group of memory cells/the second group of memory cells. In other embodiments of the present invention, the first portion of the memory cells of the first group of memory cells/the second group of memory cells are coupled to the word lines coupled to the first group of memory cells/the second group of memory cells. The even digital line, and the second portion of the memory of the first group of memory cells/the second group of memory cells is coupled to the odd-numbered element lines of the word line coupled to the first group of memory cells/the second group of memory cells. The first portion of the memory cells of the first group of memory cells/the second group of memory cells is different from the second portion of the memory cells of the first group of memory cells/the second group of memory cells. For example, the first part of the memory cell of the first group of memory cells/the second group of memory cells is the odd memory cell of the first group of memory cells/the second group of memory cells, and the first group of memory cells/the second group of cells The second part of the memory cell is the even memory of the first group of memory cells/the second group of memory cells.

In the above embodiment of the present invention, the first pass voltage _{Vpass1 is} set higher than the first pass voltage _Vpass1 , based on a substrate of the three-dimensional memory 204, because the spatial position of the first group of memory cells is higher than the spatial position of the second group of memory cells. two pass voltage V _pass2, is about the same so that the first impact and the second voltage is equal to V _pass2 by influencing the electric field or the electric field voltage V _pass1. In other embodiments of the invention, the first pass voltage _Vpass1 may be equal to or less than the second pass voltage _Vpass2 .

In various embodiments of the present invention, a memory cell of a memory string may be grouped into at least two groups of memory cells, and an erase verify operation is performed on the different groups of memory cells. Subsequent erase verification operations are performed on subsequent memory cell groups only when an erase verify operation performed on a set of memory cells is passed. When the erase verify operation performed on a group of memory cells fails, the erase voltage is increased, and the boosted erase voltage is applied to the memory cell column to erase the memory cell string. By dividing the memory cells in the memory cell into a plurality of memory cell groups, the probability of increasing the erase voltage and applying the improved erase voltage can be reduced. Furthermore, a erase verify operation may include two stages of performing a first phase of the erase verify operation on a word line (eg, an odd digital element line) connected to a first portion of the memory cells of a group of memory cells, and then A second stage of the erase verify operation can be performed on the word lines (e.g., even digital lines) of the second portion of the memory cells connected to a set of memory cells. This can alleviate the erase verification error caused by the residual charge.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

An erase verification method for a three-dimensional memory, the three-dimensional memory comprising at least one memory string, the at least one memory string comprising a plurality of memory cells, the memory cells comprising a first group of memory cells and a a second set of memory cells, each of the memory cells being coupled to a word line, the erase verification method comprising: performing a first erase verify operation on the first set of memory cells, wherein the first erase verify operation The method includes: applying a erase verify voltage to the word lines coupled to a first portion of the memory cells of the first group of memory cells and a first pass in a first stage of the first erase verifying process And the voltage is coupled to the word lines of a second portion of the memory cells of the first group of memory cells; and after the first phase of the first erase verification, the first erase verification is performed a second stage of applying the erase verify voltage to the word lines of the second portion of the memory cells coupled to the first group of memory cells and the first pass voltage to be coupled to the first group The word lines of the first portion of the memory cells of the memory cell; A set of memory cells after performing the first erase verify operation is verified as erased in a success, the second set of memory cells a second erase verify operation performed at the first set of memory cells. The erase verification method according to claim 1, wherein the first group of memory cells are adjacent to each other, and the second group of memory cells are adjacent to each other. . The erase verification method of claim 1, wherein the second erase verification operation comprises: applying a erase verification voltage to the first stage of the second erase verification to be coupled to the The word lines of a first portion of the memory cells of the second group of memory cells and a second pass voltage to the word lines of a second portion of the memory cells coupled to the second group of memory cells, The second partial memory cell of the second group of memory cells is different from the first partial memory cell of the second group of memory cells; and after the first phase of the second erasure verification, the a second stage of the second erase verification, applying the erase verify voltage to the word lines of the second portion of the memory cells coupled to the second group of memory cells and the second pass voltage to the coupling The word lines of the first portion of the memory cells of the second group of memory cells. The erase verification method of claim 3, wherein the first pass voltage is greater than the second pass voltage. The erase verification method according to claim 1, wherein the word lines comprise a plurality of even-numbered digital element lines and a plurality of odd-numbered digital lines, the first part of the first group of memory cells The memory cells are connected to the odd digital lines coupled to the word lines of the first group of memory cells, and the second portion of the first group of memory cells are coupled to the first The even number of meta-elements of the set of word lines of a set of memory cells. The wiping verification method as described in claim 1, wherein the second erasing verification operation comprises: In a first stage of the second erase verification, applying a erase verify voltage to the word lines coupled to a first portion of the memory cells of the second group of memory cells and a second pass voltage to Coupled in the word lines of a second portion of the memory cells of the second group of memory cells, the second portion of the memory cells of the second group of memory cells being different from the first portion of the second group of memory cells a portion of the memory cell; and after the first phase of the second erase verification, in the second phase of the second erase verification, applying the erase verify voltage to the second set of memories The word lines of the second portion of the cells and the second pass voltage are coupled to the word lines of the first portion of the memory cells of the second group of memory cells. The erase verification method according to claim 7, wherein the word lines comprise a plurality of even-numbered digital element lines and a plurality of odd-numbered digital lines, the first part of the second group of memory cells The memory cells are connected to the odd digital lines coupled to the word lines of the second group of memory cells, and the second portion of the second group of memory cells are coupled to the first The even digital lines of the word lines of the two sets of memory cells. The wiping verification method as described in claim 1, further comprising: in the case where the first group of memory cells are verified as being unsuccessful in erasing or the second group of memory cells is verified as being unsuccessful in erasing, Increasing an erase voltage; and applying the increased erase voltage to erase the at least one memory string. The erase verification method according to claim 1, wherein the second partial memory cell of the first group of memory cells is different from the first partial memory cell of the first group of memory cells. A memory system comprising: a three-dimensional memory comprising at least one memory string extending vertically through a plurality of layers of the three-dimensional memory, the at least one memory string comprising a plurality of memory cells, the memory cells comprising a first group of memory cells and a second group of memory cells, each of the memory cells being coupled to a word line; and a controller coupled to the three-dimensional memory for performing the first group of memory cells a first erase verify operation, and after performing the first erase verify operation on the first set of memory cells, the first set of memory cells are verified as being erased successfully, on the second set of memory cells Performing a second erase verifying operation, wherein the first erase verifying operation includes: applying a erase verify voltage to a first one of the first set of memory cells in a first stage of the first erase verifying The word lines of the first portion of the memory cells and the first pass voltages to the word lines of a second portion of the memory cells coupled to the first group of memory cells; and the first erase After the first stage of verification, the first erase test a second stage of applying the erase verify voltage to the word lines of the second portion of the memory cells coupled to the first group of memory cells and the first pass voltage to be coupled to the first The word lines of the first portion of the memory cells of the group of memory cells.