CN102103333B - Method for baking photoresist and device using method - Google Patents
Method for baking photoresist and device using method Download PDFInfo
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- CN102103333B CN102103333B CN 200910201295 CN200910201295A CN102103333B CN 102103333 B CN102103333 B CN 102103333B CN 200910201295 CN200910201295 CN 200910201295 CN 200910201295 A CN200910201295 A CN 200910201295A CN 102103333 B CN102103333 B CN 102103333B
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Abstract
The invention discloses a method for baking a photoresist, which adds the difference time in baking process links according to the difference of the exposure time of each exposure region, thus each exposure region has the same time interval between exposure and baking. The invention simultaneously discloses a device using the method. When in use, the method and device for baking the photoresist disclosed by the invention can effectively reduce the baking difference among different exposure regions caused by time delay because the exposure is not simultaneously performed and are beneficial to the more excellent uniformity of a key dimension.
Description
Technical field
The present invention relates to the optical semiconductor carving technology, particularly relate to a kind of device that toasts the method for photoresist and use this method.
Background technology
In field of semiconductor manufacture, photoetching process is very important technological process at present.Photoetching process with light acid amplified positive photoresist (the PAG photoresist is hereinafter to be referred as photoresist) is example: photo-etching technological process mainly is to utilize lithographic equipment, photon energy is arrived the respective regions of photoresist according to the mask graph distribution of shapes.Photoresist has photosensitivity, and chemical reaction can take place the photoresist that is mapped to by illumination, produces a little light acid; The photoresist chemical property that is mapped to by illumination is not constant.The silicon chip that then will adhere to photoresist is sent into the drip pan heating, Here it is back baking process (PEB), and suitable temperature makes that the light acid of exposure area increases in numbers swiftly, and increases the rate of diffusion of light acid simultaneously.By the back baking, the light acid number amount in the exposure area reaches certain numerical value, makes this regional photoresist satisfy the demand of developing.Use the developer solution immersion lithography glue that is complementary with this photoresist.The photoresist that contains light acid will generate the granule object with the developer solution reaction, wash its removal by water.The photoresist that does not contain or contain micro-light acid still exists, and stays on the silicon chip, forms the figure similar to mask graph at last.As seen, PEB technology directly influences photoetching glue pattern on the desired silicon chip of design.
The silicon wafer exposure process is silicon chip to be divided into some similar zones (be exposure field, shot), each zone is according to set order, the independent exposure technology of carrying out.For example, silicon chip is divided into n similar area, the time of a regional exposure consumption is t.When All Ranges exposure on a slice silicon chip was finished, the mistiming between first exposure area and n the exposure area was (n-1) * t.Because the existence of this mistiming produces the life span difference of light acid in the different exposure areas.Among light acid was in all the time and derives and spread, the exposure area in life-span long (namely producing early) produced more light acid and is diffused into other territory, non-exposed area, causes and crosstalks.
The baking process that widely uses in the industry is the silicon chip through overexposure to be kept flat on the hot plate toast at present, gives each exposure field heating simultaneously.Drip pan has higher temperature accuracy and temperature homogeneity.The exposure area of (namely producing different constantly) of different life-spans is heated simultaneously, and in the exposure area of life-span length, the quantity of light acid is big, and the zone of diffusion is big, causes the trend that figure increases; Otherwise the exposure area that the life-span is short.The similarity of figure reduced after on the same silicon chip developed in different exposure areas, had influenced the homogeneity of figure on the full wafer.
Especially entering 45 nanometers or high technology node (as the 32nm node) more, and under the increasing situation of die size (18 inch diameter silicon chip), the deficiency of traditional baking process is outstanding all the more.
Summary of the invention
The objective of the invention is to improve the homogeneity CDU of silicon chip critical size in the photoetching process in order to solve the problem of the poor silicon chip critical dimension uniformity variation that causes of time shutter.
The present invention discloses a kind of method of toasting photoresist, in the process of baking photoresist, according to the difference of each exposure area time shutter, add the difference time in the baking process link, make each exposure area of silicon chip between exposure and baking, be arranged the identical time interval.
Wherein, different stoving times are to realize by changing the used hot plate of baking and the relative position between the silicon chip.
Wherein, employing is toasted each zone of silicon chip with the identical order of being exposed in each exposure area.
Use the present invention to toast the apparatus for baking of the method for photoresist, comprising: hot plate, photoresist is heated, have higher temperature homogeneity and temperature accuracy, temperature value is decided according to the demand of different photoresists; Cold drawing, the edge that is positioned at silicon chip turnover hot plate is connected with hot plate, has higher temperature homogeneity and temperature accuracy, and temperature value is room temperature; Motion driving system, the relative position between control silicon chip and hot plate; And the silicon chip support system, support silicon chip, have excellent heat insulation property.
Wherein, hot plate can be two can relative motion hot plate.
Wherein, both can carry out the single face heating to silicon chip with one group of bake module, also can carry out two-sided heating to silicon chip with two groups of bake module.
By photoresist baking process method of the present invention and device, can make the figure in different exposure areas (shot) on the silicon chip have higher similarity, can improve the homogeneity of photoetching glue pattern on the whole silicon wafer.
Description of drawings
Below in conjunction with Figure of description the present invention is further detailed, wherein:
Figure 1 shows that apparatus for baking of the present invention and silicon chip position view;
Fig. 2-16 is depicted as apparatus for baking and silicon chip position view in the bake process of a preferred embodiment of the present invention;
Figure 17 shows that apparatus for baking structural representation of the present invention;
Figure 18 shows that cold drawing structural representation of the present invention.
Embodiment
Below, describe in detail according to a preferred embodiment of the invention by reference to the accompanying drawings.
Figure 1 shows that apparatus for baking of the present invention and silicon chip position view, wherein, A applies photoresist and through the silicon chip of overexposure.B is hot plate, is used for heating silicon chip A.D supports the pillar that silicon chip is used.C is cold drawing, is used for the cooling silicon chip.Digital size on the silicon chip represents exposure area (shot) exposure sequencing separately.Numeral 1 this shot of expression exposes at first on the silicon chip, and numeral 9 these shot of expression expose at last.Hot plate B has higher temperature homogeneity and temperature accuracy, and temperature value is decided according to the demand of different photoresists.Cold drawing C has higher temperature homogeneity and temperature accuracy, and temperature value is room temperature.
Fig. 2-16 is depicted as apparatus for baking and silicon chip position view in the bake process of a preferred embodiment of the present invention.Fig. 2 show silicon chip before entering baking process with the position corresponding relation of hot plate B and cold drawing C.Be not limited to this a kind of position corresponding relation in the practical application.Silicon chip A among Fig. 2 stops to move the distance of a shot width along the X-axis positive dirction after, makes shot 1 enter hot plate B2 below, and shot 6 enters cold drawing C4 below.Position, mobile back as shown in Figure 3.Behind the time shutter t through a shot, silicon chip continues to move a shot width distance along the X-axis positive dirction, makes shot 2 also enter hot plate B2 below, and shot5 enters the C4 below.Repeat above-mentioned mobile step, shot 3 is moved on to the B2 below, shot4 moves on to the C4 below.In a shot time shutter t, silicon chip moves along the X-axis positive dirction, makes shot1, shot2 and shot3 be positioned at hot plate B1 below.Position, mobile back as shown in Figure 4.In this time t, C3, B2 and C4 keep relative position constant, and integral body moves a shot length distance along the Y-axis negative direction.Position, mobile back as shown in Figure 5.Along the X-axis negative direction, similar above-mentioned move mode toasts shot4, shot5 and shot6 on the silicon chip successively with silicon chip A.Position, mobile back as shown in Figure 6.C1, B1 and C2 keep relative position constant, and integral body moves a shot length distance along the Y-axis negative direction.Position, mobile back as shown in Figure 7.Silicon chip A along the X-axis positive dirction, as above-mentioned movement, is toasted shot7, shot8 and shot9 on the silicon chip successively.Position, mobile back as shown in Figure 8.Suppose that the required stoving time of the type photoresist is T, the stoving time of shot1 is from entering hot plate B2 below constantly.In present photoetching process in the industry, the specified stoving time T of photoresist is greater than n*t.After finishing above-mentioned action, silicon chip A moves to hot plate B2 below, and position, mobile back as shown in Figure 9.Total stoving time of supposing shot1 is t1, and when t1 equaled T, silicon chip A, stopped after mobile shot width distance along the X-axis positive dirction in position shown in Figure 9, makes shot1 enter cold drawing C1 below.Per stand-by period t repeats above-mentioned move mode.Position, mobile back as shown in figure 10.Repeat above-mentioned mobile step, position, mobile back as shown in figure 11.Silicon chip A repeats above-mentioned mobile step along the X-axis negative direction.Position, mobile back as shown in figure 12.Repeat above-mentioned mobile step, position, mobile back as shown in figure 13.Repeat above-mentioned mobile step, position, mobile back as shown in figure 14.Silicon chip A is shifted out cold drawing C1 below, and position, mobile back as shown in figure 15.Hot plate and cold drawing return to position shown in Figure 16.Silicon chip is moved on to specified containers, and a slice silicon chip treatment scheme is finished.Every pending silicon chip is according to said method handled.
Figure 17 shows that apparatus for baking structural representation of the present invention.In Figure 17, B is resistance wire hot type hot plate.The resistance wire heating is to use wider method in the industry at present.C is cold drawing.Direct current generator 1 is used for drive screw 4 rotations.There is screw thread handle 3 and screw rod 4 junctions.Handle 3 and hot plate cold drawing separately, perhaps the silicon chip platform is connected.When screw rod 4 rotates under the driving of motor 1, drive handle 3 and move at Y and directions X.Handle 3 drives each hot plate cold drawing that connects or silicon chip motion.In the preferred embodiment as Fig. 2, C1, B1 and C2 are connected on the same handle, and C3, B2 and C4 are connected on the same handle.Each handle is respectively by independently screw rod 4 and motor 1 drive.Can utilize software programming and interlock circuit to realize that mode is moved described in " technical solution ".Support column D is used for the carrying silicon chip.Main frame 2 is used for fixed electrical machinery 1 and positioning screw 4, and the support of total system is provided.
The cold drawing C-structure as shown in figure 18.Cold drawing C is the cavity of hollow, by several cavity 5 be combined intos independently.Each little cavity outwards connects a water inlet and a water delivering orifice.Inside cavity intercepts with a dividing plate 6, and the lower partition and cavity inner wall leave the space of enough liquid flows.After the water of normal temperature flows into the loculus body, flow to cavity bottom, absorb the heat of being come by the silicon chip surface conduction, the temperature remains within the normal range to make silicon chip surface.The water that flows out cavity is sent to temperature control system (TCU), and water temperature is adjusted to design temperature, again water is sent into cavity, recycles.
Described in this instructions is several preferred embodiment of the present invention, and above embodiment is only in order to illustrate technical scheme of the present invention but not limitation of the present invention.All those skilled in the art all should be within the scope of the present invention under this invention's idea by the available technical scheme of logical analysis, reasoning, or a limited experiment.
Claims (3)
1. method of toasting photoresist, it is characterized in that: in the process of baking photoresist, according to the difference of each exposure area time shutter, add the difference time in the baking process link, make each exposure area of silicon chip between exposure and baking, be arranged the identical time interval; The described identical time interval is to realize by changing the used hot plate of baking and the relative position between the silicon chip; Adopt and with the identical order of being exposed in each exposure area each zone of silicon chip is toasted.
2. use the apparatus for baking of the method for baking photoresist as claimed in claim 1, it is characterized in that comprising:
Hot plate heats photoresist, has higher temperature homogeneity and temperature accuracy, and temperature value is decided according to the demand of different photoresists;
Cold drawing, the edge that is positioned at silicon chip turnover hot plate is connected with hot plate, has higher temperature homogeneity and temperature accuracy, and temperature value is room temperature;
Motion driving system, the relative position between control silicon chip and hot plate, wherein, this motion driving system comprises the handle that is connected with hot plate and cold drawing; The handle that is connected with the silicon chip support system; The main frame that is used for fixed electrical machinery and screw rod; Described each handle is respectively by independently screw rod and motor-driven, and its corresponding screw rod is by being threaded; And
The silicon chip support system supports silicon chip, has excellent heat insulation property.
3. apparatus for baking as claimed in claim 2, it is characterized in that described hot plate be two can relative motion hot plate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910201295 CN102103333B (en) | 2009-12-17 | 2009-12-17 | Method for baking photoresist and device using method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910201295 CN102103333B (en) | 2009-12-17 | 2009-12-17 | Method for baking photoresist and device using method |
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| CN102103333A CN102103333A (en) | 2011-06-22 |
| CN102103333B true CN102103333B (en) | 2013-08-14 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437018B (en) * | 2011-11-02 | 2017-11-24 | 上海华虹宏力半导体制造有限公司 | Baking method and equipment for critical dimension uniformity in wafer after improvement etching |
| CN104423346B (en) * | 2013-08-30 | 2017-01-18 | 华润赛美科微电子(深圳)有限公司 | Control method, control device and control method for silicon wafer baking |
| CN111221226A (en) * | 2018-11-27 | 2020-06-02 | 上海微电子装备（集团）股份有限公司 | Post-exposure baking method and device for photoresist layer |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1933100A (en) * | 2005-09-14 | 2007-03-21 | 大日本网目版制造株式会社 | Apparatus for and method of processing substrate subjected to exposure process |
| CN101046635A (en) * | 2006-03-29 | 2007-10-03 | 联华电子股份有限公司 | Control method and operation system for wet photoetching process |
| CN101093787A (en) * | 2006-06-20 | 2007-12-26 | 东京应化工业株式会社 | Substrate treatment apparatus |
| WO2008013211A1 (en) * | 2006-07-26 | 2008-01-31 | Tokyo Electron Limited | Substrate processing method, program, computer-readable recording medium, and substrate processing system |
| CN101408738A (en) * | 2007-10-12 | 2009-04-15 | 上海华虹Nec电子有限公司 | Split vertical type hot plate system in photolithography guide rail equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7789576B2 (en) * | 2007-03-27 | 2010-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | PEB embedded exposure apparatus |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1933100A (en) * | 2005-09-14 | 2007-03-21 | 大日本网目版制造株式会社 | Apparatus for and method of processing substrate subjected to exposure process |
| CN101046635A (en) * | 2006-03-29 | 2007-10-03 | 联华电子股份有限公司 | Control method and operation system for wet photoetching process |
| CN101093787A (en) * | 2006-06-20 | 2007-12-26 | 东京应化工业株式会社 | Substrate treatment apparatus |
| WO2008013211A1 (en) * | 2006-07-26 | 2008-01-31 | Tokyo Electron Limited | Substrate processing method, program, computer-readable recording medium, and substrate processing system |
| CN101408738A (en) * | 2007-10-12 | 2009-04-15 | 上海华虹Nec电子有限公司 | Split vertical type hot plate system in photolithography guide rail equipment |
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Address after: 201203 Zhangjiang High Tech Park, Shanghai, Zhang Dong Road, No. 1525 Patentee after: Shanghai microelectronics equipment (Group) Limited by Share Ltd Address before: 201203 Zhangjiang High Tech Park, Shanghai, Zhang Dong Road, No. 1525 Patentee before: Shanghai Micro Electronics Equipment Co., Ltd. |