CN102098418B - Amplitude self-adaption synchronous shaping circuit - Google Patents
Amplitude self-adaption synchronous shaping circuit Download PDFInfo
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- CN102098418B CN102098418B CN 201010604887 CN201010604887A CN102098418B CN 102098418 B CN102098418 B CN 102098418B CN 201010604887 CN201010604887 CN 201010604887 CN 201010604887 A CN201010604887 A CN 201010604887A CN 102098418 B CN102098418 B CN 102098418B
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Abstract
The invention relates to a synchronous shaping circuit, in particular relates to an amplitude self-adaption synchronous shaping circuit which comprises a first filter clamping circuit, a second filter clamping circuit, a peak detection circuit, a first voltage comparison circuit, a second voltage comparison circuit, and a first drive shaping circuit and a second drive shaping circuit, wherein, a first synchronous signal of a video signal is input into the first filter clamping circuit; and a second synchronous signal of the video signal is input into the second filter clamping circuit. By the synchronous shaping circuit provided by the invention, peak detection, amplitude self-adaption and drive shaping are carried out on a line-field synchronous signal of a stimulated association rabaudy grande borde (ARGB) signal, thus satisfying the requirements of synchronous signal receiving end at the condition that the voltage amplitude of the circuit can be normally matched, and achieving the condition that a clear signal image is displayed by pixel sampling process by the rear end through driving and shaping the synchronous signals.
Description
Technical field
The present invention relates to synchronous shaping, particularly a kind of amplitude self adaptation synchronous shaping.
Background technology
Present analog rgb (being ARGB) signal, the amplitude of signal is different in different signal source driving situations, the amplitude and the driving force that mainly occur according to signal source, damage when the too high meeting of synchronizing signal amplitude of output causes receiving signal end device or circuit, and then cause the image output display of can not normally sampling; In transmission, transmission, receiving course, there are signal jitter or distortion at simulation ARGB signal simultaneously, particularly under high-frequency image signal input condition, have High-frequency Interference.
Prior art is to processing such as the Chinese patent of above-mentioned situation, and application number is 95119056.3, and name is called self adaption synchronous signal separator.Be a kind of self adaption synchronous signal separator, comprise: the synchronized component that is positioned at rear edge part is contained in vision signal (LUMA) source, described vision signal; Clamp device is in order to be clamped to predetermined level (for example 0 volt) with described rear edge part; Described rear continuous IRE level along part before output reference signal (BACKPORCHREF) generating means, the described clamp device work of the value representation of this signal; Slice level values (SLICELEVEL) generating means, the numerical relation between the described baseline signal value of this clip level value representation (BACKPORCHREF) and the fixed value (for example " 64 "); And composite synchronizing signal (COMPOSITESYNC) generating means, by generation composite synchronizing signal that described vision signal (LPFLUMA2) is compared with described slice level values (SLICELEVEL).But the self adaption synchronous signal of prior art only is the amplitude limit to voltage amplitude, and fails to satisfy the normal coupling requirement of the voltage amplitude of circuit.
Summary of the invention
The invention provides a kind of amplitude self adaptation synchronous shaping, fail to satisfy the technical problem that the normal coupling of the voltage amplitude of circuit requires with the self adaption synchronous signal that solves prior art.
The technical solution used in the present invention is as follows:
A kind of amplitude self adaptation synchronous shaping, described circuit comprises that the first filtering clamp circuit, the second filtering clamp circuit, peak-detector circuit, the first voltage comparator circuit, second voltage comparison circuit, first drive shaping circuit and second and drive shaping circuit, the first synchronizing signal of vision signal is inputted the first filtering clamp circuit, and the second synchronizing signal of vision signal is inputted the second filtering clamp circuit;
The output of the first filtering clamp circuit is connected with the first input end of the first voltage comparator circuit and the input of peak-detector circuit respectively;
The output of the second filtering clamp circuit is connected with the first input end of second voltage comparison circuit;
The output of peak-detector circuit is connected with the second input of the first voltage comparator circuit and the second input of second voltage comparison circuit respectively.
The output of the first voltage comparator circuit and first drives shaping circuit and is connected, drive the first shaping synchronizing signal of shaping circuit output through adjusting by first, the output of second voltage comparison circuit and second drives shaping circuit and is connected, and drives the second shaping synchronizing signal of shaping circuit output through adjusting by second;
Described the first filtering clamp circuit is used for the first synchronizing signal of stable input, and synchronizing signal is stablized in output first, and the second filtering clamp circuit is used for stablizing input the second synchronizing signal, and synchronizing signal is stablized in output second;
Described peak-detector circuit output peak value limitation signal, peak-detector circuit is stablized synchronizing signal to first and is carried out detection, if the first voltage amplitude of stablizing synchronizing signal surpasses predefined first threshold, then the voltage amplitude of peak limiting limitation signal is first threshold;
The first voltage comparator circuit stablize synchronizing signal to first of peak value limitation signal and the first filtering clamp circuit output and is carried out difference and relatively export the first oppositely stable pulse synchronous signal, and the second voltage comparison circuit second is stablized synchronizing signal and carried out difference and relatively export the second reverse stable pulse synchronous signal what peak value limitation signal and the second filtering clamp circuit were exported;
The driving force that first drives shaping circuit increases by the first pulse synchronous signal reaches and the first pulse synchronous signal is driven shaping exports the first shaping synchronizing signal, and the driving force that second drives shaping circuit increases by the second pulse synchronous signal reaches and the second pulse synchronous signal is driven shaping exports the second shaping synchronizing signal.
As a kind of preferred version, described the first synchronizing signal is the line synchronizing signal of vision signal, and described the second synchronizing signal is the field sync signal of vision signal.
As a kind of preferred version, described the first synchronizing signal is the field sync signal of vision signal, and described the second synchronizing signal is the line synchronizing signal of vision signal.
As further preferred version, described the first filtering clamp circuit comprises the first alternating-current resistance, the first filtering clamp resistance, the second filtering clamp resistance and the first duodiode clamp circuit;
The input of the first filtering clamp circuit is connected with the first alternating-current resistance, the first synchronizing signal is carried out filtering through the first alternating-current resistance and is suppressed High-frequency Interference, the first alternating-current resistance is connected with an end of the first filtering clamp resistance, the other end of the first filtering clamp resistance is connected with the output of the first filtering clamp circuit, the first alternating-current resistance is connected with an end of the second filtering clamp resistance with the tie point of the first filtering clamp resistance, the other end of the second filtering clamp resistance is connected with the first duodiode clamp circuit and ground connection, the first duodiode clamp circuit comprises successively the first filtering clamping diode and the second filtering clamping diode that connects, the first filtering clamping diode be connected the tie point of filtering clamping diode and be connected with the output of the first filtering clamp circuit;
The second filtering clamp circuit comprises the second alternating-current resistance, the 3rd filtering clamp resistance, the 4th filtering clamp resistance and the second duodiode clamp circuit;
The input of the second filtering clamp circuit is connected with the second alternating-current resistance, the second synchronizing signal is carried out filtering through the second alternating-current resistance and is suppressed High-frequency Interference, the second alternating-current resistance is connected with an end of the 3rd filtering clamp resistance, the other end of the 3rd filtering clamp resistance is connected with the output of the second filtering clamp circuit, the second alternating-current resistance is connected with an end of the 4th filtering clamp resistance with the tie point of the 3rd filtering clamp resistance, the other end of the 4th filtering clamp resistance is connected with the second duodiode clamp circuit and ground connection, the second duodiode clamp circuit comprises the 3rd filtering clamping diode and the 4th filtering clamping diode that connects successively, and the tie point of the 3rd filtering clamping diode and the 4th filtering clamping diode is connected with the output of the second filtering clamp circuit.
As further preferred version, described peak-detector circuit comprises: crest voltage comparator, peak value triode, the first peak value electric capacity, the first peak resistance and the second peak resistance;
The input of peak-detector circuit is connected with the first input end of crest voltage comparator, the output of peak-detector circuit is connected with the second input of crest voltage comparator, the output of crest voltage comparator is connected with the base stage of peak value triode, the power input of crest voltage comparator and supply power voltage are that the threshold power of first threshold is connected, the emitter of peak value triode is connected with the first peak resistance, the tie point of the emitter of peak value triode and the first peak resistance and supply power voltage are that the threshold power of first threshold is connected, the collector electrode of peak value triode is connected ground connection with the first peak value electric capacity, the first peak resistance ground connection of connecting with the second peak resistance, the tie point of the first peak resistance and the second peak resistance, the collector electrode of peak value triode is connected with the output of peak-detector circuit with the tie point of the first peak value electric capacity.
As further preferred version, described peak-detector circuit comprises: crest voltage comparator, peak value diode, the first peak value electric capacity, the first peak resistance and the second peak resistance;
The input of peak-detector circuit is connected with the second input of crest voltage comparator, the output of peak-detector circuit is connected with the first input end of crest voltage comparator, the output of crest voltage comparator is connected with the positive pole of peak value diode, the power input of crest voltage comparator and supply power voltage are that the threshold power of first threshold is connected, the negative electrode of peak value diode is connected with the output of crest voltage comparator, one end of the first peak resistance and supply power voltage are that the threshold power of first threshold is connected, the other end peak of the first peak resistance is connected ground connection with the first peak value electric capacity, the first peak resistance ground connection of connecting with the second peak resistance, the tie point of the first peak resistance and the second peak resistance, the first peak resistance is connected with the output of peak-detector circuit with the tie point of the first peak value electric capacity.
As further preferred version, described the first voltage comparator circuit comprises: the first voltage comparator, the first voltage comparison resistance and second voltage comparison resistance, the first input end of the first voltage comparator is connected with the first input end of the first voltage comparator circuit, the second input of the first voltage comparator is connected with the second input of the first voltage comparator circuit, the output of the first voltage comparator is connected with output and the first voltage comparison resistance of the first voltage comparator circuit respectively, the output of the first voltage comparator successively with the first voltage comparison resistance, the second input of second voltage comparison resistance and the first voltage comparator is connected to form the first hysteresis loop with hysteretic characteristic;
Described second voltage comparison circuit comprises: the second voltage comparator, tertiary voltage comparison resistance and the 4th voltage comparison resistance, the first input end of second voltage comparator is connected with the first input end of second voltage comparison circuit, the second input of second voltage comparator is connected with the second input of the first voltage comparator circuit, the output of second voltage comparator is connected with output and the tertiary voltage comparison resistance of second voltage comparison circuit respectively, the output of second voltage comparator successively with the tertiary voltage comparison resistance, the second input of the 4th voltage comparison resistance and second voltage comparator is connected to form the second hysteresis loop with hysteretic characteristic.
As preferred version further, if the first synchronizing signal is the line synchronizing signal of vision signal, the second synchronizing signal is the field sync signal of vision signal, and then described the first voltage comparator is high speed voltage comparator;
If the first synchronizing signal is the field sync signal of vision signal, the second synchronizing signal is the line synchronizing signal of vision signal, and then described second voltage comparator is high speed voltage comparator.
As further preferred version, it is characterized in that, described first drives shaping circuit comprises first Schmidt's reverser, the first input that drives shaping circuit is connected with the input of first Schmidt's reverser, and the first output that drives shaping circuit is connected with the output of first Schmidt's reverser;
Described second drives shaping circuit comprises second Schmidt's reverser, and the second input that drives shaping circuit is connected with the input of second Schmidt's reverser, and the second output that drives shaping circuit is connected with the output of second Schmidt's reverser.
As further preferred version, described first threshold is 3.3 volts.
The present invention carries out peak detection, amplitude self adaptation and drives shaping the capable field sync signal of simulation ARGB signal, satisfy the requirement that the synchronizing signal receiving terminal can normally mate at the voltage amplitude of circuit, reach the rear end to pixel sampling processes and displays signal pattern picture clearly by synchronizing signal being driven shaping simultaneously.
Description of drawings
Fig. 1 is the theory diagram of the embodiment of the invention;
Fig. 2 is the circuit theory diagrams of first embodiment of the invention;
Fig. 3 is the circuit theory diagrams of second embodiment of the invention.
Embodiment
The present invention will be further described in detail below in conjunction with the drawings and specific embodiments.
As shown in Figure 1,
Circuit comprises that the first filtering clamp circuit, the second filtering clamp circuit, peak-detector circuit, the first voltage comparator circuit, second voltage comparison circuit, first drive shaping circuit and second and drive shaping circuit, the first synchronizing signal of vision signal is inputted the first filtering clamp circuit, and the second synchronizing signal of vision signal is inputted the second filtering clamp circuit;
The output of the first filtering clamp circuit is connected with the first input end of the first voltage comparator circuit and the input of peak-detector circuit respectively;
The output of the second filtering clamp circuit is connected with the first input end of second voltage comparison circuit;
The output of peak-detector circuit is connected with the second input of the first voltage comparator circuit and the second input of second voltage comparison circuit respectively.
The output of the first voltage comparator circuit and first drives shaping circuit and is connected, drive the first shaping synchronizing signal of shaping circuit output through adjusting by first, the output of second voltage comparison circuit and second drives shaping circuit and is connected, and drives the second shaping synchronizing signal of shaping circuit output through adjusting by second.
The operation principle of synchronizing signal amplitude self adaptation and shaping is as follows:
(1) filtering clamp circuit (comprising the first filtering clamp circuit and the second filtering clamp circuit):
Synchronizing signal is carried out filtering inhibition synchronous interference through alternating-current resistance first and is input to based on mainly synchronizing signal being carried out the voltage bleed off, the stabilization signal level above certain potentials in the clamp circuit of duodiode again.
(2) peak-detector circuit:
Peak-detector circuit is that the voltage amplitude according to input sync signal carries out detection, the applied signal voltage amplitude during less than 3.3V the magnitude of voltage after its detection be the voltage peak of input sync signal, the signal amplitude of input and the magnitude of voltage of detection carry out self adaptation like this; When defeated such as the signal voltage amplitude during more than or equal to 3.3V the magnitude of voltage after its detection be fixed maximum values 3.3V; Guarantee the synchronizing signal voltage amplitude coupling of back receiving terminal circuit and input.
(3) voltage comparator circuit (comprising the first voltage comparator circuit and second voltage comparison circuit):
Line synchronizing signal is sampled to rear end AD the clock of PLL is provided in simulation ARGB signal, so need to select high speed device in signal rising and the lower down-sampled comparator of having relatively high expectations, utilize simultaneously resistance feedback to form and have hysteretic characteristic to reach the stable sampling to the synchronizing signal edge; The synchronizing signal of the self adaptation resistance dividing potential drop mode by input signal amplitude and input is carried out difference and is relatively exported oppositely stable pulse synchronous signal again.
(4) drive shaping circuit (comprising that first drives shaping circuit and the second driving shaping circuit):
Synchronizing signal is output as reverse pulse signal through over-voltage comparator, by using Schmidt's reverser with the signal negate, increases simultaneously the signal driver ability and reaches driving shaping to synchronizing signal.
Physical circuit figure is as shown in Figure 2:
The first filtering clamp circuit comprises the first alternating-current resistance FB1, the first filtering clamp resistance R 2, the second filtering clamp resistance R 1 and the first duodiode clamp circuit D1;
The line synchronizing signal of the input receiving video signals of the first filtering clamp circuit, the input of the first filtering clamp circuit is connected with the first alternating-current resistance FB1, line synchronizing signal is carried out filtering through the first alternating-current resistance FB19 and is suppressed High-frequency Interference, the first alternating-current resistance FB1 is connected with an end of the first filtering clamp resistance R 2, the other end of the first filtering clamp resistance R 2 is connected with the output of the first filtering clamp circuit, the first alternating-current resistance FB1 is connected with an end of the second filtering clamp resistance R 1 with the tie point of the first filtering clamp resistance R 2, the other end of the second filtering clamp resistance R 1 is connected with the first duodiode clamp circuit D1 and ground connection, the first duodiode clamp circuit comprises successively the first filtering clamping diode and the second filtering clamping diode that connects, the first filtering clamping diode be connected the tie point of filtering clamping diode and be connected with the output of the first filtering clamp circuit;
The second filtering clamp circuit comprises the second alternating-current resistance FB2, the 3rd filtering clamp resistance R 12, the 4th filtering clamp resistance R 13 and the second duodiode clamp circuit D4;
The field sync signal of the input receiving video signals of the second filtering clamp circuit, the input of the second filtering clamp circuit is connected with the second alternating-current resistance FB2, the second synchronizing signal is carried out filtering through third high frequency resistance FB2 and is suppressed High-frequency Interference, the second alternating-current resistance FB2 is connected with an end of the 3rd filtering clamp resistance R 12, the other end of the 3rd filtering clamp resistance R 12 is connected with the output of the second filtering clamp circuit, the second alternating-current resistance FB2 is connected with an end of the 4th filtering clamp resistance R 13 with the tie point of the 3rd filtering clamp resistance R 12, the other end of the 4th filtering clamp resistance R 13 is connected with the second duodiode clamp circuit D4 and ground connection, the second duodiode clamp circuit D4 comprises the 3rd filtering clamping diode and the 4th filtering clamping diode that connects successively, and the tie point of the 3rd filtering clamping diode and the 4th filtering clamping diode is connected with the output of the second filtering clamp circuit.
Synchronizing signal is carried out filtering inhibition High-frequency Interference through FB1 and FB2 alternating-current resistance, using string and company's resistance that signal is carried out impedance matching is input to based on mainly synchronizing signal being carried out the voltage bleed off, the stabilization signal level above certain potentials in the duodiode clamp circuit of D5, D4 again.
Peak-detector circuit comprises: crest voltage comparator U1A, peak value triode Q1, the first peak value electric capacity TC1, the first peak value resistance R 4 and the second peak resistance R5;
The input of peak-detector circuit is connected with the first input end (the 2nd pin) of crest voltage comparator U1A, the output of peak-detector circuit (the 1st pin) is connected with second input (the 3rd pin) of crest voltage comparator, 1 pin of crest voltage comparator is connected with the base stage of peak value triode Q1, the power input of crest voltage comparator (the 8th pin) and supply power voltage are that the threshold power of 3.3V is connected, the emitter of peak value triode Q1 is connected with the first peak value resistance R 4, the emitter of peak value triode Q1 and the tie point of the first peak value resistance R 4 and supply power voltage are that the threshold power of 3.3V is connected, the collector electrode of peak value triode Q1 is connected ground connection with the first peak value electric capacity TC1, the first peak value resistance R 4 ground connection of connecting with the second peak resistance R5, the tie point of the first peak value resistance R 4 and the second peak resistance 24, the collector electrode of peak value triode Q1 is connected with the output of peak-detector circuit with the tie point of the first peak value electric capacity TC1.
The peak-detector circuit that the synchronizing signal of input forms through U1A, Q1, TC1, R4 and R5 carries out detection to the synchronizing signal voltage amplitude of input, the voltage peak amplitude that large electric capacity and the U1A control Q1 by TC1 exports to obtain input sync signal; The applied signal voltage amplitude during less than 3.3V the magnitude of voltage after its detection be the voltage peak of input sync signal, the signal amplitude of input and the magnitude of voltage of detection carry out self adaptation like this; When defeated such as the signal voltage amplitude during more than or equal to 3.3V the magnitude of voltage after its detection be fixed maximum values 3.3V; Guarantee the synchronizing signal voltage amplitude coupling of back receiving terminal circuit and input.
The first voltage comparator circuit comprises: the first high speed voltage comparator U2, the first voltage ratio is than resistance R 9 and second voltage comparison resistance R7, the first input end of the first high speed voltage comparator U2 (the 4th pin) is connected with the first input end of the first voltage comparator circuit, the second input of the first voltage comparator U2 (the 3rd pin) is connected with the second input of the first voltage comparator circuit, the output of the first voltage comparator U2 (the 1st pin) is connected than resistance R 9 with output and first voltage ratio of the first voltage comparator circuit respectively, the 1st pin of the first voltage comparator U2 successively with the first voltage ratio than resistance R 9, the 3rd pin of second voltage comparison resistance R7 and the first voltage comparator U2 is connected to form the first hysteresis loop with hysteretic characteristic;
The second voltage comparison circuit comprises: second voltage comparator U1B, tertiary voltage comparison resistance R15 and the 4th voltage ratio are than resistance R 10, the first input end of second voltage comparator U1B (the 6th pin) is connected with the first input end of second voltage comparison circuit, the second input of second voltage comparator U1B (the 5th pin) is connected with the second input of the first voltage comparator circuit, the output of second voltage comparator U1B (the 7th pin) is connected with output and the tertiary voltage comparison resistance R15 of second voltage comparison circuit respectively, the 7th pin of second voltage comparator U1B successively with tertiary voltage comparison resistance R15, the 4th voltage ratio is connected to form the second hysteresis loop with hysteretic characteristic than the 5th pin of resistance R 10 and second voltage comparator.
The HS line synchronizing signal is sampled to rear end AD the clock of PLL is provided in simulation ARGB signal, so need to select the U2 high speed device in signal rising and the lower down-sampled comparator of having relatively high expectations, utilize simultaneously R7 and R9 resistance feedback to form and have hysteretic characteristic to reach the stable sampling to the synchronizing signal edge; Mainly the every frame of signal is sampled in the VS field sync signal and can use the common voltage comparator of U1B and R10 and R15 resistance feedback to form to have hysteretic characteristic to reach the stable sampling to VS field sync signal edge; Carry out difference by the self adaptation of input signal amplitude with the capable field sync signal of R6 and R8 and R30 and R13 electric resistance partial pressure mode and input again and relatively export oppositely stable pulse synchronous signal.
First drives shaping circuit comprises first Schmidt's reverser U3C, the first input that drives shaping circuit is connected with the input (the 5th pin) of first Schmidt's reverser U3C, and the first output that drives shaping circuit is connected with the output (the 6th pin) of first Schmidt's reverser U3C;
Described second drives shaping circuit comprises second Schmidt's reverser U3D, the second input that drives shaping circuit is connected with the input (the 9th pin) of second Schmidt's reverser U3D, and the second output that drives shaping circuit is connected with the output (the 8th pin) of second Schmidt's reverser U3D.
Synchronizing signal is output as reverse pulse signal through over-voltage comparator, by using Schmidt's reverser with the signal negate, increases simultaneously the signal driver ability and reaches driving shaping to synchronizing signal.
Be illustrated in figure 3 as the circuit theory diagrams of second embodiment of the present invention.Be that with the distinctive points of first embodiment peak-detector circuit comprises: crest voltage comparator U1A, peak value diode D5, the first peak value electric capacity TC1, the first peak value resistance R 4 and the second peak resistance R5;
The input of peak-detector circuit is connected with the second input (the 3rd pin) of crest voltage comparator U1A, the output of peak-detector circuit is connected with the first input end (the 2nd pin) of crest voltage comparator U1A, the output of crest voltage comparator U1A (the 1st pin) is connected with the positive pole of peak value diode D5, the power input of crest voltage comparator U1A and supply power voltage are that the threshold power of 3.3V is connected, the negative electrode of peak value diode D5 is connected with the output of crest voltage comparator U1A, one end of the first peak value resistance R 4 and supply power voltage are that the threshold power of 3.3V is connected, the other end peak of the first peak value resistance R 4 is connected ground connection with the first peak value electric capacity TC1, the first peak value resistance R 4 ground connection of connecting with the second peak resistance R5, the tie point of the first peak value resistance R 4 and the second peak resistance R5, the first peak value resistance R 4 is connected with the output of peak-detector circuit with the tie point of the first peak value electric capacity TC1.
The embodiment of the invention is carried out detection to the peak amplitude of synchronizing signal and is carried out amplitude self adaptation than clip level with the simulation ARGB signal that reaches receiving by voltage ratio; At last synchronizing signal is driven shaping, satisfy the sampling processing synchronizing signal that receiving terminal can be effectively correct.
The present invention is more common at filtering clamp circuit and driving shaping circuit, be easy to otherwise realize this function, peak detection in key component synchronizing signal of the present invention also has replacement scheme: can adopt the digital processing mode to detect voltage amplitude and realize peak detection, by logic control or special-purpose AD chip the synchronizing signal of input is carried out analog-to-digital conversion with signal digitalized, signal peak amplitude control output voltage according to quantizing so also can reach the self adaptation to input signal amplitude.
Claims (8)
1. amplitude self adaptation synchronous shaping, it is characterized in that, described circuit comprises that the first filtering clamp circuit, the second filtering clamp circuit, peak-detector circuit, the first voltage comparator circuit, second voltage comparison circuit, first drive shaping circuit and second and drive shaping circuit, the first synchronizing signal of vision signal is inputted the first filtering clamp circuit, and the second synchronizing signal of vision signal is inputted the second filtering clamp circuit;
The output of the first filtering clamp circuit is connected with the first input end of the first voltage comparator circuit and the input of peak-detector circuit respectively;
The output of the second filtering clamp circuit is connected with the first input end of second voltage comparison circuit;
The output of peak-detector circuit is connected with the second input of the first voltage comparator circuit and the second input of second voltage comparison circuit respectively;
The output of the first voltage comparator circuit and first drives shaping circuit and is connected, drive the first shaping synchronizing signal of shaping circuit output through adjusting by first, the output of second voltage comparison circuit and second drives shaping circuit and is connected, and drives the second shaping synchronizing signal of shaping circuit output through adjusting by second;
Described the first filtering clamp circuit is used for the first synchronizing signal of stable input, and synchronizing signal is stablized in output first, and the second filtering clamp circuit is used for stablizing input the second synchronizing signal, and synchronizing signal is stablized in output second;
Described peak-detector circuit output peak value limitation signal, peak-detector circuit is stablized synchronizing signal to first and is carried out detection, if the first voltage amplitude of stablizing synchronizing signal surpasses predefined first threshold, then the voltage amplitude of peak limiting limitation signal is first threshold;
The first voltage comparator circuit stablize synchronizing signal to first of peak value limitation signal and the first filtering clamp circuit output and is carried out difference and relatively export the first oppositely stable pulse synchronous signal, and the second voltage comparison circuit second is stablized synchronizing signal and carried out difference and relatively export the second reverse stable pulse synchronous signal what peak value limitation signal and the second filtering clamp circuit were exported;
The driving force that first drives shaping circuit increases by the first pulse synchronous signal reaches and the first pulse synchronous signal is driven shaping exports the first shaping synchronizing signal, and the driving force that second drives shaping circuit increases by the second pulse synchronous signal reaches and the second pulse synchronous signal is driven shaping exports the second shaping synchronizing signal;
Wherein, described the first synchronizing signal is the line synchronizing signal of vision signal, and described the second synchronizing signal is the field sync signal of vision signal;
Perhaps, described the first synchronizing signal is the field sync signal of vision signal, and described the second synchronizing signal is the line synchronizing signal of vision signal.
2. described synchronous shaping according to claim 1 is characterized in that, described the first filtering clamp circuit comprises the first alternating-current resistance, the first filtering clamp resistance, the second filtering clamp resistance and the first duodiode clamp circuit;
The input of the first filtering clamp circuit is connected with the first alternating-current resistance, the first synchronizing signal is carried out filtering through the first alternating-current resistance and is suppressed High-frequency Interference, the first alternating-current resistance is connected with an end of the first filtering clamp resistance, the other end of the first filtering clamp resistance is connected with the output of the first filtering clamp circuit, the first alternating-current resistance is connected with an end of the second filtering clamp resistance with the tie point of the first filtering clamp resistance, the other end of the second filtering clamp resistance is connected with the first duodiode clamp circuit and ground connection, the first duodiode clamp circuit comprises successively the first filtering clamping diode and the second filtering clamping diode that connects, the first filtering clamping diode be connected the tie point of filtering clamping diode and be connected with the output of the first filtering clamp circuit;
The second filtering clamp circuit comprises the second alternating-current resistance, the 3rd filtering clamp resistance, the 4th filtering clamp resistance and the second duodiode clamp circuit;
The input of the second filtering clamp circuit is connected with the second alternating-current resistance, the second synchronizing signal is carried out filtering through the second alternating-current resistance and is suppressed High-frequency Interference, the second alternating-current resistance is connected with an end of the 3rd filtering clamp resistance, the other end of the 3rd filtering clamp resistance is connected with the output of the second filtering clamp circuit, the second alternating-current resistance is connected with an end of the 4th filtering clamp resistance with the tie point of the 3rd filtering clamp resistance, the other end of the 4th filtering clamp resistance is connected with the second duodiode clamp circuit and ground connection, the second duodiode clamp circuit comprises the 3rd filtering clamping diode and the 4th filtering clamping diode that connects successively, and the tie point of the 3rd filtering clamping diode and the 4th filtering clamping diode is connected with the output of the second filtering clamp circuit.
3. synchronous shaping according to claim 1 is characterized in that, described peak-detector circuit comprises: crest voltage comparator, peak value triode, the first peak value electric capacity, the first peak resistance and the second peak resistance;
The input of peak-detector circuit is connected with the first input end of crest voltage comparator, the output of peak-detector circuit is connected with the second input of crest voltage comparator, the output of crest voltage comparator is connected with the base stage of peak value triode, the power input of crest voltage comparator and supply power voltage are that the threshold power of first threshold is connected, the emitter of peak value triode is connected with the first peak resistance, the tie point of the emitter of peak value triode and the first peak resistance and supply power voltage are that the threshold power of first threshold is connected, the collector electrode of peak value triode is connected ground connection with the first peak value electric capacity, the first peak resistance ground connection of connecting with the second peak resistance, the tie point of the first peak resistance and the second peak resistance, the collector electrode of peak value triode is connected with the output of peak-detector circuit with the tie point of the first peak value electric capacity.
4. synchronous shaping according to claim 1 is characterized in that, described peak-detector circuit comprises: crest voltage comparator, peak value diode, the first peak value electric capacity, the first peak resistance and the second peak resistance;
The input of peak-detector circuit is connected with the second input of crest voltage comparator, the output of peak-detector circuit is connected with the first input end of crest voltage comparator, the output of crest voltage comparator is connected with the positive pole of peak value diode, the power input of crest voltage comparator and supply power voltage are that the threshold power of first threshold is connected, the negative electrode of peak value diode is connected with the output of crest voltage comparator, one end of the first peak resistance and supply power voltage are that the threshold power of first threshold is connected, the other end of the first peak resistance is connected ground connection with the first peak value electric capacity, the first peak resistance ground connection of connecting with the second peak resistance, the tie point of the first peak resistance and the second peak resistance, the first peak resistance is connected with the output of peak-detector circuit with the tie point of the first peak value electric capacity.
5. synchronous shaping according to claim 1, it is characterized in that, described the first voltage comparator circuit comprises: the first voltage comparator, the first voltage comparison resistance and second voltage comparison resistance, the first input end of the first voltage comparator is connected with the first input end of the first voltage comparator circuit, the second input of the first voltage comparator is connected with the second input of the first voltage comparator circuit, the output of the first voltage comparator is connected with output and the first voltage comparison resistance of the first voltage comparator circuit respectively, the output of the first voltage comparator successively with the first voltage comparison resistance, the second input of second voltage comparison resistance and the first voltage comparator is connected to form the first hysteresis loop with hysteretic characteristic;
Described second voltage comparison circuit comprises: the second voltage comparator, tertiary voltage comparison resistance and the 4th voltage comparison resistance, the first input end of second voltage comparator is connected with the first input end of second voltage comparison circuit, the second input of second voltage comparator is connected with the second input of the first voltage comparator circuit, the output of second voltage comparator is connected with output and the tertiary voltage comparison resistance of second voltage comparison circuit respectively, the output of second voltage comparator successively with the tertiary voltage comparison resistance, the second input of the 4th voltage comparison resistance and second voltage comparator is connected to form the second hysteresis loop with hysteretic characteristic.
6. synchronous shaping according to claim 5 is characterized in that, if the first synchronizing signal is the line synchronizing signal of vision signal, the second synchronizing signal is the field sync signal of vision signal, and then described the first voltage comparator is high speed voltage comparator;
If the first synchronizing signal is the field sync signal of vision signal, the second synchronizing signal is the line synchronizing signal of vision signal, and then described second voltage comparator is high speed voltage comparator.
7. synchronous shaping according to claim 1, it is characterized in that, described first drives shaping circuit comprises first Schmidt's reverser, the first input that drives shaping circuit is connected with the input of first Schmidt's reverser, and the first output that drives shaping circuit is connected with the output of first Schmidt's reverser;
Described second drives shaping circuit comprises second Schmidt's reverser, and the second input that drives shaping circuit is connected with the input of second Schmidt's reverser, and the second output that drives shaping circuit is connected with the output of second Schmidt's reverser.
8. synchronous shaping according to claim 1 is characterized in that, described first threshold is 3.3 volts.
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| CN103957648B (en) * | 2014-05-19 | 2016-01-20 | 成都启臣微电子有限公司 | Controllable silicon, simulation, PWM light modulation universal circuit and LED drive chip |
| CN108152561A (en) * | 2018-03-14 | 2018-06-12 | 广东海明晖电子科技有限公司 | Igh-speed wire-rod production line circuit |
| CN109889188B (en) * | 2019-04-17 | 2024-05-24 | 广州市恒众车联网科技股份有限公司 | Triangular wave generating device and system |
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| US7345714B2 (en) * | 2005-01-13 | 2008-03-18 | National Semiconductor Corporation | Video signal clamp |
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