CN102098041A - Reconfigurable logic gating circuit of linear system - Google Patents
Reconfigurable logic gating circuit of linear system Download PDFInfo
- Publication number
- CN102098041A CN102098041A CN 201010574426 CN201010574426A CN102098041A CN 102098041 A CN102098041 A CN 102098041A CN 201010574426 CN201010574426 CN 201010574426 CN 201010574426 A CN201010574426 A CN 201010574426A CN 102098041 A CN102098041 A CN 102098041A
- Authority
- CN
- China
- Prior art keywords
- resistance
- operational amplifier
- power supply
- input
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The invention discloses a dynamic logic gating circuit which can carry out dynamic conversion among a plurality of logic functions. The circuit comprises a first input end, a second input end, a third input end, a computing circuit and an output end, wherein the first input end is used for receiving input signals; the second input end is used for receiving a threshold parameter value and a weighting coefficient for carrying out weighting processing on the input signals; the third input end is used for receiving a control instruction; the computing circuit is respectively connected with the first input end, the second input end and the third input end and used for acquiring a logic computing result of the dynamic logic gating circuit according to the input signals, the weighting coefficient, the threshold parameter value and the control instruction; and the output end is connected with the computing circuit and used for outputting a logic computing result. Based on a linear dynamics synchronization mechanism, the dynamic logic gating circuit disclosed by the invention realizes a technology for carrying out quick conversion among a plurality of logics through distinguishing two input signals and changing the control instruction and the threshold parameter. The technical scheme provided by the invention has higher logic conversion speed as well as rich and varied logic results.
Description
Technical field
The present invention relates to technical field of integrated circuits, especially relate to a kind of reconfigurable dynamic logic gate circuit based on the linear dynamics system synchronization method.
Background technology
An important directions in research aspect the next generation computer chip design makes computing equipment have reconfigurable dynamic logic Research of structure exactly.Existing reconfigurable dynamic logic architecture all is based on traditional programmable gate array (FPGA) technology, the FPGA technology is that the line to the static state on the integrated circuit (IC) chip reconnects and realizes different functions, and its single gate is not reconfigurable.And traditional logic gates generally is to be combined by single switching circuit of selecting, and gate circuit can only pre-set, and can not change dynamically.The binary logic gate circuit that also useful pair of selected on-off circuit of prior art formed has been realized the conversion between " and door " and disjunction gate.
Chaos system can be embedded into pattern abundant in the nonlinear dynamic system by utilization, come the actuating logic computing function, promptly the reconfigurable logic door based on dynamic system uses fixing circuit structure, under the situation that does not change circuit structure, by changing circuit parameter, the dynamic system element is changed between different gates, thereby realized different calculation functions, as realize basic gate.
But the existing dynamic logic gate scheme that realizes based on the chaos method for synchronous, input is symmetrical, make the dynamic diversity of gate be restricted like this, the existing scheme that realizes based on the chaos method for synchronous only can be implemented between three kinds of gates carries out dynamic translation, in the time of can not satisfying practical application well for the multifarious requirement of logical consequence.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of input asymmetric reconfigurable dynamic logic gate circuit, can carry out dynamic translation between more kinds of logic functions.
In order to solve the problems of the technologies described above, the invention provides a kind of reconfigurable dynamic logic gate circuit, comprise first input end, second input, the 3rd input, computing circuit and output, wherein:
Described first input end is used for receiving inputted signal;
Described second input is used to receive the weight coefficient that described input signal is weighted processing, also is used for the threshold level parameter;
Described the 3rd input is used to receive control command;
Described computing circuit links to each other with described first input end, second input and the 3rd input respectively, is used for obtaining the logic operation result of described dynamic logic gate circuit according to described input signal, weight coefficient, control command, threshold parameter;
Described output links to each other with described computing circuit, is used to export described logic operation result.
Preferably, described computing circuit obtains described logic operation result according to following formula:
According to | the magnitude relationship of y-x| and β, the different logical value of described computing circuit output;
Wherein:
I
iBe i input signal, i=1,2;
B
iBe i weight coefficient, i=1,2;
X and y are respectively the state variable of drive system and responding system;
β is a threshold parameter;
K is described control command;
I
OutBe output signal.
Preferably, if | y-x|＜β, then I
Out=1, otherwise, if | y-x| 〉=β, then I
Out=0.
Preferably, change the described control command that described the 3rd input receives, the logic function of the described logic gates of dynamic translation.
Preferably, change the described threshold parameter that described second input receives, the logic function of the described logic gates of dynamic translation.
Preferably, this logic gates further comprises:
Memory links to each other with described second input, is used to store the value of described weight coefficient, threshold parameter.
Preferably, described computing circuit comprises first power supply, second source, the 3rd power supply, the 4th power supply, the 5th power supply, first operational amplifier, second operational amplifier, the 3rd operational amplifier, four-operational amplifier, first resistance, second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 11 resistance, the 12 resistance, the 13 resistance, the 14 resistance, the 15 resistance, the 16 resistance, the 17 resistance, the 18 resistance, the 19 resistance, first electric capacity, second electric capacity, first Schottky diode, second Schottky diode, wherein:
The in-phase input end of described first operational amplifier inserts first input signal through described second resistance;
The in-phase input end of described first operational amplifier inserts second input signal through described the 3rd resistance;
The inverting input of described first operational amplifier is through described first grounding through resistance;
The in-phase input end of described first operational amplifier is also through described the 4th grounding through resistance;
The inverting input of described first operational amplifier is connected with the output of described first operational amplifier behind described the 5th resistance;
The output of described first operational amplifier connects the in-phase input end of described second amplifier through described the 6th resistance, described the 8th resistance, and described the 6th resistance is simultaneously also through described first capacity earth;
The output of described first operational amplifier connects the reverse input end of described the 3rd amplifier through described the 6th resistance, described the 13 resistance;
Described first power supply, described second source, described the 3rd power supply, described the 4th power supply and described the 5th power supply are DC power supply;
Described second source is the reverse bias power supply of described first operational amplifier, described second operational amplifier and described the 3rd operational amplifier;
Described the 3rd power supply is the forward bias power supply of described first operational amplifier, described second operational amplifier, described the 3rd operational amplifier and described four-operational amplifier;
Described the 5th power supply is the reverse bias power supply of described four-operational amplifier;
The minus earth of the negative pole of the negative pole of described first power supply, described the 3rd power supply, described the 4th power supply;
The plus earth of anodal and described the 5th power supply of described second source;
The in-phase input end of described second operational amplifier connects the positive pole of described first power supply through described the 9th resistance;
The in-phase input end of described second operational amplifier is also through described the tenth grounding through resistance;
The inverting input of described second operational amplifier is through described the 7th grounding through resistance;
The inverting input of described second operational amplifier is connected with the output of described second operational amplifier behind described the 11 resistance;
The output of described second operational amplifier connects the in-phase input end of described the 3rd operational amplifier through described the 12 resistance, described the 14 resistance,
The in-phase input end of described the 3rd operational amplifier connects described the 14 resistance, through described second capacity earth;
The in-phase input end of described the 3rd operational amplifier is also through described the 15 grounding through resistance;
The inverting input of described the 3rd operational amplifier also connects the inverting input of described four-operational amplifier through described the 16 resistance, described the 17 resistance;
The output of described the 3rd operational amplifier connects the inverting input of described four-operational amplifier also through described the 17 resistance;
The in-phase input end of described four-operational amplifier connects the positive pole of described the 4th power supply through described the 18 resistance;
The output of described four-operational amplifier is through described the 19 resistance, connects ground connection behind the negative pole of described first Schottky diode;
The output of described four-operational amplifier also connects the anodal back ground connection of described second Schottky diode through described the 19 resistance;
The output of described four-operational amplifier is the output of described logic gates behind described the 19 resistance, export an output signal.
Preferably, the capacity of described first electric capacity equals the capacity of described second electric capacity;
Described the 4th power source voltage equals described first power source voltage;
First power supply and the 4th power source voltage value equal described threshold parameter;
Described the 3rd power source voltage, described the 5th power source voltage equal the voltage of described second source;
The voltage of described second source is described control command;
The ratio of the resistance of the resistance of described the 4th resistance and described second resistance equals first weight coefficient, and the ratio of the resistance of the resistance of described the 4th resistance and described the 3rd resistance equals second weight coefficient;
The resistance of the resistance of the resistance of the resistance of the resistance of the resistance of the resistance of described the 4th resistance, the 5th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the resistance of the 11 resistance, the 13 resistance, the resistance of the 14 resistance, the 15 resistance, the resistance of the 16 resistance, the resistance of the 17 resistance, the resistance of the 18 resistance equal the resistance of described second resistance;
The resistance of described the 12 resistance equals the resistance of described first resistance;
The resistance of described the 7th resistance equals the resistance of described the 3rd resistance;
The resistance of described second resistance equals three times of resistance of described first resistance;
The resistance of described second resistance also equals the twice of the resistance of described the 3rd resistance;
Described first weight coefficient is used for described first input signal is weighted, and described second weight coefficient is used for described second input signal is weighted.
The present invention is based on the linear dynamics system synchronization method and realized the technology of the dynamic logic gate circuit changed fast between multiple logic, the technical solution of the present invention logical consequence is rich and varied.
Description of drawings
Fig. 1 is the immutable gate structural circuit of the logic function schematic diagram of the single output of a kind of two inputs in the prior art;
Fig. 2 is the technical solution of the present invention principle schematic;
Fig. 3 is a reconfigurable gate model schematic diagram in the technical solution of the present invention;
Fig. 4 is the structural representation of dynamic logic gate circuit embodiment of the present invention;
Fig. 5 is the curve chart that synchronous error changes with control command;
Fig. 6 is an application example of technical solution of the present invention;
Fig. 7 is input signal I in the application example shown in Figure 6
1+ 2I
2The waveform schematic diagram;
Fig. 8 is the waveform schematic diagram of state variable x and y in the application example shown in Figure 6;
Fig. 9 is the waveform schematic diagram of synchronous error y-x in the application example shown in Figure 6.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 1 is the unalterable gate structural circuit of the logic function schematic diagram of a kind of two inputs, one output in the prior art.As shown in Figure 1, after first input (input 1) and second input (input 2) are input to this gate (Cell 1), produce an output (out 1), but the logic function of this gate can not change.
Fig. 2 is a reconfigurable dynamic logic door principle schematic of the present invention.As shown in Figure 2, first input (input 1) and second input (input 2) are connected to this gate (Cell 2), and this gate produces an output (out 2) under the effect of control signal (control).
Compare the immutable gate structure of logic function shown in Figure 1, one of key of technical solution of the present invention is to utilize this control signal of adjusting, can under the situation that does not change any available circuit structure, make the logic function of described gate take place dynamically to change and realize switching in real time.
Gate for having an output of two inputs can produce 16 kinds of basic Boolean algebra logic functions shown in table 1 (a) and table 1 (b).
Table 1 (a) basic logic NOR, NAND, XOR, OR, AND, 0,1 truth table
Table 1 (b) logic XNOR, X
1, X
2, X
3, X
4, X
5, X
6, X
7, X
8The truth table of door
Core concept of the present invention is, based on linear dynamics system synchronization mechanism, by distinguishing two input signals, and changes control command and threshold parameter, makes gate can carry out dynamic translation between multiple logic function.Compare with chaos system, linear system is also insensitive for the minor variations of system parameters and initial condition, linear system is more suitable for being used for constructing the dynamic logic gate of robust, and when considering computation processor in the cost of aspects such as element, energy consumption and change-over time, the cost of the computing element that constitutes based on linear system is much smaller than the cost of chaos computing element.According to the linear system synchronous error characteristics that rule changes along with parameter change, technical solution of the present invention utilizes linear dynamics system synchronization mechanism to construct dynamic gate, dynamic logic gate based on method for synchronous, a potential advantage can be carried out Long-distance Control exactly, the operator can utilize the flexible transformation that realizes gate and array thereof synchronously easily at far-end by changing control signal.Compare with existing reconfigurable dynamic logic door scheme based on Time Chaotic Dynamical Systems, the key of technical solution of the present invention is to use linear system, by distinguishing two input signals, and change control command and threshold parameter, make technical solution of the present invention can realize more gate.Can imagine, utilize technical scheme of the present invention, can construct and realize than prior art more flexibly, simple, robust, reconfigurable general purpose computing equipment that cost is lower.
Consider following gate model:
Wherein:
X is the state variable of drive system;
Y is the state variable of responding system;
I
1It is first input signal;
I
2It is second input signal;
K is the control command of gate controller;
B
1It is first weight coefficient;
B
2It is second weight coefficient;
β is a threshold parameter, wherein B
1And B
2Be respectively applied for the first input signal I
1With the second input signal I
2Be weighted, they and β are positive constant;
I
OutIt is output signal (also claiming logic operation result);
Fig. 3 is a reconfigurable gate model schematic diagram in the technical solution of the present invention, as shown in Figure 3, and the first input I
1With the second input I
2Handle through the overdrive system module, promptly
, obtaining output signal x, signal x drives the responding system module and handles, responding system is under the control of control signal k, obtain output signal y, after the state variable x of drive system asks the differential mode piece to be weighted processing with the state variable y process weighting of responding system then, obtain output signal I
Out, wherein the processing unit of differential mode piece is asked in weighting, carries out following deterministic process, if promptly | and y-x|＜β, then I
Out=1, else if | y-x| 〉=β, then I
Out=0.
Fig. 4 is the structural representation of dynamic logic gate circuit embodiment of the present invention.Based on aforementioned content, first input end 110, second input 120, the 3rd input 130, computing circuit 140 and the output 150 of mainly comprising embodiment illustrated in fig. 4, wherein:
First input end 110 is used to receive the first input signal I
1With the second input signal I
2
Second input 120 is used to receive the weight coefficient B that described input signal is weighted processing
1And B
2, also be used for the threshold level parameter beta;
The 3rd input 130 is used to receive control command k;
Computing circuit 140 links to each other with first input end 110, second input 120 and the 3rd input 130 respectively, according to the first input signal I
1, the second input signal I
2, the first weight coefficient B
1With the second weight coefficient B
2, threshold parameter β and control command k carry out logical operation, obtains logic operation result I
Out
And output 150, link to each other with this computing circuit 140, be used to export this logic operation result I
Out
Wherein, above-mentioned computing circuit 140 employing formulas (1), that is:
Fig. 5 has provided the curve chart that synchronous error e=|y-x| changes with control command k.Following how illustrating according to Fig. 5 realized dynamic logic gate based on above-mentioned gate model.For example: threshold parameter β=1, the first weight coefficient B is set
1=1, the second weight coefficient B
2=2, when k ∈ (4,5), select input (0,0) respectively, (0,1), (1,0), (1,1), obtaining output signal is 0,0,0,1, has so just obtained an AND door.
The value of control command k can change.When the value that changes control command k, by above definition as can be known, this gate will be become other gate by the AND door, and concrete derivation please refer to aforementioned derivation carries out, and no longer provides detailed process herein.Similarly, can obtain:
When k ∈ (∞ ,-2), (5 ,+∞) time, can obtain 0;
When k ∈ (2,1), can obtain the NOR door;
When k ∈ (1,0), can obtain X
7Door;
When k ∈ (0,1), can obtain the NAND door;
When k ∈ (1,2), can obtain 1;
When k ∈ (2,3), can obtain the OR door;
When k ∈ (3,4), can obtain X
8Door;
When k ∈ (4,5), can obtain the AND door.
Especially, if input signal is exchanged, so just can realize more eurypalynous gate.
The comparatively basic application circuit of realizing under the aforementioned core concept of the present invention that is based on embodiment illustrated in fig. 6 is with understood in detail realization principle of the present invention and process.
Embodiment shown in Figure 4, threshold parameter wherein can real-time change.Consider concrete applied environment, at specific application, threshold parameter generally can real-time change, and variable quantity only is control command k in the calculating process.Therefore can realize application-specific by preserving the mode of default threshold parameter in the technical solution of the present invention at concrete environment.Certainly, in running, this programme also can be adjusted threshold parameter where necessary in real time.
The dynamic logic gate circuit that can change in real time that technical solution of the present invention realizes, can be used as arithmetic processing unit or mnemon or the like electronic devices and components uses, and can realize cascade effect usefulness easily, can be applied to the aspects such as computer of hardware, the computer search engine of computer chip, the graph image accelerator card of network router, various special purposes, the reconfigurable computer video card that is used for multimedia or recreation, desktop computer, reconfigurable radio circuit, reconfigurable processor, lower powered mobile phone, selfreparing widely.Especially, technical solution of the present invention can also be used in the restructural electronic circuit in the telecommunication system.
Fig. 6 is an application example of technical solution of the present invention.In conjunction with embodiment illustrated in fig. 4, application example shown in Figure 6 is output as example with two inputs one technical solution of the present invention is described.As shown in Figure 6, this application example mainly comprises the first power supply E1, second source E2, the 3rd power supply E3, the 4th power supply E4, the 5th power supply E5, the first operational amplifier O1, the second operational amplifier O2, the 3rd operational amplifier O3, four-operational amplifier O4, first resistance R 11, second resistance R 12, the 3rd resistance R 13, the 4th resistance R 14, the 5th resistance R 15, the 6th resistance R 16, the 7th resistance R 21, the 8th resistance R 22, the 9th resistance R 23, the tenth resistance R 24, the 11 resistance R 25, the 12 resistance R 26, the 13 resistance R 31, the 14 resistance R 32, the 15 resistance R 33, the 16 resistance R 34, the 17 resistance R 41, the 18 resistance R 42, the 19 resistance R 43, first capacitor C 1, second capacitor C 2, the first Schottky diode D1, the second Schottky diode D2, wherein:
The in-phase input end of the described first operational amplifier O1 inserts the first input signal I through described second resistance R 12
1
The in-phase input end of the described first operational amplifier O1 inserts the second input signal I through described the 3rd resistance R 13
2
The inverting input of the described first operational amplifier O1 is through described first resistance R, 11 ground connection;
The in-phase input end of the described first operational amplifier O1 is also through described the 4th resistance R 14 ground connection;
The inverting input of the described first operational amplifier O1 is connected with the output of the described first operational amplifier O1 after described the 5th resistance R 15;
The output of the described first operational amplifier O1 is through the in-phase input end of described the 6th resistance R 16, the described second operational amplifier O2 of described the 8th resistance R 22 connections, and described the 6th resistance R 16 is simultaneously also through described first capacitor C, 1 ground connection;
The output of the described first operational amplifier O1 connects the reverse input end of described the 3rd operational amplifier O3 through described the 6th resistance R 16, described the 13 resistance R 31;
The described first power supply E1, described second source E2, described the 3rd power supply E3, described the 4th power supply E4 and described the 5th power supply E5 are DC power supply;
Described second source E2 is the reverse bias power supply of the described first operational amplifier O1, the described second operational amplifier O2 and described the 3rd operational amplifier O3;
Described the 3rd power supply E3 is the forward bias power supply of the described first operational amplifier O1, the described second operational amplifier O2, described the 3rd operational amplifier O3 and described four-operational amplifier O4;
Described the 5th power supply E5 is the reverse bias power supply of described four-operational amplifier O4;
The minus earth of the negative pole of the negative pole of the described first power supply E1, described the 3rd power supply E3, described the 4th power supply E4;
The plus earth of anodal and described the 5th power supply E5 of described second source E2;
The in-phase input end of the described second operational amplifier O2 connects the positive pole of the described first power supply E1 through described the 9th resistance R 23;
The in-phase input end of the described second operational amplifier O2 is also through described the tenth resistance R 24 ground connection;
The inverting input of the described second operational amplifier O2 is through described the 7th resistance R 21 ground connection;
The inverting input of the described second operational amplifier O2 is connected with the output of the described second operational amplifier O2 after described the 11 resistance R 25;
The output of the described second operational amplifier O2 connects the in-phase input end of described the 3rd operational amplifier O3 through described the 12 resistance R 26, described the 14 resistance R 32,
The in-phase input end of described the 3rd operational amplifier O3 connects described the 14 resistance R 32, through described second capacitor C, 2 ground connection;
The in-phase input end of described the 3rd operational amplifier O3 is also through described the 15 resistance R 33 ground connection;
The inverting input of described the 3rd operational amplifier O3 also connects the inverting input of described four-operational amplifier O4 through described the 16 resistance R 34, described the 17 resistance R 41;
The output of described the 3rd operational amplifier O3 connects the inverting input of described four-operational amplifier O4 also through described the 17 resistance R 41;
The in-phase input end of described four-operational amplifier O4 links the positive pole of described the 4th power supply E4 through described the 18 resistance R 42;
The output of described four-operational amplifier O4 is through described the 19 resistance R 43, connects ground connection behind the negative pole of the described first Schottky diode D1;
The output of described four-operational amplifier O4 also connects the anodal back ground connection of the described second Schottky diode D4 through described the 19 resistance R 43;
The output of described four-operational amplifier O4 is the output I of described logic gates after described the 19 resistance R 43
Out, export an output signal.
In the application example shown in Figure 6, the ratio of the resistance of the resistance of the 4th resistance R 14 and described second resistance R 12 equals the first weight coefficient B
1, the ratio of the resistance of the resistance of described the 4th resistance R 14 and described the 3rd resistance R 13 equals the second weight coefficient B
2, also be B
1=R
14/ R
12, B
2=R
14/ R
13, the magnitude of voltage of described first power supply E1 and the 4th power supply E4 equals described threshold parameter β; The resistance of the resistance of the resistance of the resistance of the resistance of the resistance of the resistance of described the 4th resistance R 14, the 5th resistance R 15, the 8th resistance R 22, described the 9th resistance R 23, the tenth resistance R 24, the resistance of the 11 resistance R 25, the 13 resistance R 31, the resistance of the 14 resistance R 32, the 15 resistance R 33, the resistance of the 16 resistance R 34, the resistance of the 17 resistance R 41, the resistance of the 18 resistance R 42 equal the resistance of described second resistance R 12; The resistance of described the 12 resistance R 26 equals the resistance of described first resistance R 11; The resistance of described the 7th resistance R 21 equals the resistance of described the 3rd resistance R 13; The resistance of described second resistance R 12 equals three times of resistance of described first resistance R 11; The resistance of described second resistance R 12 also equals the twice of the resistance of described the 3rd resistance R 13; The capacity of described first capacitor C 1 equals the capacity of described second capacitor C 2; The voltage of described the 4th power supply E4 equals the voltage of the described first power supply E1; The voltage of the voltage of described the 3rd power supply E3, described the 5th power supply E5 equals the voltage of described second source E2.
In the application example shown in Figure 6, control command is the magnitude of voltage of second source E2.
Below illustrate application example as shown in Figure 6 of the present invention and realize the principle of dynamic logic gate.During with the Multisim software emulation, reach stationary value for making the electric capacity full charge in the RC circuit, thereby conform to the value that is drawn by equation, take applied signal voltage more greatly, frequency input signal hangs down a little ways, with input signal I
1Be made as square wave, I
2Be made as with input signal I
1The square wave of different frequency, the I in the first order
1+ 2I
2Waveform be stepped, as shown in Figure 7; The first order realizes I with in-phase adder
1+ 2I
2, and connecting RC circuit realization differentiation operator (wherein RC=1), the first order realizes one of equation in the dynamic logic gate model of the present invention (1)
X+k is realized with in-phase adder in the second level, and connects RC circuit realization differentiation operator (wherein RC=1/2), and one of equation in the dynamic logic gate model of the present invention (1) is realized in the second level
The x of the first order and the waveform of partial y as shown in Figure 8, the x of the first order and the waveform of partial y obtain after the stationary value for each stage electric capacity all is charged to; The third level is realized y-x with the homophase subtracter, obtains synchronous error, as shown in Figure 9; The fourth stage determines output voltage with the comparison of voltage comparator realization synchronous error and threshold value with voltage stabilizing didoe, that is, if synchronous error, is exported negative voltage stabilizing value greater than threshold value, otherwise, if synchronous error, is exported positive voltage stabilizing value less than threshold value.
Change the value of control command k, by above circuit analysis process as can be known, this gate will be become other gate by the AND door, and concrete derivation please refer to aforementioned reasoning process carries out, and no longer provides detailed process herein.
Application example shown in Figure 6 be with " if | y-x|＜β, then I
Out=1, else if | y-x| 〉=β, then I
Out=0 " is judgment condition.If only regulate k, application example shown in Figure 5 can be realized multiple different logic state, if can regulate k simultaneously, β can be implemented in the function of carrying out dynamic translation between more kinds of logic states with technical solution of the present invention for two inputs, one output logic gate.
The dynamic logic gate that technical solution of the present invention provides, be different from the CPU technology that has the fixed logic door in the existing computing equipment fully, the Computer Architecture that realizes of principle in view of the above, to have more complete mobility in theory, function is also more powerful, can overcome the performance constraint of static lead connection hardware in the prior art.The FPGA technology realizes logical transition between the arithmetic processing unit connection, be much more slowly than the logical transition of the control command that realizes based on dynamic logic gate.
Need to prove; the dynamic logic gate that the present invention can realize not only comprises application example shown in Figure 6; and any replacement that comprises the technical solution of the present invention integrated circuit or done on this basis etc., all should belong within the protection range of technical solution of the present invention.
Claims (9)
1. a dynamic logic gate circuit is characterized in that, comprises first input end, second input, the 3rd input, computing circuit and output, wherein:
Described first input end is used for receiving inputted signal;
Described second input is used to receive the weight coefficient that described input signal is weighted processing, also is used for the threshold level parameter;
Described the 3rd input is used to receive control command;
Described computing circuit links to each other with described first input end, second input and the 3rd input respectively, is used for obtaining the logic operation result of described dynamic logic gate circuit according to described input signal, weight coefficient, control command, threshold parameter;
Described output links to each other with described computing circuit, is used to export described logic operation result.
2. logic gates as claimed in claim 1 is characterized in that, described computing circuit obtains described logic operation result according to following formula:
According to | the magnitude relationship of y-x| and β, the different logical value of described computing circuit output;
Wherein:
I
iBe i input signal, i=1,2;
B
iBe i weight coefficient, i=1,2;
X and y are respectively the state variable of drive system and responding system;
β is a threshold parameter;
K is described control command;
I
OutBe output signal.
3. logic gates as claimed in claim 2 is characterized in that:
If | y-x|＜β, then I
Out=1, otherwise, if | y-x| 〉=β, then I
Out=0.
4. logic gates as claimed in claim 1 is characterized in that:
Change the described control command that described the 3rd input receives, the logic function of the described logic gates of dynamic translation.
5. logic gates as claimed in claim 1 is characterized in that:
Change the described threshold parameter value that described second input receives, the logic function of the described logic gates of dynamic translation.
6. logic gates as claimed in claim 1 is characterized in that:
Two input signals are exchanged, can obtain more logic function.
7. as each described logic gates in the claim 1 to 6, it is characterized in that this logic gates further comprises:
Memory links to each other with described second input, is used to store described weight coefficient and threshold parameter value.
8. logic gates as claimed in claim 1 is characterized in that,
Described computing circuit comprises first power supply, second source, the 3rd power supply, the 4th power supply, the 5th power supply, first operational amplifier, second operational amplifier, the 3rd operational amplifier, four-operational amplifier, first resistance, second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 11 resistance, the 12 resistance, the 13 resistance, the 14 resistance, the 15 resistance, the 16 resistance, the 17 resistance, the 18 resistance, the 19 resistance, first electric capacity, second electric capacity, first Schottky diode, second Schottky diode, wherein:
The in-phase input end of described first operational amplifier inserts first input signal through described second resistance;
The in-phase input end of described first operational amplifier inserts second input signal through described the 3rd resistance;
The inverting input of described first operational amplifier is through described first grounding through resistance;
The in-phase input end of described first operational amplifier is also through described the 4th grounding through resistance;
The inverting input of described first operational amplifier is connected with the output of described first operational amplifier behind described the 5th resistance;
The output of described first operational amplifier connects the in-phase input end of described second amplifier through described the 6th resistance, described the 8th resistance, and described the 6th resistance is simultaneously also through described first capacity earth;
The output of described first operational amplifier connects the reverse input end of described the 3rd amplifier through described the 6th resistance, described the 13 resistance;
Described first power supply, described second source, described the 3rd power supply, described the 4th power supply and described the 5th power supply are DC power supply;
Described second source is the reverse bias power supply of described first operational amplifier, described second operational amplifier and described the 3rd operational amplifier;
Described the 3rd power supply is the forward bias power supply of described first operational amplifier, described second operational amplifier, described the 3rd operational amplifier and described four-operational amplifier;
Described the 5th power supply is the reverse bias power supply of described four-operational amplifier;
The minus earth of the negative pole of the negative pole of described first power supply, described the 3rd power supply, described the 4th power supply;
The plus earth of anodal and described the 5th power supply of described second source;
The in-phase input end of described second operational amplifier connects the positive pole of described first power supply through described the 9th resistance;
The in-phase input end of described second operational amplifier is also through described the tenth grounding through resistance;
The inverting input of described second operational amplifier is through described the 7th grounding through resistance;
The inverting input of described second operational amplifier is connected with the output of described second operational amplifier behind described the 11 resistance;
The output of described second operational amplifier connects the in-phase input end of described the 3rd operational amplifier through described the 12 resistance, described the 14 resistance,
The in-phase input end of described the 3rd operational amplifier connects described the 14 resistance, through described second capacity earth;
The in-phase input end of described the 3rd operational amplifier is also through described the 15 grounding through resistance;
The inverting input of described the 3rd operational amplifier also connects the inverting input of described four-operational amplifier through described the 16 resistance, described the 17 resistance;
The output of described the 3rd operational amplifier connects the inverting input of described four-operational amplifier also through described the 17 resistance;
The in-phase input end of described four-operational amplifier connects the positive pole of described the 4th power supply through described the 18 resistance;
The output of described four-operational amplifier is through described the 19 resistance, connects ground connection behind the negative pole of described first Schottky diode;
The output of described four-operational amplifier also connects the anodal back ground connection of described second Schottky diode through described the 19 resistance;
The output of described four-operational amplifier is the output of described logic gates behind described the 19 resistance, export an output signal.
9. logic gates as claimed in claim 8 is characterized in that:
The capacity of described first electric capacity equals the capacity of described second electric capacity;
Described the 4th power source voltage equals described first power source voltage;
First power supply and the 4th power source voltage value equal described threshold parameter;
Described the 3rd power source voltage, described the 5th power source voltage equal the voltage of described second source;
The voltage of described second source is described control command;
The ratio of the resistance of the resistance of described the 4th resistance and described second resistance equals first weight coefficient, and the ratio of the resistance of the resistance of described the 4th resistance and described the 3rd resistance equals second weight coefficient;
The resistance of the resistance of the resistance of the resistance of the resistance of the resistance of the resistance of described the 4th resistance, the 5th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the resistance of the 11 resistance, the 13 resistance, the resistance of the 14 resistance, the 15 resistance, the resistance of the 16 resistance, the resistance of the 17 resistance, the resistance of the 18 resistance equal the resistance of described second resistance;
The resistance of described the 12 resistance equals the resistance of described first resistance;
The resistance of described the 7th resistance equals the resistance of described the 3rd resistance;
The resistance of described second resistance equals three times of resistance of described first resistance;
The resistance of described second resistance also equals the twice of the resistance of described the 3rd resistance;
Described first weight coefficient is used for described first input signal is weighted, and described second weight coefficient is used for described second input signal is weighted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010574426 CN102098041A (en) | 2010-12-06 | 2010-12-06 | Reconfigurable logic gating circuit of linear system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010574426 CN102098041A (en) | 2010-12-06 | 2010-12-06 | Reconfigurable logic gating circuit of linear system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102098041A true CN102098041A (en) | 2011-06-15 |
Family
ID=44130933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010574426 Pending CN102098041A (en) | 2010-12-06 | 2010-12-06 | Reconfigurable logic gating circuit of linear system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102098041A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5831451A (en) * | 1996-07-19 | 1998-11-03 | Texas Instruments Incorporated | Dynamic logic circuits using transistors having differing threshold voltages |
| US20020075038A1 (en) * | 2000-12-19 | 2002-06-20 | Intel Corporation | Active leakage control technique for high performance dynamic circuits |
| CN101183866A (en) * | 2006-11-16 | 2008-05-21 | 国际商业机器公司 | Hybrid keeper circuit for dynamic logic |
| CN101783670A (en) * | 2010-01-12 | 2010-07-21 | 北京邮电大学 | Reconfigurable dynamic logic gate circuit |
-
2010
- 2010-12-06 CN CN 201010574426 patent/CN102098041A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5831451A (en) * | 1996-07-19 | 1998-11-03 | Texas Instruments Incorporated | Dynamic logic circuits using transistors having differing threshold voltages |
| US20020075038A1 (en) * | 2000-12-19 | 2002-06-20 | Intel Corporation | Active leakage control technique for high performance dynamic circuits |
| CN101183866A (en) * | 2006-11-16 | 2008-05-21 | 国际商业机器公司 | Hybrid keeper circuit for dynamic logic |
| CN101783670A (en) * | 2010-01-12 | 2010-07-21 | 北京邮电大学 | Reconfigurable dynamic logic gate circuit |
Non-Patent Citations (1)
| Title |
|---|
| 《中国博士学位论文全文数据库信息科技辑》 20101115 彭海朋 可重构的动态逻辑计算研究 正文第29～48页 2-3 , 第11期 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Gu et al. | Ultra low voltage, low power 4-2 compressor for high speed multiplications | |
| CN105913118A (en) | Artificial neural network hardware implementation device based on probability calculation | |
| Sinha et al. | Design of fault tolerant reversible multiplier | |
| Kamaraj et al. | Design and implementation of arithmetic and logic unit (ALU) using novel reversible gates in quantum cellular automata | |
| CN113037294A (en) | Multi-quantum bit control device and method based on superconducting electronics | |
| CN101783670A (en) | Reconfigurable dynamic logic gate circuit | |
| Singh et al. | A Unique design of hybrid full adder for the application of low power VLSI circuits | |
| Pooja et al. | Design of compact vedic multiplier for high performance circuits | |
| Shabeena et al. | Design and verification of reversible logic gates using quantum dot cellular automata | |
| Shrivas et al. | Design and performance analysis of 1 bit full adder using GDI technique in nanometer era | |
| Muthu et al. | Design of CMOS 8-Bit Parallel Adder Energy Efficient Structure using SRCPL Logic Style | |
| Jiang et al. | A new full adder design for tree structured arithmetic circuits | |
| CN102098041A (en) | Reconfigurable logic gating circuit of linear system | |
| Patel et al. | Design of area optimised, energy efficient quaternary circuits using CNTFETs | |
| CN101951257B (en) | Dynamic logical gate circuit | |
| Moradi et al. | An applicable high-efficient CNTFET-based full adder cell for practical environments | |
| Reddy et al. | 16-Bit GDI multiplier design for low power applications | |
| CN103219991A (en) | Dynamic reconfigurable logic gate realization method based on cellular neural network (CNN) and realization circuit thereof | |
| Li et al. | An area-efficient ternary full adder using hybrid SET-MOS technology | |
| CN102571076B (en) | Threshold logic-based 7-3 counter with SET (single-electron transistors)/MOS (metal-oxide-semiconductor) mixed structure | |
| Nehru et al. | A shannon based low power adder cell for neural network training | |
| Foroutan et al. | A Novel Current Mode Approximate Multiplier Scheme Based on 4: 2 and 5: 2 Compressors with Low Power Consumption and High Speed in CNTFET Technology | |
| Alluri et al. | Optimization of multiplexer architecture in VLSI circuits | |
| CN110728366A (en) | Artificial neural network based on up-down counter | |
| Upadhyay et al. | Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20110615 |