CN102097939A

CN102097939A - Current sampling circuit

Info

Publication number: CN102097939A
Application number: CN2011100520360A
Authority: CN
Inventors: 方健; 王泽华; 吴琼乐; 陈吕赟; 管超; 柏文斌; 杨毓俊; 黎俐
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2011-03-04
Filing date: 2011-03-04
Publication date: 2011-06-15
Anticipated expiration: 2031-03-04
Also published as: CN102097939B

Abstract

The invention discloses a current sampling circuit, which comprises a first N-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor and a first resistor. The current sampling circuit is characterized by further comprising a first single-end output operational amplifier, a second single-end output operational amplifier, a third single-end output operational amplifier, a first dual-end output operational amplifier, a second dual-end operational amplifier, a first multiplier and a second multiplier. The current sampling circuit adopts the five operational amplifiers and the two multipliers, and performs negative feedback by utilizing the third NMOS transistor to realize voltage ratios between the drains and sources of the first and second NMOS transistors and make a breakthrough in the limitation that the three-terminal levels of a power tube and a sampling tube are required to be completely identical in a sampling technology, and compared with a conventional current sampling structure, has a more flexible structure and simultaneously improves the current sampling accuracy.

Description

A kind of current sampling circuit

Technical field

The invention belongs to the chip design art field, relate in particular to a kind of current sampling circuit design.

Background technology

Switching Power Supply is to utilize modern power electronics technology, keeps a kind of power supply of output voltage stabilization by the time ratio of control switch pipe break-make.How switching power source chip is carried out simply, samples accurately and rapidly, be related to the quality of whole switching power source chip performance.At present, current sample method commonly used has resistance sampling, magnetic sampling, MOSFET sampling etc. in the Switching Power Supply.

Introducing current sampling circuit preceding, earlier NMOS pipe drain current is being described: the NMOS pipe drain current that is operated in linear zone is

μ _nBe the mobility of electronics, C _OxBe the gate oxide electric capacity of unit are, W is the width of grid, and L is the length of grid, V _GSBe the voltage between the two poles of the earth, grid source, V _THBe the threshold voltage of NMOS pipe, V _DSBe the voltage between drain-source the two poles of the earth, if, being operated in dark linear zone, its drain current expression formula is

Current sampling circuit, the general NMOS pipe that is operated in dark linear zone of using carries out current sample.

The following two kinds of current sampling circuits of main employing in the existing Switching Power Supply:

First kind of current sampling circuit in this circuit, utilizes power tube MN1 and sampling pipe MN2 to constitute current mirror, if the breadth length ratio of the grid of power tube MN1 is (W/L) as shown in Figure 1 ₁, the breadth length ratio of the grid of sampling pipe MN2 is (W/L) ₂, in ideal conditions, the source electrode of MN1 pipe, grid, drain potential equate with source electrode, grid, the drain potential of MN2 respectively, the electric current I of sampling pipe _SenseElectric current I with power tube _LdmosRatio be constant,

By adjusting the breadth length ratio of power tube MN1 and sampling pipe MN2, can obtain needed current sample ratio.But sort circuit is when practical application, the source potential of MN1 pipe and the source potential of MN2 might not equate, the result causes the voltage between drain-source the two poles of the earth of MN1 pipe and MN2 also unequal, and then make that the ratio of electric current of the electric current of sampling pipe and power tube is not to be constant, therefore sampling precision is not high, has limited its application.

Second kind of current sampling circuit as shown in Figure 2, operational amplifier A 0 is sampled in the source potential of sampling pipe MN4 and power tube MN3 respectively and is made comparisons, the comparative result feedback is input to the grid of NMOS pipe MN5, change the source potential of sampling pipe MN4 by the drain-source resistance that changes NMOS pipe MN5, with the source potential clamper of power tube MN3 pipe and sampling pipe MN4 to equal.Like this, the grid leak source electric potential of power tube MN3 pipe and sampling pipe MN2 pipe equates that all the sample rate current precision is higher.But the voltage V between drain-source the two poles of the earth of sort circuit structure strict demand power tube MN3 _DS3And the voltage V between sampling pipe MN4 drain-source the two poles of the earth _DS4Equate, i.e. V _DS3=V _DS4, so just cause this current sampling circuit that certain limitation is arranged in concrete circuit application.

Summary of the invention

The objective of the invention is to have proposed a kind of current sampling circuit in order to solve the problem that existing current sampling circuit exists.

To achieve these goals, technical scheme of the present invention is: a kind of current sampling circuit comprises NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, first resistance, it is characterized in that, also comprise the first single-ended output operational amplifier, the second single-ended output operational amplifier, the 3rd single-ended output operational amplifier, the first both-end output operational amplifier, the second both-end output operational amplifier, first multiplier, second multiplier; Wherein, the grid of the one NMOS pipe is connected respectively to the positive input terminal of the first single-ended output operational amplifier, the positive input terminal of the second single-ended output operational amplifier and the grid of the 2nd NMOS pipe, the source electrode of the one NMOS pipe is connected respectively to the negative input end of the first single-ended output operational amplifier, second input of first multiplier and an end of first resistance, the other end ground connection of first resistance, the drain electrode of a NMOS pipe link to each other with the drain electrode of the 2nd NMOS pipe, the first input end of first multiplier and the first input end of second multiplier respectively; The source electrode of the 2nd NMOS pipe connects second input of the second single-ended output operational amplifier negative input end, second multiplier and the drain electrode of the 3rd NMOS pipe respectively, the positive input terminal of the operational amplifier of output termination first both-end output of the first single-ended output operational amplifier, the negative input end of the operational amplifier of first both-end output connects outside reference voltage source, the big or small a of outside reference voltage source ₁* V _TH, wherein, a ₁It is the gain amplifier of the first single-ended output operational amplifier, two outputs of the operational amplifier of first both-end output connect first multiplier the 3rd, four-input terminal respectively, the positive input terminal of the operational amplifier of output termination second both-end output of the second single-ended output operational amplifier, the negative input end of the operational amplifier of second both-end output connects outside reference voltage source, the big or small a of outside reference voltage source ₂* V _TH, wherein, a ₂It is the gain amplifier of the second single-ended output operational amplifier, two outputs of the operational amplifier of second both-end output connect second multiplier the 3rd, four-input terminal respectively, output termination the 3rd single-ended output operational amplifier positive input terminal of first multiplier, output termination the 3rd single-ended output operational amplifier negative input end of second multiplier, the grid of the 3rd single-ended output operational amplifier output termination the 3rd NMOS pipe, the source ground of the 3rd NMOS pipe.

Beneficial effect of the present invention: the present invention is by adopting five operational amplifiers and two multipliers, and utilize the 3rd NMOS pipe to carry out negative feedback, realized that the voltage between NMOS pipe and the 2nd NMOS pipe drain-source the two poles of the earth is proportional, when effectively realizing current sample, broken through the on all four limitation of three terminal potentials that requires power tube and sampling pipe in the Sampling techniques, than traditional current sample structure, the flexibility of this circuit structure is bigger, has improved the sample rate current precision simultaneously.

Description of drawings

Fig. 1 is traditional a kind of current sampling circuit structural representation.

Fig. 2 is traditional degenerative current sampling circuit structural representation of being with.

Fig. 3 is the current sampling circuit structural representation of the embodiment of the invention.

Fig. 4 is the particular circuit configurations schematic diagram of the multiplier of the embodiment of the invention.

Fig. 5 is the simulation result schematic diagram of the embodiment of the invention.

Embodiment

The invention will be further elaborated below in conjunction with accompanying drawing and specific embodiment.

The current sampling circuit of the embodiment of the invention as shown in Figure 3, comprise NMOS pipe MN6, the 2nd NMOS manages MN7, the 3rd NMOS manages MN8, first resistance R 4, also comprise the first single-ended output operational amplifier A1, the second single-ended output operational amplifier A2, the 3rd single-ended output operational amplifier A5, the first both-end output operational amplifier A3, the second both-end output operational amplifier A4, the first multiplier B1, the second multiplier B2, the grid of the one NMOS pipe MN6 is connected respectively to the positive input terminal of the first single-ended output operational amplifier A1, the grid of the positive input terminal of the second single-ended output operational amplifier A2 and the 2nd NMOS pipe MN7, the source electrode of the one NMOS pipe MN6 is connected respectively to the negative input end of the first single-ended output operational amplifier A1, one end of second input of the first multiplier B1 and first resistance R 4, the other end ground connection of first resistance R 4, the drain electrode of MN7 is managed in the drain electrode of NMOS pipe MN6 respectively with the 2nd NMOS, the first input end of the first multiplier B1 links to each other with the first input end of the second multiplier B2; The source electrode of the 2nd NMOS pipe MN7 connects the drain electrode of second input and the 3rd NMOS pipe MN8 of the second single-ended output operational amplifier A2 negative input end, the second multiplier B2 respectively, the positive input terminal of the operational amplifier A 3 of output termination first both-end output of the first single-ended output operational amplifier A1, the negative input end of the operational amplifier A 3 of first both-end output connects outside reference voltage source, the big or small a of outside reference voltage source ₁* V _TH, wherein, a ₁It is the gain amplifier of the first single-ended output operational amplifier A1, two outputs of the operational amplifier A 3 of first both-end output connect the first multiplier B1 the 3rd, four-input terminal respectively, the positive input terminal of the operational amplifier A 4 of output termination second both-end output of the second single-ended output operational amplifier A2, the negative input end of the operational amplifier A 4 of second both-end output connects outside reference voltage source, the big or small a of outside reference voltage source ₂* V _TH, wherein, a ₂It is the gain amplifier of the second both-end output operational amplifier A4, two outputs of the operational amplifier A 4 of second both-end output connect the second multiplier B2 the 3rd, four-input terminal respectively, output termination the 3rd single-ended output operational amplifier A5 positive input terminal of the first multiplier B1, output termination the 3rd single-ended output operational amplifier A5 negative input end of the second multiplier B2, the grid of the 3rd single-ended output operational amplifier A5 output termination the 3rd NMOS pipe MN8, the source ground of the 3rd NMOS pipe MN8.

The NMOS pipe MN6 here is a power tube, and the 2nd NMOS pipe MN7 is a sampling pipe, and NMOS pipe model and performance described here are identical, V _THThreshold voltage for the NMOS pipe.

Here, the one NMOS manages MN6, the 2nd NMOS manages MN7, the first single-ended output operational amplifier A1, the second single-ended output operational amplifier A2, the 3rd single-ended output operational amplifier A5, the first both-end output operational amplifier A3, the second both-end output operational amplifier A4 is those skilled in the art's a common practise, no longer is described in detail at this.

The first multiplier B1 is identical with the structure of the second multiplier B2, and as shown in Figure 4, it is made of two-stage, the first order is a Gilbert cell, and by NMOS pipe MN9, NMOS manages MN10, NMOS manages MN11, NMOS manages MN12, and NMOS manages MN13, and NMOS manages MN14, NMOS manages MN15, resistance R 6, resistance R 7 is formed, and can realize multiplication function; MP1 is managed by PMOS in the second level, and PMOS manages MP2, and NMOS manages MN16, and NMOS pipe MN17 forms, and realizes the single-ended output of both-end output changing into.

The annexation of this circuit is: the grid of NMOS pipe MN9 is as the first input end of the first couple input Vin1 of multiplier, connect the grid of NMOS pipe MN10, the source electrode of NMOS pipe MN9 connects the source electrode of NMOS pipe MN12 respectively, the drain electrode of NMOS pipe MN13, the drain electrode of NMOS pipe MN9 is the end of connecting resistance R6 respectively, the grid of the drain electrode of NMOS pipe MN11 and NMOS pipe MN16, another termination external power source VCC of resistance R 6, the grid of NMOS pipe MN10 connects the drain electrode of NMOS pipe MN12 and an end of resistance R 7 respectively, another termination external power source VCC of resistance R 7, the grid of NMOS pipe MN11 is as second input of the first couple input Vin1 of multiplier, connect the grid of NMOS pipe MN12 respectively, the grid of NMOS pipe MN17, the source electrode of NMOS pipe MN11 connects the source electrode of MN10 respectively, the drain electrode of NMOS pipe MN14, the grid of MN13 is as the first input end of the second couple input Vin2 of multiplier, the source electrode of MN13 connects the source electrode of NMOS pipe MN14 respectively, the drain electrode of NMOS pipe MN15, the grid of NMOS pipe MN14 is as second input of the second couple input Vin2 of multiplier, the source ground of NMOS pipe MN15, the grid of NMOS pipe MN15 connects the grid of PMOS pipe MP1 respectively, the drain electrode of PMOS pipe MP1, the grid of PMOS pipe MP2, the source electrode of PMOS pipe MP1 meets external power source VCC, and be connected with the source electrode of PMOS pipe MP2, the drain electrode of PMOS pipe MP2 connects the drain electrode of NMOS pipe MN17 respectively, the source electrode of NMOS pipe MN17 connects source electrode and the ground of NMOS pipe MN16 respectively, and the drain electrode of PMOS pipe MP2 is the output VOUT of multiplier.

Here first couple of input Vin1 and the second pair input Vin2 constituted four inputs of multiplier, respectively as first, second, third and four-input terminal of multiplier.

Foregoing circuit is adjusted parameter by rationally choosing pipe, can realize that output voltage equals the product of two input voltages, promptly has V _OUT=Vin1*Vin2 " rationally chooses pipe, adjusts parameter " common practise that belongs to this area here, no longer is described in detail at this.

In Fig. 3, the grid of positive input termination the one NMOS of first single-ended output operational amplifier A1 pipe MN6 pipe, negative input end first connects the source electrode of NMOS pipe MN6, is input as the poor of source gate voltage Be output as

Again with a ₁V _THCompare, with difference Be input to the first both-end output operational amplifier A3, its output connects two inputs of the first multiplier B1, and two other input of the first multiplier B1 connects the drain electrode and the source electrode of NMOS pipe MN6 pipe respectively, and its difference is

The first multiplier B1 is output as

a ₃It is the gain amplifier of the first both-end output operational amplifier A3.

The grid of positive input termination the 2nd NMOS pipe MN7 pipe of the second single-ended output operational amplifier A2, negative input end connects the source electrode of the 2nd NMOS pipe MN7, is input as the poor of source gate voltage

Be output as

Again with a ₂V _THCompare, with difference

Input both-end output operational amplifier A4, its output connects two inputs of the second multiplier B2, and two other input of the second multiplier B2 connects the drain electrode and the source electrode of the 2nd NMOS pipe MN7 pipe respectively, and its difference is

The second multiplier B2 is output as

a ₄It is the gain amplifier of the second both-end output operational amplifier A4.

The output of two multipliers is connected respectively to two inputs of the 3rd single-ended output amplifier A5, and the grid voltage of the 3rd NMOS pipe MN8 is controlled in the output of the 3rd single-ended output amplifier A5, adjusts voltage by the drain electrode output realization negative feedback of MN8.

Be operated in the resistance R between the drain-source of the 3rd NMOS pipe MN8 of dark linear zone _DSChange along with the change in voltage between the two poles of the earth, grid source, the physical relationship formula is:

As long as the input of the 3rd single-ended output amplifier A5 has imbalance, the grid potential of the 3rd NMOS pipe MN8 is constantly adjusted, and the drain potential of the 3rd NMOS pipe MN8 is also adjusted simultaneously, and two-way input signal clamper is equated.That is:

Be operated in the drain current expression formula I of dark linear zone NMOS pipe MN6, MN7 ₆, I ₇As follows:

I_{6} = μ_{n} C_{ox} {(\frac{W}{L})}_{6} (V_{G_{6} S_{6}} - V_{TH}) V_{D_{6} S_{6}};

I_{7} = μ_{n} C_{ox} {(\frac{W}{L})}_{7} (V_{G_{7} S_{7}} - V_{TH}) V_{D_{7} S_{7}} .

I ₆, I ₇Ratio be:

The electric current that then flows through sampling pipe MN7 is a power tube MN6 electric current Doubly, k is the breadth length ratio of two pipes,

Can preestablish by external circuit.

The simulation result of Fig. 5 shows, flows through the electric current I of sampling pipe MN7 ₇Be power tube MN6 electric current I ₆Amplification in proportion, amplified about 1400 times, realized the sampling function, simultaneously, than traditional current sample structure, the flexibility of this circuit structure is bigger, break through the on all four limitation of three terminal potentials that requires power tube and sampling pipe in the Sampling techniques, improved the precision of sample rate current.

Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that the protection range of inventing is not limited to such special statement and embodiment.Everyly make various possible being equal to according to foregoing description and replace or change, all be considered to belong to the protection range of claim of the present invention.

Claims

1. a current sampling circuit comprises NMOS pipe, the 2nd NMOS pipe, and the 3rd NMOS pipe, first resistance is characterized in that,

Also comprise the first single-ended output operational amplifier, the second single-ended output operational amplifier, the 3rd single-ended output operational amplifier, the first both-end output operational amplifier, the second both-end output operational amplifier, first multiplier, second multiplier; Wherein, the grid of the one NMOS pipe is connected respectively to the positive input terminal of the first single-ended output operational amplifier, the positive input terminal of the second single-ended output operational amplifier and the grid of the 2nd NMOS pipe, the source electrode of the one NMOS pipe is connected respectively to the negative input end of the first single-ended output operational amplifier, second input of first multiplier and an end of first resistance, the other end ground connection of first resistance, the drain electrode of a NMOS pipe link to each other with the drain electrode of the 2nd NMOS pipe, the first input end of first multiplier and the first input end of second multiplier respectively; The source electrode of the 2nd NMOS pipe connects second input of the second single-ended output operational amplifier negative input end, second multiplier and the drain electrode of the 3rd NMOS pipe respectively, the positive input terminal of the operational amplifier of output termination first both-end output of the first single-ended output operational amplifier, the negative input end of the operational amplifier of first both-end output connects outside reference voltage source, the big or small a of outside reference voltage source ₁* V _TH, wherein, a ₁It is the gain amplifier of the first single-ended output operational amplifier, two outputs of the operational amplifier of first both-end output connect first multiplier the 3rd, four-input terminal respectively, the positive input terminal of the operational amplifier of output termination second both-end output of the second single-ended output operational amplifier, the negative input end of the operational amplifier of second both-end output connects outside reference voltage source, the big or small a of outside reference voltage source ₂* V _TH, wherein, a ₂It is the gain amplifier of the second single-ended output operational amplifier, two outputs of the operational amplifier of second both-end output connect second multiplier the 3rd, four-input terminal respectively, output termination the 3rd single-ended output operational amplifier positive input terminal of first multiplier, output termination the 3rd single-ended output operational amplifier negative input end of second multiplier, the grid of the 3rd single-ended output operational amplifier output termination the 3rd NMOS pipe, the source ground of the 3rd NMOS pipe.

2. current sampling circuit according to claim 1 is characterized in that, described first multiplier is identical with the structure of described second multiplier, be made of two-stage, the first order is a Gilbert cell, by NMOS pipe MN9, NMOS manages MN10, and NMOS manages MN11, and NMOS manages MN12, NMOS manages MN13, NMOS manages MN14, and NMOS manages MN15, resistance R 6, resistance R 7 is formed, and can realize multiplication function; MP1 is managed by PMOS in the second level, and PMOS manages MP2, and NMOS manages MN16, and NMOS pipe MN17 forms, and realizes the single-ended output of both-end output changing into, and concrete annexation is as follows:

The grid of NMOS pipe MN9 is as the first input end of the first couple input Vin1 of multiplier, be connected to the grid of NMOS pipe MN10, the source electrode of NMOS pipe MN9 connects the source electrode of NMOS pipe MN12 respectively, the drain electrode of NMOS pipe MN13, the drain electrode of NMOS pipe MN9 is the end of connecting resistance R6 respectively, the grid of the drain electrode of NMOS pipe MN11 and NMOS pipe MN16, another termination external power source of resistance R 6, the grid of NMOS pipe MN10 connects the drain electrode of NMOS pipe MN12 and an end of resistance R 7 respectively, another termination external power source of resistance R 7, the grid of NMOS pipe MN11 is as second input of the first couple input Vin1 of multiplier, connect the grid of NMOS pipe MN12 respectively, the grid of NMOS pipe MN17, the source electrode of NMOS pipe MN11 connects the source electrode of NMOS pipe MN10 respectively, the drain electrode of NMOS pipe MN14, the grid of NMOS pipe MN13 is as the first input end of the second couple input Vin2 of multiplier, the source electrode of NMOS pipe MN13 connects the source electrode of NMOS pipe MN14 respectively, the drain electrode of NMOS pipe MN15, the grid of NMOS pipe MN14 is as second input of the second couple input Vin2 of multiplier, the source ground of NMOS pipe MN15, the grid of NMOS pipe MN15 connects the grid of PMOS pipe MP1 respectively, the drain electrode of PMOS pipe MP1, the grid of PMOS pipe MP2, the source electrode of PMOS pipe MP1 connects external power source, and be connected with the source electrode of PMOS pipe MP2, the drain electrode of PMOS pipe MP2 connects the drain electrode of NMOS pipe MN17 respectively, the source electrode of NMOS pipe MN17 connects source electrode and the ground of NMOS pipe MN16 respectively, and the drain electrode of PMOS pipe MP2 is the output of multiplier.