CN102097855B - Parallel running phase lock method for digital-controlled uninterruptible power supply - Google Patents
Parallel running phase lock method for digital-controlled uninterruptible power supply Download PDFInfo
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Abstract
The invention provides a parallel running phase lock method for a digital-controlled uninterruptible power supply. The parallel running phase lock method comprises the following steps of: A, calculating a periodic difference and a phase difference between a set signal of an inverter of each parallel uninterruptible power supply and a synchronizing signal for reference; B, calculating a phase difference between an output voltage of the inverter and the synchronizing signal; C, making the set signal of the inverter greater than the synchronizing signal for one phase difference, wherein the phase difference is the phase difference obtained in the step B; and D, performing phase lock on the set signal and the synchronizing signal. By the parallel running phase lock method, the influence of large circulation caused by switching of the uninterruptible power supply to bypass power supply on devices is reduced, the possibility of damage to the switch device of the inverter is reduced so that the uninterruptible power supply has no circulation or has the circulation within a limited range during switching, and the reliability of the parallel uninterruptible power supply system is improved.
Description
Technical field
The present invention relates to field of power electronics, specifically, relate to dereliction from the phase-locked control structure of parallel UPS system, make in parallel system each unit output voltage with reference to the synchronizing voltage homophase, thereby make the parallel system normal operation.
Background technology
Uninterrupted power supply requires output voltage consistent with the phase place of line voltage under the unit mode of operation, thereby circulation avoids damaging device in restricted portion during guarantee UPS failover.The purpose of uninterrupted power supply parallel running is to improve the stability of system power supply, and the unit fault withdraws from parallel system, and residue UPS continues to realize the guarantee of power supply to the important load power supply.
Fig. 1 is the schematic diagram of the given signal of inverter and output signal, the given signal of inverter is sinusoidal signal, and the common adoption rate of the inverter of Digital Control or ratio-integral control are according to classical control theory, can there be steady-state error in the output of inverter, comprises amplitude error and phase error.Amplitude error can be eliminated by the effective value outer shroud of inverter, and phase error can't be eliminated by control loop, can only eliminate by phase-locked mode.Fig. 2 is the traditional locks phase structure, and traditional digital UPS inverter phase-lock technique uses the method that the inverter output voltage zero passage is synchronizeed with the line voltage zero passage to realize phase-locked.Adopt the digital UPS of this phase-lock mode to have very large problem when parallel running, reason is, the output voltage phase place of two UPS is fixed, and is equivalent to phase-locked loop at the outer shroud of control loop.When phase-locked loop is in outside flow equalizing ring, the phase-locked sinusoidal given deviation of signal that brings can not be modulated by flow equalizing ring, and when causing the UPS parallel running, circulation is excessive.So, from combining system, must change the phase-locked structure of inverter, the adverse effect that sharing control is caused to reduce phase-locked deviation as far as possible for distributed dereliction.
Summary of the invention
For the defective of phase-locked structure in above-mentioned combining system, the present invention will solve existing phase-locked structure and control the adverse effect of bringing to circulation, to strengthen the reliability of parallel system.Purpose of the present invention realizes by following technical measures.
A kind of Digital Control uninterrupted power supply parallel running phase-lock technique, step comprises:
A: periodic inequality and the phase difference of given signal and the synchronizing signal that is used for reference that calculates the inverter of each parallel uninterrupted power supply: adopt the DSP timer, it is configured in acquisition mode, catch the synchronizing signal trailing edge, when the synchronizing signal trailing edge arrives, trigger capture interrupt and read the count value T1CAP_1 that catches, T1CAP_2, the difference T1CAP_2-T1CAP_1 that catches for twice is the cycle of synchronizing signal, PWM when sinusoidal pointer is zero interrupts reading the count value T1CNTR_1 of timer, T2CNTR_2, successively the count difference value T1CNTR_2-T1CNTR_1 of twice sinusoidal zero passage is the cycle of the given signal of inverter, thereby obtain the periodic inequality of given signal and synchronizing signal, time difference T1CNTR_1-T1CAP_1 between sine table zero passage and reference signal is used for calculating the phase difference between sinusoidal given signal and reference sync signal, thereby obtains the phase difference of given signal and synchronizing signal,
B: calculate the output voltage of inverter and the phase difference of synchronizing signal;
C: make phase difference of the leading synchronizing signal of the given signal of inverter, this phase difference is step B gained phase difference;
D: given signal and synchronizing signal is phase-locked.
When the DSP timer count down to maximum, counting again resetted.
The PWM half period of DSP advances PWM at every turn and interrupts, and the sine table pointer adds one, when reaching the sine table maximum number, and the pointer zero clearing.
The present invention has reduced the large circulation that produces to the impact of device when uninterrupted power supply switches to bypass power supply, reduced the probability that inverter switch device damages, guaranteed uninterrupted power supply when switching without circulation or circulation in limited range, strengthened the reliability of parallel uninterrupted power source system.
Description of drawings
The present invention will be further described to utilize accompanying drawing, but the content in accompanying drawing does not consist of any limitation of the invention.
Fig. 1 is the amplitude between the given signal of inverter and actual output, the schematic diagram of phase relation.
Fig. 2 is the schematic diagram of phase-locked structure of the prior art.
Fig. 3 is the schematic diagram of phase-locked structure of the present invention.
Fig. 4 is the schematic diagram of phase-lock technique of the present invention.
Fig. 5 be before phase compensation inverter output voltage synchronize with reference, the schematic diagram of the phase relation between given signal.
Fig. 6 be after phase compensation inverter output voltage with reference to synchronize, the schematic diagram of phase relation between given signal.
Embodiment
The invention will be further described with the following Examples.
Digital Control uninterrupted power supply parallel running phase-lock technique of the present invention such as Fig. 3-shown in Figure 6, step comprises:
A: periodic inequality and the phase difference of given signal and the synchronizing signal that is used for reference that calculates the inverter of each parallel uninterrupted power supply: adopt the DSP timer, it is configured in acquisition mode, catch the synchronizing signal trailing edge, when the synchronizing signal trailing edge arrives, trigger capture interrupt and read the count value T1CAP_1 that catches, T1CAP_2, the difference T1CAP_2-T1CAP_1 that catches for twice is the cycle of synchronizing signal, PWM when sinusoidal pointer is zero interrupts reading the count value T1CNTR_1 of timer, T2CNTR_2, successively the count difference value T1CNTR_2-T1CNTR_1 of twice sinusoidal zero passage is the cycle of the given signal of inverter, thereby obtain the periodic inequality of given signal and synchronizing signal, time difference T1CNTR_1-T1CAP_1 between sine table zero passage and reference signal is used for calculating the phase difference between sinusoidal given signal and reference sync signal, thereby obtains the phase difference of given signal and synchronizing signal,
B: calculate the output voltage of inverter and the phase difference of synchronizing signal;
C: make phase difference of the leading synchronizing signal of the given signal of inverter, this phase difference is step B gained phase difference;
D: given signal and synchronizing signal is phase-locked.
When the DSP timer count down to maximum, counting again resetted.
The PWM half period of DSP advances PWM at every turn and interrupts, and the sine table pointer adds one, when reaching the sine table maximum number, and the pointer zero clearing.
Technical program of the present invention lies in utilizing the DSP resource, the given signal of inverter is synchronizeed with reference sync signal, according to controller architecture and inverter parameter, given signal is carried out phase compensation again, thereby inverter output voltage is synchronizeed with line voltage.Fig. 3 is the phase-locked structural representation of the present invention.Fig. 4 is phase-locked schematic diagram, and phase-locked structure of the present invention is used the counter of DSP, makes it to be configured in acquisition mode, and when rolling counters forward arrived maximum, counter resetted and again counts.Capturing function is used for catching the trailing edge of reference sync signal, and when the synchronizing signal trailing edge arrived, the triggering capture interrupt read count value T1CAP_1, the T1CAP_2 that catches, and the difference T1CAP_2-T1CAP_1 that catches for twice is the cycle of reference sync signal.It is the internal interrupt of DSP that the heavy duty of PWM half period is interrupted, and the priority of this interruption is the highest, is used for inverter control.Advance PWM at every turn and interrupt, the sine table pointer adds one, when reaching the sine table maximum number, and the pointer zero clearing.For the phase place, the frequency that make the given signal of inverter (sine table) consistent with reference sync signal, can the PWM when sinusoidal pointer is zero interrupt reading count value T1CNTR_1, the T2CNTR_2 of timer, successively the count difference value T1CNTR_2-T1CNTR_1 of twice sinusoidal zero passage is the cycle of the given signal of inverter.Time difference T1CNTR_1-T1CAP_1 between sine table zero passage and reference signal is used for calculating the phase difference between sinusoidal given signal and reference sync signal.After periodic inequality, the phasometer of reference signal and conditioning signal calculate, can complete phase-lockedly, make both synchronous.
Use phase-locked structure of the present invention also must the phase place of inverter output voltage to be compensated, make it to synchronize with line voltage.Fig. 5 is the waveform schematic diagram before phase compensation, through phase-locked control, the sine table pointer with reference sync signal same-phase, same frequency.Because the given signal of inverter is sinusoidal signal, there is phase difference in output voltage, after given signal and reference sync signal (synchronizeing with civil power) same-phase, phase difference of the given signal of inverter lag output, it is the identical phase place of inverter lag output civil power, this phase difference can produce very large circulation when UPS switches to bypass power supply, make inverter switch device damage.When realizing that UPS switches without circulation or circulation in limited range, must accomplish that inverter output voltage synchronizes with line voltage.The present invention adopts the method for phase compensation, makes the certain phase place of the leading reference sync signal of the given signal of inverter.Fig. 6 is the waveform schematic diagram after sinusoidal given signal compensation, and when the leading reference sync signal of sinusoidal signal, the phase place of inverter output voltage is corresponding shifting to an earlier date also, reaches consistent with the reference sync signal phase place.The concrete numerical value of phase compensation amount, relevant with the inverter system of reality, depend on concrete controller parameter, major loop device parameters, inverter topology etc.
(1) DSP timer of configuration is operated in acquisition mode, this timer cycle, phase place of doing reference sync signal, and cycle, the phase place of sinusoidal given signal are calculated.The schematic diagram of Fig. 4 timer counter figure place used is 16, and timer resets when counting reaches maximum, the counting again of starting from scratch.
(2) when the synchronizing signal trailing edge arrives, timer generation capture interrupt records interrupt timer count value (T1CAP_1, T1CAP_2) constantly, and the count difference value (T1CAP_1-T1CAP_2) that twice interruption occurs is the cycle of synchronizing signal.
(3) the phase place set-point of inverter is provided by the sine table that is stored in the DSP internal memory.With in a pointed sine table certain a bit, As time goes on, the PWM interrupt routine makes the sine table pointer constantly add one, realize that given signal changes by sinusoidal rule, sinusoidal pointer be indicated to sine table last the time, sinusoidal pointer zero clearing realizes that the cycle of sinusoidal rule changes.
(4) sine table with the given process of synchronizeing of reference is, PWM when the sine table pointer is zero interrupts, read the count value (T1CNTR_1, T1CNTR_2) of timer, the difference in count (T1CNTR_2-T1CNTR_1) between twice zero passage is the cycle of sinusoidal given signal.
(5) phase-locked process also need read sine table zero point and the phase difference of reference sync signal between zero point, and the difference of catching count value of the count value of this difference during by sinusoidal zero passage when capture interrupt occurs determines (T1CNTR_1-T1CAP_1).
(6) process of sine table phase compensation is, measures the phase difference between the given signal of real system and inverter output voltage, calculates corresponding sine table points N.The trailing edge of sine table respective point and reference sync signal is coincide.Namely read the count value T1CNTR_1 of timer at compensation point, T1CNTR_2, difference between difference in count T1CNTR_2-T1CNTR_1 between twice compensation point is the cycle of sinusoidal given signal, and between given signal and reference sync signal, difference T1CNTR_1-T1CAP_1 is phase information.
Should be noted that at last; above embodiment only is used for technical scheme of the present invention being described but not limiting the scope of the invention; although with reference to preferred embodiment, the present invention has been done detailed description; those of ordinary skill in the art is to be understood that; can modify or be equal to replacement technical scheme of the present invention, and not break away from essence and the scope of technical solution of the present invention.
Claims (3)
1. Digital Control uninterrupted power supply parallel running phase-lock technique, it is characterized in that: step comprises:
A: periodic inequality and the phase difference of given signal and the reference sync signal that is used for reference that calculates the inverter of each parallel uninterrupted power supply: adopt the DSP timer, it is configured in acquisition mode, catch the reference sync signal trailing edge, when the reference sync signal trailing edge arrives, trigger capture interrupt and read the count value T1CAP_1 that catches, T1CAP_2, the difference T1CAP_2-T1CAP_1 that catches for twice is the cycle of reference sync signal, PWM when sinusoidal pointer is zero interrupts reading the count value T1CNTR_1 of timer, T2CNTR_2, successively the count difference value T1CNTR_2-T1CNTR_1 of twice sinusoidal zero passage is the cycle of the given signal of inverter, thereby obtain the periodic inequality of given signal and reference sync signal, time difference T1CNTR_1-T1CAP_1 between sine table zero passage and reference sync signal is used for calculating the phase difference between given signal and reference sync signal, thereby obtain the phase difference of given signal and reference sync signal, synchronize between the given signal that makes inverter and reference sync signal,
B: calculate the output voltage of inverter and the phase difference of reference sync signal;
C: make phase difference of the leading reference sync signal of the given signal of inverter, this phase difference is step B gained phase difference.
2. Digital Control uninterrupted power supply parallel running phase-lock technique according to claim 1, is characterized in that: when the DSP timer count down to maximum, reset and again count.
3. Digital Control uninterrupted power supply parallel running phase-lock technique according to claim 1 is characterized in that: the PWM half period of DSP advances PWM at every turn and interrupts, and the sine table pointer adds one, when reaching the sine table maximum number, and the pointer zero clearing.
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| CN102611134B (en) * | 2012-03-13 | 2014-03-19 | 电子科技大学 | Network voltage phase-frequency tracking method based on capturing unit |
| CN103713515B (en) * | 2012-09-28 | 2016-04-06 | 力博特公司 | A kind of determine compensation points method, device and realize the method for Repetitive controller |
| CN103217918B (en) * | 2013-04-28 | 2015-06-03 | 华南理工大学 | Synchronous implementation method and synchronous control device for three-phase uninterrupted power supply (UPS) parallel operation system |
| CN105846698B (en) * | 2015-01-16 | 2018-02-09 | 广东易事特电源股份有限公司 | Phase control rectifier method of controlling switch and device |
| CN113394811B (en) * | 2021-07-23 | 2023-08-18 | 深圳鹏城新能科技有限公司 | Method for synchronous phase locking through controller local area network and related device |
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| US6178103B1 (en) * | 2000-05-10 | 2001-01-23 | Ford Global Technologies, Inc. | Method and circuit for synchronizing parallel voltage source inverters |
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