CN102096220A - Drive circuit and output buffer - Google Patents
Drive circuit and output buffer Download PDFInfo
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- CN102096220A CN102096220A CN2009102462856A CN200910246285A CN102096220A CN 102096220 A CN102096220 A CN 102096220A CN 2009102462856 A CN2009102462856 A CN 2009102462856A CN 200910246285 A CN200910246285 A CN 200910246285A CN 102096220 A CN102096220 A CN 102096220A
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Abstract
The invention provides an output buffer which comprises a first switching circuit and a buffer, wherein the first switching circuit is used for receiving a first input signal and a second input signal; a buffer circuit comprises a first input stage, a second input stage, a first output stage, a second output stage and a second switching circuit; the first input stage and the second input stage are coupled to the first switching circuit; the first output stage and the second output stage are coupled to the second switching circuit; the second switching circuit is coupled to the first input stage and the second input stage and coupled to the first output stage and the second output stage; one of the first input stage and the second input stage is selectively coupled to the first output stage, and the other one of the first input stage and the second input stage is selectively coupled to the second output stage; and the first switching circuit selectively provides one of a first input signal and a second input signal for the first input stage and selectively provides the other one of the first input signal and the second input signal for the second input stage. The invention also provides a drive circuit applied to an electronic display device.
Description
Technical field
The present invention relates to a kind of driving circuit, relates to a kind of driving circuit that is applied in the electronic display unit particularly.
Background technology
LCD has advantages such as low radiation, low consumption, becomes the main flow of display gradually.LCD generally includes a plurality of source electrode drive circuits (Source Driver).Source electrode drive circuit drives the LCD panel in order to analog drive voltage to be provided.In the past, use two groups of output buffers in the source electrode driver, positive polarity output voltage and negative polarity output voltage are provided.So, corresponding to each delivery channel (Output Channel), source electrode driver can provide the analog drive voltage of reversal of poles to the LCD panel in the different picture frame cycle (Frame Period).Yet positive polarity and negative polarity output buffer may be because technological factor cause its critical voltage (Threshold Voltage) not match each other.So, with making the positive polarity analog drive voltage and the negative polarity analog drive voltage of the output of conventional source driver not match each other, cause abnormal demonstration.
Summary of the invention
The present invention relates to a kind of output buffer (Output Buffer), in order to drive first and second delivery channel, wherein output buffer comprises first input stage and second input stage.Output buffer that the present invention is correlated with is used commutation circuit and is switched the input signal of first and second input stage and the transmission path of output signal, makes signal that first and second input stage amplifies generation respectively by regularly as the output signal on first and second delivery channel.In other words, the present invention's output buffer of being correlated with can be used fixing input stage and comes fixing delivery channel is driven.In view of the above, compared to traditional output buffer, the output buffer that the present invention is correlated with can be avoided the conventional source driver effectively because the critical voltage (Threshold Voltage) between impact damper does not wherein match each other, output cathode that is caused and output negative pole analog drive voltage do not match and the shortcoming of corresponding undesired demonstration each other, and have output cathode and the output negative pole analog drive voltage is mated each other and display effect is good advantage effectively.
According to an aspect of the present invention, propose a kind of output buffer, be applied in the driving circuit, output buffer comprises first switched circuit and buffer circuit.First switched circuit is in order to receive first input signal and second input signal.Buffer circuit comprises first and second input stage, first and second output stage and second switched circuit.First and second input stage is coupled to first switched circuit.First and second output stage is coupled to second switched circuit.Second switched circuit is coupled to first and second input stage, and be coupled to first and second output stage, and in order to optionally one of them is coupled to first output stage with first and second input stage, and optionally wherein another of first and second input stage is coupled to second output stage.First switched circuit is also in order to optionally one of them provides to first input stage with first and second input signal, and optionally wherein another of first and second input signal provided to second input stage.
Preferably, output buffer of the present invention also comprises: first delivery channel and second delivery channel; And the 3rd switched circuit, be coupled to this first and this second output stage, and be coupled to this first and this second delivery channel, the 3rd switched circuit in order to optionally with this first and this second output stage one of them be coupled to this first delivery channel, and optionally with this first and wherein another of this second output stage be coupled to this second delivery channel.
Preferably, in output buffer of the present invention, under first operator scheme: this first switched circuit provides this first input signal to this first input stage; This first switched circuit provides this second input signal to this second input stage; This second switched circuit is coupled to this first output stage with this first input stage; This second switched circuit is coupled to this second output stage with this second input stage; The 3rd switched circuit is coupled to this first delivery channel with this first output stage; And the 3rd switched circuit this second output stage is coupled to this second delivery channel.
Preferably, in output buffer of the present invention, under second operator scheme: this first switched circuit provides this first input signal to this second input stage; This first switched circuit provides this second input signal to this first input stage; This second switched circuit is coupled to this second output stage with this first input stage; This second switched circuit is coupled to this first output stage with this second input stage; The 3rd switched circuit is coupled to this second delivery channel with this first output stage; And the 3rd switched circuit this second output stage is coupled to this first delivery channel.
Preferably, in output buffer of the present invention, this first and this second operator scheme operate in respectively in first operating period and second operating period, wherein this first and this second operating period crossover not each other.
According to a further aspect in the invention, propose a kind of driving circuit, be applied in the electronic display unit.Driving circuit comprises first and second change-over circuit and output buffer.First and second change-over circuit is respectively in order to provide first and second input signal.Output buffer comprises first switched circuit and buffer circuit.First switched circuit is in order to receive first input signal and second input signal.Buffer circuit comprises first and second input stage, first and second output stage and second switched circuit.First and second input stage is coupled to first switched circuit.First and second output stage is coupled to second switched circuit.Second switched circuit is coupled to first and second input stage, and be coupled to first and second output stage, and in order to optionally one of them is coupled to first output stage with first and second input stage, and optionally wherein another of first and second input stage is coupled to second output stage.First switched circuit is also in order to optionally one of them provides to first input stage with first and second input signal, and optionally wherein another of first and second input signal provided to second input stage.
For foregoing of the present invention can be become apparent, hereinafter the spy enumerates preferred embodiment, and conjunction with figs., is elaborated:
Description of drawings
Fig. 1 shows the calcspar according to the driving circuit of the embodiment of the invention.
Fig. 2 shows the detailed circuit diagram of the switched circuit SW1 of Fig. 1.
Fig. 3 shows the detailed circuit diagram of the switched circuit SW2 of Fig. 1.
Fig. 4 shows the detailed circuit diagram of the switched circuit SW3 of Fig. 1.
Fig. 5 shows the coherent signal sequential chart of the driving circuit 1 of Fig. 1.
Equivalent calcspar when the output buffer 10 that Fig. 6 A shows Fig. 1 is in the first polar operation state.
Equivalent calcspar when the output buffer 10 that Fig. 6 B shows Fig. 1 is in the second polar operation state
Embodiment
The driving circuit of the embodiment of the invention utilizes commutation circuit, switch first input stage and the input signal of second input stage and the transmission path of output signal in the impact damper, make first and second input stage amplify the signal that produces and be used to regularly as the output signal on first delivery channel and second delivery channel.
Please refer to Fig. 1, it shows the calcspar according to the driving circuit of the embodiment of the invention.Driving circuit 1 is used in the electronic display unit, and for instance, electronic display unit for example is a LCD.In an operational instances, driving circuit 1 is a source electrode driver, has a plurality of delivery channels, in order to a plurality of pixel columns (Column) in the LCD are driven, only shows the partial structure in the source electrode drive circuit in Fig. 1.
Driving circuit 1 comprises output buffer 10, first change-over circuit and second change-over circuit.First and second change-over circuit for example is a digital analog converter (DAC), in order in response to supplied with digital signal D1 and D2, provides analog input signal In1 and In2 respectively.For instance, the positive polarity DAC (PDAC) 12 of first change-over circuit for realizing with the P transistor npn npn, it is in order to provide the aanalogvoltage of positive polarity, and its common electrode voltage compared to electronic display unit has positive polarity; The negative polarity DAC (NDAC) 14 of second change-over circuit for realizing with the N transistor npn npn, it is in order to provide the aanalogvoltage of negative polarity, and its common electrode voltage compared to electronic display unit has negative polarity.
More comprise the time schedule controller (not shown) in the electronic display unit of the driving circuit 1 of the application embodiment of the invention, it is in order to provide reversal of poles control signal POL to driving circuit 1.Driving circuit 1 for example comprises logical circuit 16, in order to reversal of poles control signal POL is carried out logical operation, to produce control signal POL_PDAC, POL_NDAC, POLN_PDAC and POLN_NDAC.Control signal POL_PDAC, POL_NDAC, POLN_PDAC and POLN_NDAC are in order to control output buffer 10 aanalogvoltage of output cathode and negative polarity optionally, electronic display unit is carried out the driving operation of reversal of poles.
Switched circuit SW1 is in order to receive analog input signal In1 and In2, and in order to be controlled by control signal POL_PDAC, POL_NDAC, POLN_PDAC and POLN_NDAC, couple PDAC 12 and NDAC 14 one of them to input stage IST1, and wherein another of PDAC 12 and NDAC 14 be coupled to input stage IST2, one of them provides to input stage IST1 as switching signal S_In1 with analog input signal In1 and In2 thus, and wherein another of analog input signal In1 and In2 provided to input stage IST2 as switching signal S_In2.
Please refer to Fig. 2, it shows the detailed circuit diagram of the switched circuit SW1 of Fig. 1.For instance, switched circuit SW1 comprises transistor T 1-T4, and wherein transistor T 1 and T3 are P type gold oxygen half (PMOS) transistor, and its high signal level that is controlled by control signal POL_PDAC and POLN_PDAC respectively is for ending.It is accurate for conducting that transistor T 1 and T3 are controlled by the low signal position of control signal POL_PDAC and control signal POLN_PDAC more respectively, provides to input stage IST2 as switching signal S_In2 respectively analog input signal In1 is provided to input stage IST1 and with analog input signal In1 as switching signal S_In1.
Transistor T 2 and T4 are N type gold oxygen half (NMOS) transistor, and its low signal position that is controlled by control signal POL_NDAC and POLN_NDAC respectively is accurate for ending.The high signal level that transistor T 2 and T4 also are controlled by control signal POL_NDAC and control signal POLN_NDAC respectively is conducting, provides to input stage IST2 as switching signal S_In2 respectively analog input signal In2 is provided to input stage IST1 and with analog input signal In2 as switching signal S_In1.
Input stage IST1 and IST2 for example realize with the input stage circuit of operational amplifier that it is in order to switching signal S_In1 and S_In2 are carried out main gain (Gain) amplification, to produce amplifying signal A_In1 and A_In2.
Please refer to Fig. 3, it shows the detailed circuit diagram of the switched circuit SW2 of Fig. 1.Switched circuit SW2 receives amplifying signal A_In1 and A_In2, and be controlled by control signal POL_PDAC, POL_NDAC, POLN_PDAC and POLN_NDAC, one of them is coupled to output stage OST1 with input stage IST1 and IST2, and wherein another of input stage IST1 and IST2 is coupled to output stage OST2; One of them provides to output stage OST1 as switching signal S ' _ In1 with amplifying signal A_In1 and A_In2 thus, and wherein another of amplifying signal A_In1 and A_In2 provided to output stage OST2 as switching signal S ' _ In2.For instance, switched circuit SW2 has identical in fact circuit structure and circuit operation with switched circuit SW1.Switched circuit SW2 comprises transistor T 1 '-T4 ', is comparable to the operation of transistor T 1-T4 respectively in order to execution, no longer its operation is given unnecessary details at this.
Output stage OST1 and OST2 for example realize with the output-stage circuit of operational amplifier that it is in order to carry out power amplification to switching signal S ' _ In1 and S ' _ In2, to produce amplifying signal A ' _ In1 and A ' _ In2.
Please refer to Fig. 4, it shows the detailed circuit diagram of the switched circuit SW3 of Fig. 1.Switched circuit SW3 receives amplifying signal A ' _ In1 and A ' _ In2, and be controlled by control signal POL_PDAC, POL_NDAC, POLN_PDAC and POLN_NDAC, one of them is coupled to delivery channel CH1 with output stage OST1 and OST2, and wherein another of output stage OST1 and OST2 is coupled to delivery channel CH2; One of them provides to delivery channel CH1 as output signal Out1 with amplifying signal A ' _ In1 and A ' _ In2 thus, and wherein another of amplifying signal A ' _ In1 and A ' _ In2 provided to delivery channel CH2 as output signal Out2.
For instance, switched circuit SW3 has identical in fact circuit structure and circuit operation with switched circuit SW1 and SW2.Switched circuit SW3 comprises transistor T 1 "-T4 ", be comparable to the operation of transistor T 1-T4 and T1 '-T4 ' respectively in order to execution, no longer its operation is given unnecessary details at this.
Delivery channel CH1 and CH2 receive output signal Out1 and Out2 respectively, and drive corresponding pixel column according to this respectively.For instance, delivery channel CH1 and CH2 for example correspond to capable pixel of 2i+1 and the capable pixel of 2i+2 in the display panel of electronic type display device, and i is the integer more than or equal to 0.Suppose that i equals 0, then delivery channel CH1 and CH2 correspond to the 1st and the 2nd row pixel of this display panel respectively, and in order to provide analog voltage signal to drive the 1st and the 2nd row pixel respectively.
Please refer to Fig. 5, it shows the coherent signal sequential chart of the driving circuit 1 of Fig. 1.Output buffer 10 is controlled by reversal of poles control signal POL, is in the first polar operation state during operation among the TI1, and is in the second polar operation state among the TI2 during operation.For instance, in the first polar operation state, the signal on delivery channel CH1 and the CH2 corresponds to positive polarity and negative polarity respectively; In second polar operation, the signal on delivery channel CH1 and the CH2 corresponds to negative polarity and positive polarity respectively.
Further, among the TI1, reversal of poles control signal POL, control signal POL_NDAC and POL_PDAC have low signal position standard during operation, and control signal POLN_PDAC and POLN_NDAC have high signal level.In view of the above, transistor T 2, T2 ', T2 ", T3, T3 ' and T3 " for ending, and transistor T 1, T1 ', T1 ", T4, T4 ' and T4 " be conducting, make output buffer 10 have equivalent calcspar as shown in Figure 6A, with according to input simulating signal In1 with positive polarity, output signal Out1 with positive polarity is provided on delivery channel CH1, and, on delivery channel CH2, provides output signal Out2 with negative polarity according to input simulating signal In2 with negative polarity.
Among the TI2, reversal of poles control signal POL, control signal POL_NDAC and POL_PDAC have high signal level during operation, and control signal POLN_PDAC and POLN_NDAC have low signal position standard.In view of the above, transistor T 1, T1 ', T1 ", T4, T4 ' and T4 " for ending, and transistor T 2, T2 ', T2 ", T3, T3 ' and T3 " be conducting, make output buffer 10 have the equivalent calcspar shown in Fig. 6 B, to provide output signal Out2 with positive polarity according to the correspondence on delivery channel CH2 of the input simulating signal In1 with positive polarity, and according to the input simulating signal In2 with negative polarity, the corresponding output signal Out1 that provides on delivery channel CH1 with negative polarity.
In an example, also have TO1 and TO2 between transfer period during operation between TI1 and the TI2.Among TO1 and the TO2, control signal POL_PDAC and POLN_PDAC have high signal level between transfer period, and control signal POL_NDAC and POLN_NDAC have low signal position standard.In view of the above, transistor T 1-T4, T1 '-T4 ' and T1 "-T4 " all end, making input and the output node of input stage IST1 and IST2 and output stage OST1 and OST2 is suspension joint (Floating), with avoid switched circuit SW1-SW3 in response to the accurate change in the position time (Transition) long control signal POL_PDAC, POL_NDAC, POLN_PDAC and POLN_NDAC produce misoperation (Malfunction).
In an example, logical circuit 16 also provides bias voltage signal PH and PL to output stage OST1 and OST2.Bias voltage signal PH and PL activation are between transfer period among TO1 and the TO2, in order to when the input node of output stage OST1 and OST2 and output node are suspension joint, provide reference bias respectively to output stage OST1 and OST2, operate in desirable operation bias voltage to guarantee output stage OST1 and OST2 with high signal level VDD and the accurate VSS in low signal position.
In one embodiment, input stage IST1 and IST2 need switching signal S_In1 with positive polarity and the switching signal S_In2 with negative polarity are carried out amplifieroperation, in view of the above, input stage IST1 and IST2 need be driven by track to track (Rail To Rail) power supply signal, promptly are the high voltage signal of power supply signal of input stage IST1 and IST2 and ceiling voltage signal VDD and the minimum voltage signal VSS that low voltage signal need equal output signal Out1 and Out2 respectively.
In one embodiment, output stage OST1 is only in order to carrying out amplifieroperation to the switching signal S ' _ In1 with positive polarity, and output stage OST2 is only in order to carry out amplifieroperation to the switching signal S ' _ In2 with negative polarity.In view of the above, output stage OST1 and OST2 can be driven by half voltage source signal (Half Supply), promptly are the high voltage signal of power supply signal of output stage OST1 and ceiling voltage signal VDD and the half voltage signal VDD/2 that low voltage signal can only equal output signal Out1 and Out2 respectively; And the high voltage signal of the power supply signal of output stage OST2 and low voltage signal can only equal half voltage signal VDD/2 and the minimum voltage signal VSS of output signal Out1 and Out2 respectively.
The output buffer of present embodiment comprises first and second input stage, and it is responsible for main gain amplifieroperation.Output buffer that the present invention is correlated with is used commutation circuit and is switched the input signal of first and second input stage and the transmission path of output signal, makes signal that first and second input stage amplifies generation respectively by regularly as the output signal on first and second delivery channel.In other words, the present invention's output buffer of being correlated with can be used fixing input stage and comes fixing delivery channel is driven.So compared to traditional output buffer, the output buffer that the present invention is correlated with can be avoided the conventional source driver effectively because the critical voltage (Threshold Voltage) between impact damper does not wherein match each other, output cathode that is caused and output negative pole analog drive voltage do not match and the shortcoming of corresponding undesired demonstration each other, and have output cathode effectively and the output negative pole analog drive voltage is mated each other and display effect advantage preferably.
In addition, the output buffer of the embodiment of the invention also comprises first and second output stage, and for example uses half voltage source signal and come first and second output stage is driven.In view of the above, the output buffer of the embodiment of the invention also has the lower advantage of dissipation power.
In addition, also using four control signals in the output buffer of the embodiment of the invention comes sequential control is carried out in the reversal of poles operation of output buffer, with between configuration transfer period between first and second main operating period of output buffer (respectively in order to output signal that first polarization state is provided and the output signal of second polarization state), to guarantee first and second main operating period crossover (Non-overlapped) not each other, to avoid because first to the 3rd switched circuit in the output buffer produces misoperation (Malfunction).
In sum, though the present invention be illustrated with preferred embodiment, yet its purpose is not intended to limit the invention.The general technical staff of the technical field of the invention without departing from the spirit and scope of the present invention, should do various changes and modification.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.
Main element numbers explanation
1: drive circuit
12: the positive polarity digital analog converter
14: the negative polarity digital analog converter
16: logic circuit
10: the output buffer
SW1, SW2, SW3: switched circuit
BF: buffer circuit
IST1, IST2: input stage
OST1, OST2: output stage
T1-T4, T1 '-T4 '-, T1 "-T4 ": transistor.
Claims (6)
1. an output buffer is applied in the driving circuit, and described output buffer comprises:
First switched circuit is in order to receive first input signal and second input signal; And
Buffer circuit comprises:
First input stage and second input stage are coupled to described first switched circuit;
First output stage and second output stage are coupled to described second switched circuit; And
Second switched circuit, be coupled to described first and described second input stage, and be coupled to described first and described second output stage, described second switched circuit in order to optionally with described first and described second input stage one of them be coupled to described first output stage, and selectivity with described first and wherein another of described second input stage be coupled to described second output stage; And
Wherein, described first switched circuit more in order to optionally with described first and described second input signal one of them provide to described first input stage, and optionally with described first and wherein another of described second input signal provide to described second input stage.
2. output buffer according to claim 1 also comprises:
First delivery channel and second delivery channel; And
The 3rd switched circuit is coupled to described first and described second output stage, and is coupled to described first and described second delivery channel, described the 3rd switched circuit in order to optionally with described first and described second output stage one of them be coupled to described
First delivery channel, and optionally with described first and wherein another of described second output stage be coupled to described second delivery channel.
3. output buffer according to claim 2, wherein, under first operator scheme:
Described first switched circuit provides described first input signal to described first input stage;
Described first switched circuit provides described second input signal to described second input stage;
Described second switched circuit is coupled to described first output stage with described first input stage;
Described second switched circuit is coupled to described second output stage with described second input stage;
Described the 3rd switched circuit is coupled to described first delivery channel with described first output stage; And
Described the 3rd switched circuit is coupled to described second delivery channel with described second output stage.
4. output buffer according to claim 2, wherein, under second operator scheme:
Described first switched circuit provides described first input signal to described second input stage;
Described first switched circuit provides described second input signal to described first input stage;
Described second switched circuit is coupled to described second output stage with described first input stage;
Described second switched circuit is coupled to described first output stage with described second input stage;
Described the 3rd switched circuit is coupled to described second delivery channel with described first output stage; And
Described the 3rd switched circuit is coupled to described first delivery channel with described second output stage.
5. output buffer according to claim 4, wherein, described first and described second operator scheme operate in respectively in first operating period and second operating period, wherein said first and described second operating period crossover not each other.
6. a driving circuit is applied in the electronic display unit, and described driving circuit comprises:
First change-over circuit and second change-over circuit are respectively in order to provide first input signal and second input signal; And
A kind of output buffer comprises:
First switched circuit is in order to receive described first and described second input signal; And
Buffer circuit comprises:
First input stage and second input stage are coupled to described first switched circuit;
First output stage and second output stage are coupled to described second switched circuit; And
Second switched circuit, be coupled to described first and described second input stage, and be coupled to described first and described second output stage, described second switched circuit in order to optionally with described first and described second input stage one of them be coupled to described first output stage, and optionally with described first and wherein another of described second input stage be coupled to described second output stage;
Wherein, described first switched circuit also in order to optionally with described first and described second input signal one of them provide to described first input stage, and optionally with described first and wherein another of described second input signal provide to described second input stage.
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| CN200910246285A CN102096220B (en) | 2009-12-15 | 2009-12-15 | Drive circuit and output buffer |
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| CN200910246285A CN102096220B (en) | 2009-12-15 | 2009-12-15 | Drive circuit and output buffer |
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Cited By (1)
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| CN102968976A (en) * | 2012-08-29 | 2013-03-13 | 友达光电股份有限公司 | driving circuit and display driving method |
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| KR100510500B1 (en) * | 2002-12-05 | 2005-08-26 | 삼성전자주식회사 | TFT-LCD source driver integrated circuit for improving display quality and Method for eliminating offset of output amplifier |
| JP2008065286A (en) * | 2006-09-11 | 2008-03-21 | Nec Lcd Technologies Ltd | Liquid crystal display device and control method of liquid crystal display device |
| JP2008185915A (en) * | 2007-01-31 | 2008-08-14 | Nec Electronics Corp | Liquid crystal display device, source driver and method for driving liquid crystal display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102968976A (en) * | 2012-08-29 | 2013-03-13 | 友达光电股份有限公司 | driving circuit and display driving method |
| CN102968976B (en) * | 2012-08-29 | 2015-11-18 | 友达光电股份有限公司 | driving circuit and display driving method |
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