CN102087880A - Initialization method of memory element - Google Patents
Initialization method of memory element Download PDFInfo
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- CN102087880A CN102087880A CN2009102538376A CN200910253837A CN102087880A CN 102087880 A CN102087880 A CN 102087880A CN 2009102538376 A CN2009102538376 A CN 2009102538376A CN 200910253837 A CN200910253837 A CN 200910253837A CN 102087880 A CN102087880 A CN 102087880A
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Abstract
The invention provides an initialization method of a memory element, comprising a step of transmitting at least N+1 clock periods to the memory element, wherein N represents the digit of a serial data output by the memory element. One of the clock periods is used for transmitting a first commencement and termination signal to the memory element. The other one of the clock periods is used for transmitting a second commencement and termination signal to the memory element.
Description
Technical field
The present invention relates to a kind of TW two wire transmission interface, and be particularly related to a kind of initial method of memory component with TW two wire transmission interface.
Background technology
General TW two wire transmission interface, for example (Inter-integrated Circuit Bus, the I of the bus between the integrated circuit
2C Bus), be to utilize serial clock (serial clock, SCL) (serial data, SDA) these two lines transmit data with serial data.(liquid crystal display LCD) is example, and its time schedule controller (timing controller) just can utilize I with LCD
2C go the access EEPROM (Electrically Erasable Programmable Read Only Memo) (electrically erasable programmable read-only memory, EEPROM).Time schedule controller provides SCL to EEPROM, with synchronous communication sequential each other.Data transfer between time schedule controller and the EEPROM only depends on this bus of SDA.Time schedule controller must pass through I
2C goes the related setting data in the access EEPROM.
Fig. 1 is that the explanation time schedule controller passes through I
2C is to fetch program that EEPROM carried out.Time schedule controller provides SCL to EEPROM.The sequential that cooperates SCL, time schedule controller transmits reading requirement via sda line and gives EEPROM.After obtaining reading requirement, the SCL sequential that EEPROM matching timing controller provides returns corresponding data to time schedule controller via sda line.
Please refer to Fig. 1, time schedule controller sends start signal (start signal) S via sda line and gives EEPROM, makes EEPROM enter the state that receives control byte (control byte).Time schedule controller and then send contain identification code and read write command control byte to EEPROM.The identification code of supposing EEPROM is 001, and the time schedule controller desire writes EEPROM with the target address, so time schedule controller can be passed to EEPROM for the control byte of " 1,010 001 0 " with content, wherein last position " 0 " is the instruction of expression " writing ".Finish the operation of reception control byte through 8 clock period after, and then EEPROM gives time schedule controller via sda line passback confirmation signal ACK (being logical zero).After time schedule controller is received confirmation signal ACK, just data (being aforesaid target address) are write EEPROM via sda line.After finishing the operation of receiving target address through 8 clock period, and then EEPROM returns confirmation signal ACK and gives time schedule controller.So far, time schedule controller has been finished the operation to the EEPROM addressing.
Time schedule controller sends start signal S to EEPROM via sda line again, makes EEPROM enter the state that receives control byte once more.And then time schedule controller sends control byte to EEPROM.Owing to will carry out read operation to EEPROM, so time schedule controller can pass to EEPROM for the control byte of " 1,010 001 1 " with content, and wherein last position " 1 " is the instruction of expression " reading ".Finish the operation of reception control byte through 8 clock period after, and then EEPROM gives time schedule controller via sda line passback confirmation signal ACK, and then returns to time schedule controller through the corresponding data of 8 clock period with previous addressing.After finishing the data passback, and then EEPROM gives time schedule controller via sda line return path signal NO_ACK.At last, time schedule controller sends stop signal (stop signal) P via sda line and gives EEPROM, makes EEPROM enter the state of initialization (initialize) (promptly waiting for the state of the order that receives major component).So far, time schedule controller has been finished the fetch program that EEPROM is carried out.
Yet, in the above-mentioned fetch program, may unusual surging (glitch) or other factors be arranged because of reset signal (reset signal) and cause the read interruption of time schedule controller EEPROM.When time schedule controller carries out the fetch program to EEPROM again, cause EEPROM may be parked in the state that to arrange because of previous fetch program aborted, thereby cause time schedule controller to read again again.So time schedule controller must first initialization EEPROM before EEPROM is carried out the fetch program.
Summary of the invention
The invention provides a kind of initialization (initialize) method of memory component,, all can make memory component return back to init state no matter which kind of mode of operation memory component is in.
The embodiment of the invention proposes a kind of initial method of memory component, comprises that transmitting at least N+1 clock period gives this memory component, and wherein N exports serial data figure place for this memory component.During the clock period of described N+1 at least in the clock period, transmit first the beginning and the end signal and give this memory component.During described N+1 at least another clock period in the clock period, transmit second the beginning and the end signal and give this memory component.
In an embodiment of the present invention, except that above-mentioned first the beginning and the end signal and second the beginning and the end signal, do not transmit any signal in during the described clock period of N+1 at least and give this memory component.
In an embodiment of the present invention, above-mentioned first the beginning and the end signal and second the beginning and the end signal can be start signal or stop signal.
In an embodiment of the present invention, the time of above-mentioned transmission first the beginning and the end signal is in described N+1 at least first clock period in the clock period.
In an embodiment of the present invention, above-mentioned first the beginning and the end signal and second at least one clock period in the beginning and the end sigtnal interval.
In an embodiment of the present invention, except that described first the beginning and the end signal and described second the beginning and the end signal, also transmit at least one the 3rd the beginning and the end signal in the clock period at described N+1 at least and give this memory component.
Based on above-mentioned, the embodiment of the invention transmits two or more a plurality of the beginning and the end signal and gives this memory component in N+1 clock period at least.Therefore, during the non-output data of memory component, first the beginning and the end signal can enter initialized state by the flip-flop storage element.If first the beginning and the end signal conflicts mutually with the affirmation signal of memory component passback, then can send second the beginning and the end signal to memory component definitely, so that memory component enters initialized state.During output data at memory component, though sending these the beginning and the end signals of this memory component to can conflict mutually with the data of memory component output, but through supplying with memory component at least after N+1 clock period, can impel memory component end output data during/state and enter initialized state.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and be described in detail below in conjunction with the accompanying drawings.
Description of drawings
Fig. 1 is that the explanation time schedule controller passes through I
2C is to fetch program that EEPROM carried out.
Fig. 2 is the initial method that a kind of memory component is described according to the embodiment of the invention.
Embodiment
Fig. 2 is the initial method that a kind of memory component is described according to the embodiment of the invention.Major component (for example time schedule controller) is by TW two wire transmission interface access memory element (for example EEPROM).This TW two wire transmission interface (I for example
2The C bus) (serial clock is SCL) with serial data (serial data, SDA) these two lines to comprise serial clock.Major component provides the clock period to memory component by scl line, with synchronous communication sequential each other.Cooperate the sequential of scl line, major component sends to memory component such as the beginning and the end signal, control byte, address data by sda line.Memory component also cooperates the sequential of scl line, sends to major component such as confirmation signal, output serial data by this sda line.
When major component was desired this memory component of initialization, major component provides at least N+1 clock period by scl line, and wherein N was that this memory component is exported serial data figure place to memory component.With the fetch program shown in Figure 1 be example, the figure place of the output serial data of this memory component is 8, is 8 so can set N.Routine according to this, then major component provides at least 9 clock period to memory component by scl line.
In (during N+1 clock period) during this initialization, major component cooperates the sequential of scl line to select two clock period in these clock period, and transmits first the beginning and the end signal SP1 and second the beginning and the end signal SP2 to memory component in this two clock period by sda line.The beginning and the end signal SP1 and SP2 can be start signal S, or are stop signal P.Perhaps, described first the beginning and the end signal SP1 is start signal S, and described second the beginning and the end signal SP2 is stop signal P.
In the present embodiment, first in these clock period and the 3rd clock period are transmitted the beginning and the end signal SP1 and SP2 to memory component to major component respectively.During this initialization (N+1 clock period), except the beginning and the end signal SP1 and SP2, major component can transmit any signal (for example signal of the signal of logical zero or logical one).In the present embodiment, except that the beginning and the end signal SP1 and SP2, major component does not transmit signal in during these clock period and gives memory component.
The delivery time point of above-mentioned the beginning and the end signal SP1 and SP2 is not limited to shown in Figure 2.The beginning and the end signal SP1 and SP2 are transmitted to memory component in any two clock period of these N+1 in the clock period.The beginning and the end signal SP1 and SP2 can be continuous, and be just at interval not free between the two.Perhaps, the beginning and the end signal SP1 and SP2 one or more clock period of interval.
If aborted takes place in memory component NOP (for example shown in Figure 1) during non-output data, because the ownership of sda line belongs to major component, so major component can make memory component enter initialized state (promptly waiting for the state of the order that receives major component) by first the beginning and the end signal SP1 (for example being stop signal P).Though NOP during non-output data, the ownership of sda line belongs to major component, yet memory component still needs to give major component by sda line passback confirmation signal ACK (for example shown in Figure 1) during this period.The ACK if the affirmation signal of first the beginning and the end signal SP1 and memory component passback conflicts mutually, then second the beginning and the end signal SP2 (for example being stop signal P) must send memory component very definitely to.That is to say that even if first the beginning and the end signal SP1 initialization failure, second the beginning and the end signal SP2 must be so that memory component enters initialized state (promptly waiting for the state of the order that receives major component).
Using the present embodiment person can look its design requirement and determine the beginning and the end number of signals during this initialization (N+1 clock period).For example, except that described first the beginning and the end signal SP1 and described second the beginning and the end signal SP2, in described a plurality of clock period, also transmit at least one the 3rd the beginning and the end signal (for example being stop signal P, not shown) and give this memory component.
If aborted takes place memory component OP (for example shown in Figure 1) during output data, because ownership of sda line belongs to memory component during this, so the beginning and the end signal SP1 that major component transmitted all can conflict with the output of memory component mutually with SP2.That is to say that OP during this output data, major component can't transmit the beginning and the end signal and give memory component, can't make memory component enter initialized state by OP certainly during output data.Therefore, major component can by the SCK line transmitted greater than N clock period, impel memory component to finish the output of N bit data.Finish the output of N bit data when memory component after, naturally and understandably, during memory component just can finish output data/state and enter initialized state (promptly wait for and please refer to the explanation of Fig. 1 by the state of the order that receives major component).Next, major component can begin this memory component of access normally, for example carries out the fetch program shown in Figure 1.
In sum, no matter memory component under which kind of mode of operation aborted takes place, after finishing the initial method of above-mentioned memory component, can make memory component return back to init state effectively.Therefore, carry out after initialized N+1 clock period finish above-mentioned, major component can begin this memory component of access normally.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; can make many modifications and modification, so protection scope of the present invention is when being as the criterion with appended claim.
Claims (12)
1. the initial method of a memory component comprises:
If the output serial data of described memory component is the N position, then transmit at least N+1 clock period to described memory component;
Select a clock cycle in the clock period at described N+1 at least, transmit first the beginning and the end signal and give described memory component; And
Select another clock period at described N+1 at least in the clock period, transmit second the beginning and the end signal and give described memory component.
2. the initial method of memory component as claimed in claim 1, wherein, during the described clock period of N+1 at least in, except that described first the beginning and the end signal and described second the beginning and the end signal, do not transmit signal and give described memory component.
3. the initial method of memory component as claimed in claim 1, wherein, described first the beginning and the end signal and described second the beginning and the end signal are start signal.
4. the initial method of memory component as claimed in claim 1, wherein, described first the beginning and the end signal and described second the beginning and the end signal are stop signal.
5. the initial method of memory component as claimed in claim 1, wherein, described first the beginning and the end signal is a start signal, and described second the beginning and the end signal is a stop signal.
6. the initial method of memory component as claimed in claim 1 wherein, transmits the time of described first the beginning and the end signal, is in described N+1 at least first clock period in the clock period.
7. the initial method of memory component as claimed in claim 1, wherein, described first the beginning and the end signal and described second at least one clock period in the beginning and the end sigtnal interval.
8. the initial method of memory component as claimed in claim 1 also comprises:
Except that described first the beginning and the end signal and described second the beginning and the end signal, also transmit at least one the 3rd the beginning and the end signal in the clock period at described N+1 at least and give described memory component.
9. the initial method of memory component as claimed in claim 8, wherein, described the 3rd the beginning and the end signal is a stop signal.
10. the initial method of memory component as claimed in claim 1 wherein, after described N+1 at least clock period finishes, begins the described memory component of access.
11. the initial method of memory component as claimed in claim 1, wherein, described memory component receives described a plurality of clock period, described first the beginning and the end signal and described second the beginning and the end signal by the TW two wire transmission interface.
12. the initial method of memory component as claimed in claim 11, wherein, described TW two wire transmission interface is I
2C.
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| CN 200910253837 CN102087880B (en) | 2009-12-08 | 2009-12-08 | Initialization method of memory element |
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| CN 200910253837 CN102087880B (en) | 2009-12-08 | 2009-12-08 | Initialization method of memory element |
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| CN102087880A true CN102087880A (en) | 2011-06-08 |
| CN102087880B CN102087880B (en) | 2013-09-18 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109741776A (en) * | 2018-12-29 | 2019-05-10 | 广东高云半导体科技股份有限公司 | Initial method, device, equipment and the medium of blocky Static RAM |
| CN116580742A (en) * | 2023-07-14 | 2023-08-11 | 芯天下技术股份有限公司 | NOR FLASH resetting method and device, memory chip and equipment |
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| TW327212B (en) * | 1994-06-27 | 1998-02-21 | Microchip Tech Inc | Memory device with switching of data stream modes |
| US7036004B2 (en) * | 2001-07-25 | 2006-04-25 | Micron Technology, Inc. | Power up initialization for memory |
| US7554843B1 (en) * | 2005-11-04 | 2009-06-30 | Alta Analog, Inc. | Serial bus incorporating high voltage programming signals |
| CN101499314A (en) * | 2008-01-29 | 2009-08-05 | 财团法人工业技术研究院 | Memory device and its updating method |
-
2009
- 2009-12-08 CN CN 200910253837 patent/CN102087880B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW327212B (en) * | 1994-06-27 | 1998-02-21 | Microchip Tech Inc | Memory device with switching of data stream modes |
| US7036004B2 (en) * | 2001-07-25 | 2006-04-25 | Micron Technology, Inc. | Power up initialization for memory |
| US7554843B1 (en) * | 2005-11-04 | 2009-06-30 | Alta Analog, Inc. | Serial bus incorporating high voltage programming signals |
| CN101499314A (en) * | 2008-01-29 | 2009-08-05 | 财团法人工业技术研究院 | Memory device and its updating method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109741776A (en) * | 2018-12-29 | 2019-05-10 | 广东高云半导体科技股份有限公司 | Initial method, device, equipment and the medium of blocky Static RAM |
| CN116580742A (en) * | 2023-07-14 | 2023-08-11 | 芯天下技术股份有限公司 | NOR FLASH resetting method and device, memory chip and equipment |
| CN116580742B (en) * | 2023-07-14 | 2023-09-26 | 芯天下技术股份有限公司 | NOR FLASH resetting method and device, memory chip and equipment |
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| CN102087880B (en) | 2013-09-18 |
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