CN102087880A - Initialization method of memory element - Google Patents

Abstract

A method for initializing a memory device includes transmitting at least N +1 clock cycles to the memory device, where N is the number of serial data bits output by the memory device. During one of the clock cycles, a first acknowledgement signal is transmitted to the memory element. A second origin-destination signal is communicated to the memory element during another one of the clock cycles.

Description

Initialization method of memory element

technical field

The invention relates to a two-wire transmission interface, and in particular to an initialization method of a memory element with a two-wire transmission interface.

Background technique

The general two-wire transmission interface, such as the bus between integrated circuits (Inter-integrated Circuit Bus, I ² C Bus), is to use the serial clock (serial clock, SCL) and serial data (serial data, SDA) two wire to transmit data. Taking a liquid crystal display (LCD) as an example, its timing controller can use I ² C to access an electrically erasable programmable read-only memory (EEPROM). The timing controller provides SCL to the EEPROM to synchronize the communication timing of each other. The data transmission between the timing controller and the EEPROM only depends on the SDA bus. The timing controller must access the relevant setting data in the EEPROM through I ² C.

Figure 1 illustrates the reading procedure of the timing controller through I ² C to the EEPROM. The timing controller provides SCL to EEPROM. Cooperating with the timing of SCL, the timing controller sends a read request to the EEPROM via the SDA line. After receiving the read request, the EEPROM cooperates with the SCL timing provided by the timing controller, and returns the corresponding data to the timing controller via the SDA line.

Please refer to Figure 1, the timing controller sends a start signal (start signal) S to the EEPROM via the SDA line, so that the EEPROM enters the state of receiving the control byte (control byte). The timing controller then sends the control byte containing the identification code and read and write instructions to the EEPROM. Suppose the identification code of the EEPROM is 001, and the timing controller wants to write the target address into the EEPROM, so the timing controller will send the control byte with the content "1010 001 0" to the EEPROM, and the last bit "0" is Indicates the "write" command. After completing the operation of receiving the control byte after 8 clock cycles, the EEPROM then sends back an acknowledgment signal ACK (ie logic 0) to the timing controller via the SDA line. After the timing controller receives the acknowledgment signal ACK, it writes the data (that is, the aforementioned target address) into the EEPROM via the SDA line. After completing the operation of receiving the target address after 8 clock cycles, the EEPROM then returns an acknowledgment signal ACK to the timing controller. So far, the timing controller has completed the operation of addressing the EEPROM.

The timing controller then sends a start signal S to the EEPROM via the SDA line, so that the EEPROM enters the state of receiving the control byte again. The sequence controller then sends the control byte to the EEPROM. Since the EEPROM needs to be read, the timing controller will transmit the control byte with the content of "1010 001 1" to the EEPROM, where the last bit "1" is an instruction for "reading". After completing the operation of receiving the control byte after 8 clock cycles, the EEPROM then returns the confirmation signal ACK to the timing controller via the SDA line, and then returns the previously addressed corresponding data to the timing controller after 8 clock cycles. After completing the data transmission, the EEPROM then transmits the signal NO_ACK to the timing controller via the SDA line. Finally, the timing controller sends a stop signal (stop signal) P to the EEPROM via the SDA line, so that the EEPROM enters the state of initialization (that is, the state of waiting to receive commands from the master component). So far, the timing controller has completed the reading procedure of the EEPROM.

However, in the above reading procedure, the timing controller may interrupt the reading of the EEPROM due to an abnormal glitch of the reset signal or other factors. When the timing controller re-reads the EEPROM, the EEPROM may stop in an uncontrollable state due to the abnormal interruption of the previous reading program, thus causing the timing controller to be unable to read again. Therefore, before the timing controller reads the EEPROM, it must first initialize the EEPROM.

Contents of the invention

The present invention provides a memory element initialization (initialize) method, which can restore the memory element to the initialization state no matter what operation state the memory element is in.

An embodiment of the present invention provides a method for initializing a memory element, including sending at least N+1 clock cycles to the memory element, where N is the number of serial data output bits of the memory element. During one of the at least N+1 clock cycles, a first OK signal is transmitted to the memory element. During another clock cycle of the at least N+1 clock cycles, a second OK signal is transmitted to the memory element.

In an embodiment of the present invention, except for the first start-stop signal and the second start-stop signal, no signal is transmitted to the memory element during the at least N+1 clock cycle periods.

In an embodiment of the present invention, the first start-end signal and the second start-end signal may be a start signal or a stop signal.

In an embodiment of the present invention, the above-mentioned time for transmitting the first start-stop signal is the first clock cycle in the at least N+1 clock cycles.

In an embodiment of the present invention, the interval between the first start-stop signal and the second start-stop signal is at least one clock period.

In an embodiment of the present invention, in addition to the first start-stop signal and the second start-stop signal, at least one third start-stop signal is transmitted to the memory element during the at least N+1 clock cycles.

Based on the above, the embodiment of the present invention transmits two or more start-stop signals to the memory element in at least N+1 clock cycles. Therefore, during the non-output data period of the memory element, the first start-stop signal will trigger the memory element to enter the initialization state. If the first start-stop signal conflicts with the acknowledgment signal sent back by the memory element, the second start-stop signal can be sent to the memory element with certainty, so that the memory element enters an initialization state. During the data output period of the memory element, although these start-stop signals transmitted to the memory element will conflict with the data output by the memory element, after supplying the memory element for at least N+1 clock cycles, it will prompt the memory element to end the output data period/state to enter the initialized state.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

Figure 1 illustrates the reading procedure of the timing controller through I ² C to the EEPROM.

FIG. 2 illustrates a method for initializing a memory element according to an embodiment of the present invention.

Detailed ways

FIG. 2 illustrates a method for initializing a memory element according to an embodiment of the present invention. The main component (such as the timing controller) accesses the memory component (such as EEPROM) through the two-wire transmission interface. The two-wire transmission interface (for example, I ² C bus) includes two lines of serial clock (SCL) and serial data (SDA). The master element provides the clock cycle to the memory element through the SCL line to synchronize the communication timing with each other. Cooperating with the timing of the SCL line, the main component transmits the start-stop signal, control byte, address data, etc. to the memory component through the SDA line. The memory element also cooperates with the timing of the SCL line, and transmits the confirmation signal, output serial data, etc. to the main element through the SDA line.

When the master device intends to initialize the memory device, the master device provides at least N+1 clock cycles to the memory device through the SCL line, where N is the number of serial data output by the memory device. Taking the reading program shown in FIG. 1 as an example, the number of bits of the output serial data of the memory element is 8 bits, so N can be set to be 8. According to this example, the master device provides at least 9 clock cycles to the memory device through the SCL line.

During this initialization period (during N+1 clock cycles), the main component selects two clock cycles in these clock cycles in accordance with the timing of the SCL line, and transmits the first start-stop signal SP1 and the second clock cycle through the SDA line during these two clock cycles. Two start and end signals SP2 are given to the memory element. The start-stop signals SP1 and SP2 can both be start signals S, or both be stop signals P. Alternatively, the first start-stop signal SP1 is a start signal S, and the second start-stop signal SP2 is a stop signal P.

In this embodiment, the master device transmits the start-stop signals SP1 and SP2 to the memory device in the first and third clock cycles of the clock cycles, respectively. During this initialization (N+1 clock cycles), the master can transmit any signal (such as a logic 0 signal or a logic 1 signal) except the start-stop signal SP1 and SP2. In this embodiment, except for the start-stop signals SP1 and SP2, the master device does not send signals to the memory device during these clock cycles.

The transmission time points of the start-stop signals SP1 and SP2 are not limited to those shown in FIG. 2 . The start-stop signals SP1 and SP2 may be transmitted to the memory element during any two clock cycles of these N+1 clock cycles. The start-stop signals SP1 and SP2 can be continuous, that is, there is no time interval between them. Alternatively, the start-stop signals SP1 and SP2 are separated by one or more clock periods.

If the memory element is abnormally interrupted during the non-output data period NOP (such as shown in Figure 1), since the master control of the SDA line belongs to the master element, the master element can use the first start signal SP1 (such as the stop signal P) to make The memory element enters an initialized state (ie, a state waiting to receive a command from the master element). Although the control right of the SDA line belongs to the master element during the non-output data period NOP, the memory element still needs to return an acknowledgment signal ACK (such as shown in FIG. 1 ) to the master element through the SDA line during this period. If the first start-stop signal SP1 conflicts with the acknowledgment signal ACK returned by the memory element, then the second start-stop signal SP2 (such as the stop signal P) must be transmitted to the memory element with certainty. That is to say, even if the initialization of the first start-stop signal SP1 fails, the second start-stop signal SP2 must make the memory element enter the initialization state (ie, the state of waiting to receive a command from the master element).

Those who apply this embodiment can determine the number of start-stop signals during the initialization (N+1 clock cycles) according to their design requirements. For example, in addition to the first start-stop signal SP1 and the second start-stop signal SP2, at least one third start-stop signal (such as a stop signal P, not shown) is also transmitted to the memory during the plurality of clock cycles element.

If the memory element is abnormally interrupted during the data output period OP (such as shown in Figure 1), since the master control of the SDA line belongs to the memory element during this period, the start and end signals SP1 and SP2 transmitted by the master element will be consistent with the output of the memory element. Conflict. That is to say, during the data output period OP, the master device cannot transmit the start-stop signal to the memory device, and of course the OP cannot enter the memory device into an initialized state during the data output period. Therefore, the master element can prompt the memory element to complete the output of N-bit data through the SCK line for more than N clock cycles. After the memory element completes the output of N-bit data, naturally, the memory element will end the data output period/state and enter the initialization state (that is, the state of waiting to receive the command from the master element, please refer to the description of FIG. 1 ). Next, the master device can normally access the memory device, such as performing the read procedure shown in FIG. 1 .

To sum up, no matter what operation state the memory element is in, the memory element can be effectively returned to the initialization state after the initialization method of the memory element is completed. Therefore, after the above N+1 clock cycles for initialization are over, the master element can start to normally access the memory element.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many modifications and variations without departing from the spirit and scope of the present invention, so the protection scope of the present invention The appended claims shall prevail.

Claims (12)

1. the initial method of a memory component comprises:

If the output serial data of described memory component is the N position, then transmit at least N+1 clock period to described memory component;

Select a clock cycle in the clock period at described N+1 at least, transmit first the beginning and the end signal and give described memory component; And

Select another clock period at described N+1 at least in the clock period, transmit second the beginning and the end signal and give described memory component.

2. the initial method of memory component as claimed in claim 1, wherein, during the described clock period of N+1 at least in, except that described first the beginning and the end signal and described second the beginning and the end signal, do not transmit signal and give described memory component.

3. the initial method of memory component as claimed in claim 1, wherein, described first the beginning and the end signal and described second the beginning and the end signal are start signal.

4. the initial method of memory component as claimed in claim 1, wherein, described first the beginning and the end signal and described second the beginning and the end signal are stop signal.

5. the initial method of memory component as claimed in claim 1, wherein, described first the beginning and the end signal is a start signal, and described second the beginning and the end signal is a stop signal.

6. the initial method of memory component as claimed in claim 1 wherein, transmits the time of described first the beginning and the end signal, is in described N+1 at least first clock period in the clock period.

7. the initial method of memory component as claimed in claim 1, wherein, described first the beginning and the end signal and described second at least one clock period in the beginning and the end sigtnal interval.

8. the initial method of memory component as claimed in claim 1 also comprises:

Except that described first the beginning and the end signal and described second the beginning and the end signal, also transmit at least one the 3rd the beginning and the end signal in the clock period at described N+1 at least and give described memory component.

9. the initial method of memory component as claimed in claim 8, wherein, described the 3rd the beginning and the end signal is a stop signal.

10. the initial method of memory component as claimed in claim 1 wherein, after described N+1 at least clock period finishes, begins the described memory component of access.

11. the initial method of memory component as claimed in claim 1, wherein, described memory component receives described a plurality of clock period, described first the beginning and the end signal and described second the beginning and the end signal by the TW two wire transmission interface.

12. the initial method of memory component as claimed in claim 11, wherein, described TW two wire transmission interface is I ²C.

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