CN102087312A

CN102087312A - Automatically controlled peak detector for signal

Info

Publication number: CN102087312A
Application number: CN 201010561875
Authority: CN
Inventors: 王颖; 高松松; 嵇凤丽
Original assignee: Harbin Engineering University
Current assignee: Harbin Engineering University
Priority date: 2010-11-29
Filing date: 2010-11-29
Publication date: 2011-06-08

Abstract

The invention provides an automatically controlled peak detector for a signal. The automatically controlled peak detector comprises a PD (peak detector) circuit (11), a peak discrimination circuit (14), an ADC (analogue-to-digital converter) (12) and a rear end processor (13), wherein one path of an input signal passes through the PD circuit (11), and then a peak voltage is output to an analogue voltage input end of the ADC (12); the other path of the input signal is connected with a negative end of a comparator (42) through a differentiating circuit and compared with zero voltage to output pulse which controls the ADC (12) and the rear end processor (13) to generate a reset signal for the PD circuit (11) and the ADC (12); and after conversion is finished, an EOC end of the ADC (12) outputs a high level to control the processor (13) to read data. According to the invention, automatic trigger control of the input signal is realized so that the input signal is applicable to the application occasions with relatively large waveform width and quick ADC conversion, restriction on the high-speed ADC is eliminated, and the dead time of signal acquisition of a system is reduced.

Description

A kind of signal is controlled peak detctor automatically

Technical field

What the present invention relates to is a kind of peak detctor.Relate to application of differential specifically and cross two edge control peak detctors that zero balancing is screened.

Background technology

In nuclear radiation detector, (analog-to-digital converter ADC) collects the peak signal that peak detctor is exported accurately and effectively, and the peak value discriminator has played crucial effects in order to make analog to digital converter.In order to allow the nuclear radiation detector performance obtain good performance, the peak value discriminator need satisfy: 1, for convenience ADC accurately gathers peak information, needs the peak value discriminator accurately to judge input signal peak value time of arrival; 2,, need the peak value discriminator adopting the error logging that can not occur under the situation of high-speed ADC to peak information in order to reduce the dead time of total system.

(the Caccic S of research before, Bertuccio G.IEEE Transactions on Nuclear Science, 2007,54 (3): the peak value discriminator of 538-540.) mentioning is by relatively peak value detection and holding circuit (peak detector, PD) input and output voltage is determined the detection peak due in, as shown in Figure 3, input signal one tunnel is output voltage comparer 61 anodes in ADC32 analog voltage input and the peak value discriminator 34 behind PD circuit 31, another road is comparer 61 negative terminals in peak value discriminator 34, compare with PD circuit 31 output voltages, output pulse control ADC32) ADC32 exports high level processor controls 33 reading of data by the EOC end after conversion is finished, the output reset signal was given PD circuit 31 and ADC32 after processor 33 was finished data read, detected so that carry out the follow-up signal peak value.For fear of because the leakage meter that the randomness of pulse signal causes, wrong meter, just must limit the application of high-speed ADC like this to the consideration of compromising of the slewing rate of ADC.People such as Qiu Yingyu are leakage and the accumulation of energy effects that utilizes electric capacity at " based on the spectrometry circuit of MCU radon chamber data acquisition system (DAS) " and the yellow peak value discriminator of mentioning in " a kind of development of GPS nuclear spectrum measurement instrument " such as understanding and considerate, allow input signal and self time delayed signal make comparisons to determine the peak value due in, as shown in Figure 2, input signal one tunnel behind PD circuit 21 output voltage to the ADC22 analog voltage input, the delay circuit 51 of another road in peak value discriminator 24 received comparer 52 anodes, compare output pulse control ADC22 with the input signal of comparer 52 negative terminals.By EOC end output high level processor controls 23 reading of data, the output reset signal was given PD circuit 21 and ADC22 to ADC22 after processor 23 was finished data read after conversion is finished.But because reset signal is to trigger after processor is received data, the influence of follow-up input signal at random also can cause the mistake meter phenomenon of total system.More than two kinds of peak detection circuits, though adopted different peak values to screen way, all adopted the way that after Data Receiving is finished, resets immediately, when adopting fast A C, just cause the mistake meter phenomenon of data so easily, as Fig. 5, shown in Figure 6, limited the application of high-speed ADC.

Summary of the invention

The object of the present invention is to provide a kind ofly can reduce the unimodal data-switching time of system, improve the ADC slewing rate, the signal that the wrong meter of data error can not occur is controlled peak detctor automatically.

The object of the present invention is achieved like this:

Comprise PD circuit 11, peak value discriminator circuit 14, ADC12, back-end processor 13; Input signal one tunnel is exported crest voltage to the ADC12 analog voltage input behind PD circuit 11, comparer 42 negative terminals are received through differentiating circuit 41 in another road of input signal, compare with no-voltage, output pulse control ADC12 and back-end processor 13 produce reset signal and give PD circuit 11 and ADC12; ADC12 exports high level processor controls 13 reading of data by the EOC end after conversion is finished.

Peak value discriminator circuit 14 of the present invention can improve the precision of discriminator circuit 14 detection peak due ins by optimal design differentiating circuit 41 and comparer 42 inner parameters.

The present invention has designed a kind of improved discriminator circuit, adopt differential to cross the method for zero balancing, unipolar signal is configured as double polarity pulse signal, utilize the two of output rect.p. to start and circuit reset along control ADC, realize that input signal triggers control automatically, make it be applicable to that the waveform width is big, the fast application scenario of ADC conversion rate, eliminated restriction, reduce the dead time of system acquisition signal high-speed ADC.

Description of drawings

Fig. 1 is that application of differential of the present invention is crossed the peak detection system synoptic diagram that zero balancing is screened;

Fig. 2 uses the peak detection system synoptic diagram that signal lag is relatively screened;

Fig. 3 uses the peak detection system synoptic diagram that the PD input and output voltage is relatively screened;

Fig. 4 is that application of differential of the present invention is crossed the peak detection system simulation result that zero balancing is screened;

Fig. 5 uses the peak detection system simulation result that signal lag is relatively screened;

Fig. 6 uses the peak detection system simulation result that the PD input and output voltage is relatively screened.

Embodiment

For example the present invention is done more detailed description below in conjunction with accompanying drawing:

In conjunction with Fig. 1, the peak detctor of using this peak value discriminator circuit comprises PD circuit 11, peak value discriminator circuit 14, ADC12, back-end processor 13 4 parts.Input signal one tunnel is exported crest voltage to the ADC12 analog voltage input behind PD circuit 11, comparer 42 negative terminals are received through differentiating circuit 41 in another road, compare with no-voltage, output pulse control ADC12 and negative edge trigger processor 13 and produce reset signal to PD circuit 11 and ADC12.ADC12 exports high level processor controls 13 reading of data by the EOC end after conversion is finished.

Among Fig. 1, Fig. 2, Fig. 3 except that discriminator circuit other circuit tool identical, 3 systems all error in omission can occur under slow ADC situation, compare checking at this under to the situation that adopts high-speed ADC.

With reference to Fig. 1, application of differential of the present invention is crossed the peak detctor that zero balancing is screened.Comprise peak value detect with holding circuit (peak detector, PD) 11, peak value discriminator circuit 14, ADC12, back-end processor 13 4 parts.Its feature is crossed zero balancing with input differential signal, utilizes the rising edge of a pulse that produces to trigger ADC12, and negative edge triggers back-end processor 13 and produces reset signal, realizes two along triggering control.

With reference to Fig. 4-Fig. 6, cross peak detection system that zero balancing screens and use peak detection system that signal lag relatively screens, use the simulation result of peak detection system under the situation that adopts same transitions speed ADC that the PD input and output voltage relatively screens as seen by application of differential of the present invention, the wrong meter of data error can not appear in peak detection system of the present invention when adopting high-speed ADC, eliminated the restriction of system to high-speed ADC, improve the unimodal data-switching speed of total system, avoided the error in omission that causes because of ADC.

Peak value discriminator inner structure parameter provided by the invention is not breaking away from the spirit and scope of the invention, can do a little adjustment and optimization, and protection scope of the present invention is as the criterion with claim.

Claims

1. a signal is controlled peak detctor automatically, comprises PD circuit (11), peak value discriminator circuit (14), ADC (12), back-end processor (13); It is characterized in that: input signal one tunnel is exported crest voltage to ADC (12) analog voltage input behind PD circuit (11), comparer (42) negative terminal is received through differentiating circuit (41) in another road of input signal, compare with no-voltage, output pulse control ADC (12) and back-end processor (13) produce reset signal and give PD circuit (11) and ADC (12); ADC (12) exports high level processor controls (13) reading of data by the EOC end after conversion is finished.