CN102082156A - Solid-state imaging device, method of manufacturing the same, and electronic apparatus - Google Patents
Solid-state imaging device, method of manufacturing the same, and electronic apparatus Download PDFInfo
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- CN102082156A CN102082156A CN2010105532196A CN201010553219A CN102082156A CN 102082156 A CN102082156 A CN 102082156A CN 2010105532196 A CN2010105532196 A CN 2010105532196A CN 201010553219 A CN201010553219 A CN 201010553219A CN 102082156 A CN102082156 A CN 102082156A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/10—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths
- H04N23/12—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths with one sensor only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The solid-state imaging device comprises a semiconductor layer, an insulating material in an opening penetrating a surface of the semiconductor layer, and a protective film that is resistant to etching covering one end of the insulating material on an interior side of the semiconductor layer. The method of manufacturing the solid-state imaging device includes the steps of forming an opening which penetrates a semiconductor layer, filling the opening with an insulating material, and forming a protective film that is resistant to etching at one end of the opening on an interior side of the semiconductor layer. According to the invention, a solid-state imaging device with high reliability without increasing the number of processes can be obtained. In addition, an electronic apparatus using the solid-state imaging device can also be obtained.
Description
The data of related application
The application requires the priority of on November 30th, 2009 to the Japanese patent application JP2009-272442 of Japan Patent office submission, incorporates this paper by reference at this full content with this Japanese patent application.
Technical field
The electronic installation that the present invention relates to a kind of solid photographic device, makes the method for this solid photographic device and use this solid photographic device.
Background technology
Solid photographic device roughly can be divided into charge coupled device (Charge Coupled Device, CCD) type solid photographic device and CMOS (Complementary Metal Oxide Semiconductor) (Complementary MetalOxide Semiconductor, CMOS) type solid photographic device.
In such solid photographic device, the photographic department that is formed by photodiode is formed in each pixel, and in this photographic department, thereby produce signal charge by opto-electronic conversion by the light that is incident to photographic department.In CCD type solid photographic device, the signal charge that is produced by photographic department is transmitted and enters into the charge transfer unit with CCD structure, and the pixel electric charge is converted into the picture element signal that is output as output signal.On the other hand, in CMOS type solid photographic device, the signal charge that is produced by photographic department is exaggerated in each pixel and institute's amplifying signal is output to holding wire as picture element signal.
Because the photodiode and the distance between the light incident surface that are formed on the substrate will be reduced to improve convergence efficient, therefore proposed a kind of like this backside illumination solid picture pick-up device, it is used to make light from the opposite rear side incident of that side with being formed with wiring layer of substrate.In this backside illumination solid picture pick-up device, after forming wiring layer on the face side of the substrate that is formed with photodiode or pixel transistor, substrate overturn, and forming lens on color-filter layer and the sheet on the rear side of substrate.In this backside illumination solid picture pick-up device, because will be with substrate overturn and subsequently lens shaped on color-filter layer or the sheet is formed on the rear side of substrate, therefore necessary alignment mask when being formed with on the rear side of substrate that lens position on to color-filter layer or sheet.In addition, in this backside illumination solid picture pick-up device,, formed from the substrate back side and to allow electrode pad form the opening that expose in the zone for the electrode pad that will be formed in the wiring layer on the substrate front side side forms the rear side that the zone is wired to substrate.In order to connect outside wiring from the substrate back side, formed electrode pad has been formed the opening that comes out in the zone.
Japanese Patent Application Publication communique spy opens and has illustrated for 2005-150463 number overleaf and form the method for alignment mask and the method for the pad contact site that formation is connected with electrode pad in the illumination solid picture pick-up device.Open in 2005-150463 number Japanese Patent Application Publication communique spy; in order to form alignment mask or in order to ensure the insulating properties between pad contact site and substrate; put down in writing a kind of like this structure: in this structure; after in substrate, forming opening, for example imbed insulating material such as SiO to form insulating barrier.
The manufacturing process of the backside illumination solid picture pick-up device of correlation technique is described with reference to Figure 25 A to Figure 25 C below.Figure 25 A to Figure 25 C shows the manufacturing process of the backside illumination solid picture pick-up device under alignment mask and situation about being formed by SiO round the insulating barrier of electrode pad portion.
At first, shown in Figure 25 A, adopt silicon-on-insulator (silicon-on-insulator, SOI) substrate 103 is (in this SOI substrate 103, imbedding oxidation film (BOX layer 101) and silicon layer 102 is formed on the silicon substrate 100 successively), form the pixel that includes photodiode PD in the pre-position of the pixel region 108 of silicon layer 102.Subsequently, on the surface of silicon layer 102, form after the oxidation film 104, form zone 107 and electrode pad at alignment mask and form to form in the zone 106 and pass the opening that silicon layer 102 arrives BOX layers 101.Then, imbed the insulating material that forms by SiO to form insulating barrier 105.
Then, on the surface of oxidation film 104, form a plurality of wiring layers 109 (interlayer dielectric 110 is mediate) thus form multiple wiring layer 111.
Then, on multiple wiring layer 111, form supporting substrate (not shown), the resulting member that overturns, and grind off the silicon substrate 110 and the BOX layer 101 of SOI substrate 103.Then, form in 105 region surrounded of insulating barrier in 106 of zone and form opening being formed at electrode pad, thereby expose electrode pad 112.Use is formed at alignment mask and forms the insulating barrier 105 of zone in 107 as alignment mask, is forming lens 113 on color-filter layer 114 and the sheet on the silicon layer 102 of pixel region 108.So the backside illumination solid picture pick-up device is accomplished.
Yet, in the manufacture method of correlation technique, when etching and remove silicon substrate 100 and during BOX layer 101, also can be etched by alignment mask 105a or insulating barrier 105 that SiO makes.So shown in Figure 25 C, alignment mask 105a or electrode pad form the insulating barrier 105 in zone and are excessively removed to the position darker than the surface of silicon layer 102.Because alignment mask 105a is by over etching and remove, so observability becomes bad.Alignment mask 105a being formed outstandingly so that improve under the situation of observability, in alignment mask 105a, use the insulating material different with SiO from the rear side of silicon layer 102.
Alignment mask 105a or be formed on the opening that electrode pad forms in 106 the insulating barrier 105 of zone and have high relatively aspect ratio.Therefore, when using SiO, be difficult to this opening of landfill as the material imbedded in this opening.As shown in figure 26, produced space 120.
The above problem that has been produced when having used SiO in order to solve in alignment mask 105a can use silicon nitride SiN as the insulating material of imbedding in the above-mentioned opening.In this case, in the operation of Figure 25 A, shown in Figure 27 A, after being formed for the opening of alignment mask, the insulating material that is formed by SiN is imbedded in this opening.
In the manufacturing process of this solid photographic device, after the operation of imbedding the insulating material 116 that becomes alignment mask 105a, for example, be used to remove the operation of the insulating material 116 on oxidation film 104.For example, shown in Figure 27 B, using hot phosphoric acid to remove under the situation of the insulating material that is formed by SiN 116 unnecessary on the oxidation film 104, should forming alignment mask 105a or electrode pad, to form the top of SiN of regional 106 insulating barrier 105 etched and remove.So, formed uneven by shown in the regional a on the top of this insulating barrier.
Having formed under the rough situation, shown in Figure 28 A, for example, polysilicon 118 is deposited on the insulating barrier 105 that is deteriorated.In this case, will be short-circuited between polysilicon 118 and the silicon layer 102.So, form in the zone 106 at electrode pad, can't guarantee silicon layer 102 and be connected in insulation between the contact layout (not shown) of electrode pad 112.Shown in Figure 28 B, in operation subsequently, silicon dioxide film 117 is formed under the situation on the insulating barrier 105 that is deteriorated, the silicon dioxide film 117 on the rough insulating barrier 105 can come off.In this case, can cause wafer contamination or device contamination.
Even being formed by silicon dioxide under the situation of insulating barrier 105, when removing unnecessary silicon dioxide, the silicon dioxide that constitutes this insulating barrier top also may be removed.Even in this case, the problem of Figure 28 A or Figure 28 B also can take place.
Summary of the invention
The invention provides a kind of solid photographic device, this solid photographic device has the insulating barrier of high reliability and can not increase the operation quantity that is used to make this solid photographic device.In addition, the invention provides a kind of electronic installation that uses this solid photographic device.
One embodiment of the present of invention relate to a kind of solid photographic device, and it comprises semiconductor layer, insulating material and diaphragm; Described insulating material is in the opening that penetrates described semiconductor layer; Described diaphragm has elching resistant, and is covered with an end of the described semiconductor layer of being positioned at of described insulating material inboard.
In the solid photographic device of another embodiment of foundation present embodiment, described semiconductor layer is provided with pixel region.
In the solid photographic device of another embodiment of foundation present embodiment, wherein said opening is arranged in the alignment area of described semiconductor layer, and described semiconductor layer is provided with the element separation zone between described alignment area and described pixel region.
In the solid photographic device of another embodiment of foundation present embodiment, wherein said diaphragm is arranged in the groove of described semiconductor layer, and described groove is at the place, described end of described opening.
In the solid photographic device of another embodiment of foundation present embodiment, also comprise: the impurity diffusion layer in described element separation zone; And be formed at dielectric film on the described diffusion layer.
In the solid photographic device of another embodiment of foundation present embodiment, also comprise: be carried on the multiple wiring layer on the described semiconductor layer; Outside the described pixel region of described semiconductor layer, be positioned at the electrode pad of described multiple wiring layer; And the electrode pad opening that passes described semiconductor layer and described multiple wiring layer and described electrode pad is exposed.
In the solid photographic device of another embodiment of foundation present embodiment, also comprise: a plurality of photodiodes in the described semiconductor layer in described pixel region.
In the solid photographic device of another embodiment of foundation present embodiment, also comprise: lens on the sheet above the described photodiode of each in described pixel region.
In the solid photographic device of another embodiment of foundation present embodiment, also comprise: each the described colour filter of going up between lens and each the described photodiode.
In the solid photographic device of another embodiment of foundation present embodiment, also comprise described insulating material and the described diaphragm made by identical materials.
In the solid photographic device of another embodiment of foundation present embodiment, wherein said insulating material contains silicon nitride.
Another embodiment of the present invention relates to a kind of solid-state imaging device manufacturing method, and it comprises the steps: to form the opening that penetrates semiconductor layer; With the described opening of filling insulating material; And the place, an end in the described semiconductor layer of being positioned at of described opening inboard forms the diaphragm with elching resistant.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment, wherein said semiconductor layer is provided with pixel region.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment, wherein said opening is formed in the alignment area of described semiconductor layer, and described semiconductor layer is provided with the element separation zone between described alignment area and described pixel region.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment; also comprise the steps: to form groove in described semiconductor layer before the step that forms described diaphragm, described groove is in the place, described end of the described semiconductor layer of being positioned at of described opening inboard.In this method, the step that forms described diaphragm comprises: form dielectric film in described groove.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment, also comprise the steps: in described element separation zone, to form impurity diffusion layer; And on described diffusion layer, form dielectric film.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment, also comprise the steps: on described semiconductor layer, to form multiple wiring layer; Outside the described pixel region of described semiconductor layer, in described multiple wiring layer, form electrode pad; And in described semiconductor layer, form the electrode pad opening that described electrode pad is exposed.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment, also comprise the steps: to form in the described semiconductor layer in described pixel region a plurality of photodiodes.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment, also comprise the steps: to form lens on the sheet above each the described photodiode in described pixel region.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment, also comprise the steps: between lens on each described and each described photodiode, to form colour filter.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment, wherein said insulating material and described diaphragm are made by identical materials.
In the solid-state imaging device manufacturing method of another embodiment of foundation present embodiment, wherein on described insulating material, form described diaphragm after etching so that described insulating material is kept intact.
Another embodiment of the present invention relates to a kind of electronic installation, and it comprises optical lens and semiconductor device.This semiconductor device is arranged at the front of described optical lens, and comprises: (1) semiconductor layer; (2) insulating material, it is in the opening that penetrates described semiconductor layer; And (3) diaphragm, it has elching resistant, and is covered with an end of the described semiconductor layer of being positioned at of described insulating material inboard.
In the electronic installation of foundation an alternative embodiment of the invention, wherein said semiconductor layer is provided with pixel region.
In the electronic installation of foundation an alternative embodiment of the invention, wherein said opening is arranged in the alignment area of described semiconductor layer, and described semiconductor layer is provided with the element separation zone between described alignment area and described pixel region.
In the electronic installation of foundation an alternative embodiment of the invention, wherein said diaphragm is arranged in the groove of described semiconductor layer, and described groove is in the place, described end of the described semiconductor layer of being positioned at of described insulating material inboard.
In the electronic installation of foundation an alternative embodiment of the invention, also comprise: the impurity diffusion layer in described element separation zone; And the dielectric film on described diffusion layer.
In the electronic installation of foundation an alternative embodiment of the invention, also comprise: the multiple wiring layer on described semiconductor layer; Outside the described pixel region of described semiconductor layer, be positioned at the electrode pad of described multiple wiring layer; And the electrode pad opening that passes described semiconductor layer and described multiple wiring layer and described electrode pad is exposed.
In the electronic installation of foundation an alternative embodiment of the invention, also comprise: a plurality of photodiodes in the described semiconductor layer in the described pixel region.
In the electronic installation of foundation an alternative embodiment of the invention, also comprise: lens on the sheet of the described photodiode of each in described pixel region top.
In the electronic installation of foundation an alternative embodiment of the invention, also comprise: each the described colour filter of going up between lens and each the described photodiode.
In the electronic installation of foundation an alternative embodiment of the invention, wherein said insulating material and described diaphragm are made by identical materials.
In the electronic installation of foundation an alternative embodiment of the invention, wherein said insulating material contains silicon nitride.
In the electronic installation of foundation an alternative embodiment of the invention, also comprise: the shutter device between described optical lens and described solid photographic device.
According to embodiments of the invention, can under the prerequisite that can not increase operation quantity, obtain solid photographic device with high reliability.In addition, can obtain to use the electronic installation of this solid photographic device.
Description of drawings
The accompanying drawing that is incorporated in the application's text and constitutes the part of the application's text illustrates embodiments of the present invention, and is used from explanation advantage of the present invention and principle with specification one.In the accompanying drawing:
Fig. 1 shows the schematic diagram of the structure of solid photographic device of the present invention;
Fig. 2 shows the schematic sectional view of solid photographic device of the present invention;
Fig. 3 A to Fig. 3 C shows the figure of solid-state imaging device manufacturing method of the present invention;
Fig. 4 D to Fig. 4 F shows the figure of solid-state imaging device manufacturing method of the present invention;
Fig. 5 G to Fig. 5 I shows the figure of solid-state imaging device manufacturing method of the present invention;
Fig. 6 A to Fig. 6 C shows the figure of solid-state imaging device manufacturing method of the present invention;
Fig. 7 D to Fig. 7 E shows the figure of solid-state imaging device manufacturing method of the present invention;
The electrode pad that Fig. 8 shows solid photographic device of the present invention forms regional schematic sectional view;
Fig. 9 A to Fig. 9 C shows the figure of solid-state imaging device manufacturing method of the present invention;
Figure 10 A to Figure 10 C shows the figure of solid-state imaging device manufacturing method of the present invention;
Figure 11 D to Figure 11 E shows the figure of solid-state imaging device manufacturing method of the present invention;
The electrode pad that Figure 12 shows solid photographic device of the present invention forms regional schematic sectional view;
Figure 13 A to Figure 13 C shows the figure of solid-state imaging device manufacturing method of the present invention;
Figure 14 D to Figure 14 F shows the figure of solid-state imaging device manufacturing method of the present invention;
Figure 15 G to Figure 15 I shows the figure of solid-state imaging device manufacturing method of the present invention;
Figure 16 J to Figure 16 K shows the figure of solid-state imaging device manufacturing method of the present invention;
Figure 17 A to Figure 17 C shows the figure of solid-state imaging device manufacturing method of the present invention;
Figure 18 D to Figure 18 E shows the figure of solid-state imaging device manufacturing method of the present invention;
The electrode pad that Figure 19 shows solid photographic device of the present invention forms regional schematic sectional view;
Figure 20 A to Figure 20 C shows the figure of solid-state imaging device manufacturing method of the present invention;
Figure 21 A to Figure 21 C shows the figure of solid-state imaging device manufacturing method of the present invention;
Figure 22 D to Figure 22 E shows the figure of solid-state imaging device manufacturing method of the present invention;
The electrode pad that Figure 23 shows solid photographic device of the present invention forms regional schematic sectional view;
Figure 24 shows the schematic diagram of the structure of electronic installation of the present invention;
Figure 25 A to Figure 25 C shows the figure of the solid-state imaging device manufacturing method of correlation technique;
Figure 26 is the schematic diagram that is formed the situation of dielectric film in the solid-state imaging device manufacturing method of correlation technique by SiO;
Figure 27 A and Figure 27 B are the schematic diagrames that is formed the situation of dielectric film in the solid-state imaging device manufacturing method of correlation technique by SiN; And
Figure 28 A and Figure 28 B show the schematic diagram of the problem that produces in the dielectric film that the solid-state imaging device manufacturing method by correlation technique forms.
Embodiment
Though various embodiments of the present invention has been described in the literary composition, for a person skilled in the art, it is conspicuous having more embodiment and implementation within the scope of the invention.Therefore, except the instruction of appended claim and equivalent thereof, the present invention is unrestricted.
At first, with reference to Fig. 1 and Fig. 2 the CMOS type solid photographic device 1 of the embodiment of the invention is described.The solid photographic device of following first to fourth embodiment of the present invention has adopted the structure of Fig. 1 and Fig. 2 jointly.In the present embodiment, will the rear surface irradiation type CMOS type solid photographic device as this solid photographic device be described.
Fig. 1 shows the integrally-built schematic diagram of the CMOS type solid photographic device 1 of the embodiment of the invention.
The solid photographic device 1 of present embodiment comprises pixel region 3, vertical drive circuit 4, column signal treatment circuit 5, horizontal drive circuit 6, output circuit 7 and control circuit 8 etc.In pixel region 3, on the substrate 11 that forms by silicon, be furnished with a plurality of pixels.
Each pixel 2 comprises the photographic department that is formed by photodiode and a plurality of pixel transistor, and a plurality of pixel 2 is arranged on the substrate 11 regularly in the mode of two-dimensional array.The described a plurality of pixel transistors that constitute pixel 2 can comprise for example transmission transistor, reset transistor, selection transistor, these four pixel transistors of amplifier transistor, perhaps can comprise three transistors except selecting transistor.
Column signal treatment circuit 5 and each row pixel 2 corresponding setting, so that the signal from the pixel corresponding with delegation 2 outputs in each pixel column is carried out for example signal processing such as noise removing, signal amplification according to signal from black benchmark pixel zone (though not shown, it is formed at around the effective pixel area).Horizontal selector switch (not shown) is arranged between the output stage and horizontal signal lines 10 of column signal treatment circuit 5.
7 pairs of signals that provide from each column signal treatment circuit 5 successively via horizontal signal lines 10 of output circuit carry out signal processing and export treated signal.
Fig. 2 shows the schematic sectional view of major part of the solid photographic device of present embodiment.As shown in Figure 2, the solid photographic device 1 of present embodiment comprises that in the neighboring area of pixel region 3 alignment mask 27 and electrode pad form zone 34, this alignment mask 27 is used for positioning during fabrication, and this electrode pad forms to be formed with in the zone 34 and is used for and the outside electrode pad 25 that connects up and be connected.
Backside illumination solid picture pick-up device 1 comprises: be formed with semiconductor layer 20 in it, be formed on the multiple wiring layer 21 on semiconductor layer 20 face side and be formed on color-filter layer 32 on semiconductor layer 20 rear side as each photodiode PD of photo-electric conversion element and sheet on lens 33.In addition, on the surface of that surface opposite of semiconductor layer 20, be formed with supporting substrate 22 with it at multiple wiring layer 21.
In the pixel region 3 of semiconductor layer 20, be formed with a plurality of photodiode PD that are used to constitute each pixel, and though not shown, the pixel transistor that is used to drive pixel 2 forms near each pixel.
Each color-filter layer 32 is formed in the zone corresponding with each pixel on the rear side as the rayed side of semiconductor layer 20, and is formed by the organic material that comprises redness (R) pigment, green (G) pigment and blueness (B) pigment.Lens 33 are formed on each color-filter layer 32 corresponding with each pixel by organic material on each sheet.On each sheet in the lens 33, thereby incident light is assembled and is incident to the photodiode PD that constitutes the pixel 2 corresponding with lens on this sheet effectively.
Electrode pad in the neighboring area that is formed at semiconductor layer 20 forms in the zone 34, has opening 26 to be formed in semiconductor layer 20 and the interlayer dielectric 24, makes electrode pad 25 in the part be formed at wiring 23 towards the rear side of semiconductor layer 20.Be formed with insulating barrier 28 round this opening 26 in semiconductor layer 20 sides, and insulating barrier 28 protected film 31 on the face side of semiconductor layer 20 is covered with.
That is to say; in the solid photographic device 1 of present embodiment, similarly be covered with as the insulating barrier 29 of alignment mask 27 and the insulating barrier 28 protected respectively film 30 and 31 on the face side of semiconductor layer 20 that forms in the mode that forms the opening 26 in the zone 34 round electrode pad.
Among each embodiment below, will to the insulating barrier 28 of backside illumination solid picture pick-up device 1 and 29 and the diaphragm 30 and 31 that is covered with insulating barrier 28 and 29 be elaborated.
The solid-state imaging device manufacturing method of first embodiment of the invention is described below with reference to Fig. 3 A to Fig. 9 C.The manufacturing process of Fig. 3 A to Fig. 5 I is the operation that is used to form alignment mask 27, and will be illustrated concurrently with the operation that is used in that pixel region 3 forms the operation of element separation portions and is used for forming at peripheral circuit area element separation portion.In the present embodiment, as the element separation portion of pixel region 3, be provided with such element separation portion and (hereinafter be called expansion photodiode area (the Expanding photodiode area Designed forIsolation that designs for isolation; EDI)), it comprises: be formed at the impurity diffusion layer in the semiconductor layer; And be formed on dielectric film (oxidation film) on this semiconductor layer with predetermined thickness.As the element separation portion of peripheral circuit area, be provided with such element separation portion and (hereinafter be called shallow trench isolation from (ShallowTrench Isolation; STI)): in this element separation portion, be formed with dielectric film in the groove in being formed at semiconductor layer.In the following description, with the zone that is formed with STI in it be called STI form the zone 36, and with the region description that is formed with EDI in it be EDI form the zone 37.
As shown in Figure 3A, prepare SOI substrate 40, in this SOI substrate 40, on the substrate of making by silicon 39, form the semiconductor layer 20 of imbedding oxidation film (hereinafter being called BOX layer 38) and forming successively by silicon.Then, on semiconductor layer 20, form silicon dioxide film 43 and photoresist film 44 successively.As shown in Figure 3A, form in the photoresist film 44 of zone in 35 at alignment mask and form opening.
Then, shown in Fig. 3 B, use photoresist film 44 to come etch silicon dioxide film 43, the opening that semiconductor layer 20 is exposed with formation as mask.Use the silicon dioxide film 43 that is formed with this opening in it as the hard mask that is used for etching semiconductor layer 20.
Then, shown in Fig. 3 C, use the hard mask that forms by silicon dioxide film 43 to come etching semiconductor layer 20 to form opening 45 to form at alignment mask in the zone 35.At this moment, silicon dioxide film 43 also has been thinned.Opening 45 forms to such an extent that penetrate semiconductor layer 20.For example, opening 45 forms to such an extent that have the 70nm width and 3 μ m degree of depth.
Then, shown in Fig. 4 D, will form to such an extent that imbed in the opening 45 by the insulating barrier 46 that silicon nitride (SiN) forms, and this insulating barrier 46 be formed on the whole surface of semiconductor layer 20.Therefore, form in the zone 35, in opening 45, formed insulating barrier 29, thereby formed alignment mask 27 at alignment mask.
Though the operation in the present embodiment is to enter subsequent processing under silicon dioxide film 43 and insulating barrier 46 are formed at state on the semiconductor film 20, the some time may be removed insulating barrier 46 and the silicon dioxide film 43 on the semiconductor layer 20.In this case, on the semiconductor layer 20 of having removed insulating barrier 46 and silicon dioxide film 43, form new silicon dioxide film and the insulating barrier that forms by SiN, and operation enters subsequent processing.
Then, shown in Fig. 4 E, on the insulating barrier 46 that is formed on the semiconductor layer 20, form photoresist film 47, in this photoresist film 47, form zone 35, STI at alignment mask and form the desired locations place that zone 36 and EDI form zone 37 and be formed with a plurality of openings 48.Use photoresist film 47 to come etching and remove insulating barrier 46 and silicon dioxide film 43 on the semiconductor layer 20 as mask.In this case, the opening 48 that forms in the zone 35 at alignment mask of photoresist film 47 has comprised the zone that is formed with insulating barrier 29 in it, and this opening 48 is to form like this: become this opening than the regional wide zone that is formed with insulating barrier 29 in it.Therefore, the upper area that exposes insulating barrier 29.
Then, remove the photoresist film 47 that in operation before, uses, shown in Fig. 4 F, form new photoresist film 49.In photoresist film 49, form zone 35 and STI at alignment mask and form the zone and form opening in 36, do not form opening and form in the zone 37 at EDI.That is to say, form in the zone 37, (be also included within on the semiconductor layer 20 that has exposed) formation photoresist film 49 on the whole surface of insulating barrier 46 at EDI.Subsequently, use photoresist film 49 to come etching and remove semiconductor layer 20 as hard mask, thereby form groove 50a and 50b to desired depth as mask and use insulating barrier 46.The groove 50b that forms in the zone 36 at STI becomes the groove that is used to constitute STI.The groove 50a that forms in the zone 35 at alignment mask is the groove that will form diaphragm 30 in subsequent handling thereon.Form in the zone 35 at alignment mask, etching is also removed the semiconductor layer 20 that surrounds insulating barrier 29 to forming the identical degree of depth of the groove 50b in zone 36 (for example approximately the degree of depth of 300nm) with STI, and insulating barrier 29 also can be etched and remove.Yet because the difference of rate of etch, this insulating barrier 29 is held at the upside place of semiconductor layer 20 bottoms.That is to say that insulating barrier 29 is not etched to the downside of semiconductor layer 20.
After forming groove 50a and 50b, the surperficial intermediate ion that forms the semiconductor layer 20 in zone 37 to EDI injects required impurity, thereby is formed for constituting the impurity diffusion layer 56 of EDI.
Then, remove the photoresist film 49 that on insulating barrier 46, forms, and shown in Fig. 5 G, form the dielectric film 51 that forms by SiO on groove 50a in comprising semiconductor layer 20 and the insulating barrier 46 of 50b.Therefore, form in the zone 35 at alignment mask, the top of the alignment mask 27 that is formed by insulating barrier 29 is insulated film 51 and is covered with.Form in the zone 36 at STI, dielectric film 51 is formed among the groove 50b as groove.Form in the zone 37 at EDI, dielectric film 51 forms and is formed with within it on the semiconductor 20 of impurity diffusion layer 56.
Then, shown in Fig. 5 H, use for example cmp (Chemical MechanicalPolishing; CMP) method is removed the dielectric film 51 that formed by SiO till the insulating barrier that is formed by SiN 46 that exposes on the semiconductor layer 20.That is to say that in the operation of grinding dielectric film 51, the insulating barrier 46 that is formed by SiN is used as stop layer.
Subsequently, shown in Fig. 5 I, the insulating barrier 46 that uses hot phosphoric acid to remove to have exposed.Therefore, form in the zone 35 at alignment mask, the diaphragm 30 that is formed by dielectric film 51 as the top of the insulating barrier 29 of alignment mask 27 is covered with.Form the STI 52 that has formed in the zone 36 as element separation portion at STI, and form the EDI 53 that has formed in the zone 37 as element separation portion at EDI.The thickness of the dielectric film 51 of the thickness of formed diaphragm 30 or formation EDI 53 is with the consistency of thickness that is formed on the insulating barrier 46 on the silicon dioxide film 43.For the thickness of the dielectric film 51 of the thickness that makes diaphragm 30 or EDI53 remains on about 100nm, the thickness that is formed at the insulating barrier 46 on the silicon dioxide film 43 is preferably about 100nm.
In the solid photographic device of present embodiment; the groove 50a that forms simultaneously with the groove 50b that constitutes STI 52 is formed in the semiconductor layer 20 that comprises as the top of the insulating barrier 29 of alignment mask 27, and diaphragm 30 is to form in the same operation when being formed for constituting the dielectric film 51 of STI 52.By covering insulating barriers 29 with diaphragm 30, the insulating barrier 29 that can prevent to be used for to constitute alignment mask 27 in etching and the process of removing the insulating barrier 46 that constitutes by SiN do not needed the ground etching.
As a comparative example, below with reference to Fig. 6 A to Fig. 6 C and Fig. 7 D to Fig. 7 E, the method for using correlation technique is described by the situation that the insulating barrier 29 that is formed by SiN forms alignment mask 68.Even in comparative example, also can be to being used for forming operation that zone 35 forms alignment masks 68, being used for forming zone 36 and forming the operation of STI and be used for forming the operations that zone 37 forms EDI and illustrate concurrently at EDI at STI at alignment mask.In Fig. 6 A to Fig. 6 C and Fig. 7 D to Fig. 7 E, represent by identical Reference numeral with the each several part that those parts among Fig. 3 A to Fig. 5 I are corresponding, and omit description of them.
Fig. 6 A is the corresponding figure of next step operation with Fig. 4 D of present embodiment, and the operation before Fig. 6 A is identical with the operation of Fig. 3 A to Fig. 3 C and Fig. 4 D, omits description of them.
As shown in Figure 6A, after forming insulating barrier 46, on the insulating barrier 46 that is formed on the semiconductor layer 20, form photoresist film 54, in this photoresist film 54, form the desired locations place that zone 36 and EDI form zone 37 at STI and be formed with opening 55.That is to say, form in the zone 35 at alignment mask and do not form opening.Use photoresist film 54 to come etching and remove insulating barrier 46 and silicon dioxide film 43 on the semiconductor layer 20 as mask.
Then, remove employed photoresist film 54 in operation before, and shown in Fig. 6 B, form new photoresist film 57.In photoresist film 57, form that the zone is formed with opening in 36 and form zone 35 and EDI at alignment mask and form in the zone 37 and do not form opening at STI.That is to say, form photoresist film 57 (be also included within alignment mask form on the zone 35 and form on the semiconductor layer that has exposed 20 of zone in 37) on the whole surface of insulating barrier 46 at EDI.Subsequently, use photoresist film 57 is as mask and use insulating barrier 46 as hard mask, thereby comes etching and remove semiconductor layer 20 to desired depth to form groove 58.Groove 58 becomes and is used for constituting the groove that STI forms the STI in zone 36.
After forming groove 58, the surperficial intermediate ion that forms the semiconductor layer 20 in zone 37 to EDI injects required impurity, thereby is formed for constituting the impurity diffusion layer 56 of EDI.
Then, remove the photoresist film 57 that is formed on the insulating barrier 46, and shown in Fig. 6 C, on insulating barrier 46, (be also included within on the groove 58 in the semiconductor layer 20) and form the dielectric film 59 that forms by SiO.
Then shown in Fig. 7 D, the dielectric film 59 that uses CMP method for example to remove to be formed by SiO is till the insulating barrier that is formed by SiN 46 that exposes on the semiconductor layer 20.
Then, shown in Fig. 7 E, use hot phosphoric acid to remove insulating barrier 46.Therefore, form in the zone 36, thereby dielectric film 59 is embedded in the STI 52 that forms to the groove 58 as element separation portion at STI.Form in the zone 37 at EDI, dielectric film 59 is formed on the semiconductor layer 20 that is formed with impurity diffusion layer 56 in it, thereby forms the EDI 53 as element separation portion.
Yet in such comparative example, when removing the insulating barrier 46 that is formed by SiN, the insulating barrier 29 that is used for constituting alignment mask 68 can form zone 35 at alignment mask and expose.Therefore, during insulating barrier 46 on removing semiconductor layer 20, the top (the regional Z by Fig. 7 E illustrates) of insulating barrier 29 that is used for constituting alignment mask 68 is simultaneously etched.Therefore, Figure 28 A and the illustrated problem of Figure 28 B have been produced.
In the solid photographic device of present embodiment, as mentioned above, be covered with insulating barrier 29 as alignment mask 27 by using diaphragm 30,27 the insulating barrier 29 that can prevent to be used to constitute alignment mask is removed with not needing.Therefore, can prevent the generation of the problem shown in Figure 28 A and Figure 28 B.
In the solid photographic device of present embodiment,, therefore can not increase the quantity of operation owing to can in the operation of making STI 52, form diaphragm 30 simultaneously.
Though illustrated in the description of Fig. 3 A to Fig. 5 I is the method that forms alignment mask 27, also can form insulating barrier 28 at the desired locations place that electrode pad forms the semiconductor layer 20 in the zone 34 by the method identical with the method that forms alignment mask 27.
Fig. 8 shows in the present embodiment and forms zone 35 forms the insulating barrier 28 that forms in the semiconductor layer 20 in zone 34 similarly at electrode pad figure with alignment mask.Form in the zone 34 at electrode pad, use the identical method of method with the formation alignment mask 27 of Fig. 3 A to Fig. 5 I, with formation insulating barrier 28 in semiconductor layer 20 accordingly round the zone that is formed at the electrode pad 25 in the multiple wiring layer 21.Electrode pad forms the periphery of the insulating barrier 28 of zone in 34 round the opening 26 that forms in subsequent handling, this opening 26 makes the rear side of electrode pad 25 towards semiconductor layer 20.Even form in the zone 34, also use and on insulating barrier 28, form diaphragm 31 in the identical method of the method for formation diaphragm 30 on the alignment mask 27 at electrode pad.
Fig. 9 A to Fig. 9 C shows in the solid-state imaging device manufacturing method of present embodiment, has formed photodiode PD, pixel transistor (not shown) and insulating barrier 28 and 29 manufacturing process afterwards in semiconductor layer 20.
Shown in Fig. 9 A, form the insulating barrier 28 in the zone 34 except forming alignment mask 27 or electrode pad, form photodiode PD, on the surface of semiconductor layer 20, form pixel transistor (not shown), on semiconductor layer 20, form multiple wiring layer 21 then.Multiple wiring layer 21 is by alternately forming interlayer dielectric 24 and required wiring 23 is formed.Form in the zone 34 at electrode pad, form electrode pad 25 by a wiring part of 23.
After forming multiple wiring layer 21 on the face side of semiconductor layer 20, supporting substrate 22 is adhered on the multiple wiring layer 21, and shown in Fig. 9 B, whole member is overturn.Subsequently, remove substrate 39 on the rear side of semiconductor layer 20 and BOX layer 38 till exposing semiconductor layer 20.
Then, shown in Fig. 9 C, electrode pad form the zone in 34 by 28 region surrounded of insulating barrier in form opening 26, thereby expose the electrode pad 25 that is formed in the multiple wiring layer 21.By using alignment mask 27 to position, forming lens 33 on required color-filter layer 32 and the sheet on the back side of semiconductor layer 20.
So the solid photographic device of present embodiment is accomplished.
In the solid photographic device of present embodiment, as the insulating barrier 29 of alignment mask 27 or be formed at electrode pad form insulating barrier 28 in the zone 34 can be not etched in manufacture process and remove.Therefore, improved output.Form in the zone 34 at electrode pad, even when the bonding wire that is connected with electrode pad 25 of formation in opening 26 etc., the insulation that also can keep this bonding wire or semiconductor layer 20.
As the insulating barrier 29 of alignment mask 27 or be formed at the insulating barrier 28 that electrode pad forms in the zone 34 and be formed in the opening that penetrates semiconductor layer 20 with high aspect ratio.Even in this case, the silicon nitride that has good imbedibility by use just can prevent the generation in space as insulating barrier 28 and 29.
By using silicon nitride to form insulating barrier 28 and 29, can prevent when the above-mentioned member and removing of overturning be used to constitute the substrate 39 of SOI substrate 40 and when imbedding the film formed BOX of oxide layer 38 insulating barrier 28 and 29 excessively removed.Therefore, insulating barrier 28 and 29 can be formed outstandingly to improve the observability of alignment mask 27 from the rear side of semiconductor layer 20.
In above-mentioned manufacture method; such example has been described: in this example, the diaphragm of alignment mask 27 30 and to be formed at diaphragm 31 that electrode pad forms the insulating barrier 28 in the zone 34 be to form in same operation with STI 52 as the element separation portion in the peripheral circuit area.As alternative scheme, the diaphragm of alignment mask 27 (insulating barrier 29) 30 and be formed at the diaphragm 31 that electrode pad forms the insulating barrier 28 in the zone 34 and can in same operation, form with EDI 53 as the element separation portion in the pixel region.To the example that side by side forms alignment mask and insulating barrier with EDI 53 be described below.
Below with reference to Figure 10 A to Figure 12 the solid-state imaging device manufacturing method of second embodiment of the invention is described.The manufacturing process of Figure 10 A to Figure 12 is the operation that is used to form alignment mask 27 that is similar to first embodiment, and will be illustrated concurrently with the operation that is used in peripheral circuit area formation element separation portion (STI) with the operation that is used in pixel region formation element separation portion (EDI).In Figure 10 A to Figure 12, represent by identical Reference numeral with the part that those parts among Fig. 3 A to Fig. 5 I and Fig. 8 are corresponding, and omit description of them.
Figure 10 A is the corresponding figure of Fig. 4 E with first embodiment.From the operation until Figure 10 A is identical with the operation of Fig. 3 A to Fig. 4 E before, and omitted description of them.
Shown in Figure 10 A, utilize photoresist film 47 to be etched in that alignment mask forms zone 35, STI forms zone 36 and EDI forms the insulating barrier 46 and the silicon dioxide film 43 at 37 desired locations place, zone, and remove photoresist film 47 subsequently.
Then, shown in Figure 10 B, form new photoresist film 49.In photoresist film 49, form the zone at STI and 36 be formed with opening, form zone 37 and do not form opening and form zone 35 and EDI at alignment mask.That is to say, form zone 35 and EDI forms in the zone 37, formed photoresist film 49 (being also included within on the semiconductor layer 20 that has exposed) on the whole surface of insulating barrier 46 at alignment mask.Subsequently, use photoresist film 49 as mask and use insulating barrier 46 as hard mask, thus etching and remove semiconductor layer 20 and form at STI to desired depth and form groove 50b in the zone 36.
After forming groove 50b, the surperficial intermediate ion that forms the semiconductor layer 20 in zone 37 to EDI injects required impurity, thereby is formed for constituting the impurity diffusion layer 56 of EDI.
Then, remove the photoresist film 49 that on insulating barrier 46, forms, and shown in Figure 10 C, on the whole surface of insulating barrier 46, (be also included within on the groove 50b) and form the dielectric film 51 that forms by SiO.Therefore, form in the zone 35 at alignment mask, the top of the alignment mask 27 that is formed by insulating barrier 29 is insulated film 51 and is covered with.Form in the zone 36 at STI, dielectric film 51 is formed among the groove 50b as groove.Form in the zone 37 at EDI, dielectric film 51 is formed on the semiconductor 20 that is formed with impurity diffusion layer 56 in it.
Then shown in Figure 11 D, the dielectric film 51 that uses CMP method for example to remove to be formed by silicon dioxide is till the insulating barrier that is formed by SiN 46 that exposes on the semiconductor layer 20.
Subsequently, shown in Figure 11 E, use hot phosphoric acid to come etching and remove the insulating barrier 46 that has exposed.Therefore, form in the zone 35 at alignment mask, the diaphragm 30 that is formed by dielectric film 51 as the top of the insulating barrier 29 of alignment mask 27 is covered with.Form the STI 52 that has formed in the zone 36 as element separation portion at STI, and form the EDI 53 that has formed in the zone 37 as element separation portion at EDI.
In the solid photographic device of present embodiment; form in the zone 35 at alignment mask; the diaphragm 30 that is formed by dielectric film 51 as the top of the insulating barrier 29 of alignment mask 27 is covered with, and this dielectric film 51 and being used for constitutes the dielectric film 51 of EDI 53 and forms in same operation.Therefore, in etching and remove in the operation of the insulating barrier 46 that is made of SiN, the insulating barrier 29 that can prevent to be used to constitute alignment mask 27 is not needed the ground etching.
Though illustrated in the description of Figure 10 A to Figure 11 E is the method that is used to form alignment mask 27, even but in the present embodiment, can form electrode pad by the method identical and form insulating barrier 28 in the zone 34 around opening 26 with the method that forms alignment mask 27.
Figure 12 shows with alignment mask and forms zone 35 forms the insulating barrier 28 that forms in the desired region in zone 34 similarly at electrode pad figure.Form in the zone 34 at electrode pad, similar with the operation of formation alignment mask 27 among Figure 10 A to Figure 11 E, and in semiconductor layer 20, form insulating barrier 28 accordingly round the zone that is formed at the electrode pad 25 in the multiple wiring layer 21.Electrode pad forms the periphery of the insulating barrier 28 of zone in 34 round the opening 26 that forms in subsequent handling, this opening 26 makes the rear side of electrode pad 25 towards semiconductor layer 20.Even form in the zone 34 at electrode pad, the similar method of method in the time of also can using with formation diaphragm 30 on alignment mask 27 forms diaphragm 31 on insulating barrier 28.
Finish the solid photographic device of present embodiment with the operation identical with Fig. 9 A to Fig. 9 C.These operations are identical with those operations among first embodiment, and omit description of them.
Present embodiment can obtain the effect identical with first embodiment.In the present embodiment, on as the insulating barrier 29 of alignment mask 27 and be formed at electrode pad and form the diaphragm 30 that forms respectively on the insulating barrier 28 in the zone 34 and 31 and can form simultaneously with the dielectric film 51 that is used to constitute EDI 53.Therefore, can under the prerequisite of the quantity that can not increase manufacturing process, form diaphragm 30 and 31.
Though in first and second embodiment, illustrated wherein by silicon nitride to form the example that insulating barrier 29 or electrode pad as alignment mask 27 form the insulating barrier 28 in the zone 34, the invention is not restricted to this.Below, will the configuration example different with the configuration among first and second embodiment that wherein forms the insulating barrier 28 in the zone 34 as the insulating barrier 29 of alignment mask 27 and electrode pad be described.
Below with reference to Figure 13 A to Figure 20 C the solid-state imaging device manufacturing method of third embodiment of the invention is described.The manufacturing process of Figure 13 A to Figure 15 I is the operation that is used to form alignment mask 27, and will be illustrated concurrently with the operation that is used in peripheral circuit area formation element separation portion (STI) with the operation that is used in pixel region formation element separation portion (EDI) similarly with first embodiment.In Figure 13 A to Figure 20 C, represent by identical Reference numeral with the each several part that those parts among Fig. 3 A to Fig. 9 C are corresponding, and omit description of them.
As shown in FIG. 13A, prepare SOI substrate 40, in this SOI substrate 40, imbed oxidation film (hereinafter being called BOX layer 38) and be formed on successively on the substrate of making by silicon 39 by the semiconductor layer 20 that silicon forms.Then, on semiconductor layer 20, form silicon dioxide film 43 and photoresist film 44 successively.As shown in FIG. 13A, form in the photoresist film 44 of zone in 35 at alignment mask and form opening.
Then, shown in Figure 13 B, use photoresist film 44 to come etch silicon dioxide film 43, thereby be formed for opening that semiconductor layer 20 is exposed as mask.Use the silicon dioxide film 43 that is formed with this opening in it as the hard mask that is used for etching semiconductor layer 20.
Then, shown in Figure 13 C, use the hard mask that forms by silicon dioxide film 43 to come etching semiconductor layer 20, thereby the formation alignment mask form the opening 45 in the zone 35.Opening 45 is formed to such an extent that penetrate semiconductor layer 20.At this moment, silicon dioxide film 43 also has been thinned.
Then, shown in Figure 14 D, first imbed film 60 forming on the sidewall of opening 45 and the bottom and on the whole surface at semiconductor layer 20 by what silicon nitride SiN formed.In Figure 14 D, the silicon nitride film 42 that in operation before, forms and in Figure 14 D, form first imbed film 60 and be described as identical layer.Subsequently, will second imbed film 69 and form to such an extent that imbed on its sidewall and bottom, being formed with first and imbed in the opening 45 of film 60, and second imbeds film 69 and is formed on and is formed at first on the semiconductor layer 20 and imbeds on the whole surface of film 60 by what polysilicon formed.
Then, shown in Figure 14 E, etching and remove first on the semiconductor layer 20 imbed on the film 60 form second imbed film 69 till first embedding layer 60 exposes.
Form in the zone 35 at alignment mask, first imbed film 60, so kept the insulation with semiconductor layer 20 owing on the sidewall of opening 45 and bottom, be formed with by what the insulating material silicon nitride formed.That is to say, be formed at first on the opening 45 and imbed film 60 and second and imbed the effect that film 69 has played insulating barrier 29.
Therefore, comprise by what the insulating material silicon nitride formed and first imbed film 60 and be formed at alignment mask and form on the opening of zone in 35, and therefore insulating barrier 29 becomes alignment mask 27 by second insulating barrier 29 of imbedding film 69 that polysilicon forms.
Then, shown in Figure 14 F, the termination film 61 that is formed by SiN is formed on comprises that being formed at first on the semiconductor layer 20 imbeds on the whole surface of film 60 and alignment mask 27.When grinding, stop film 61 and be used as stop layer by the CMP that in subsequent handling, uses.
Then, shown in Figure 15 G, on the termination film 61 that is formed on the semiconductor layer 20, form photoresist film 62, in this photoresist film 62, form zone 35, STI at alignment mask and form the desired locations place that zone 36 and EDI form zone 37 and be formed with opening 63.Then, use photoresist film 62 to come etching and the termination film 61, first removed on the semiconductor layer 20 is imbedded film 60 and silicon dioxide film 43 as mask.In this example, the opening 63 that alignment mask forms the photoresist film 62 in the zone 35 has comprised the zone that is formed with the insulating barrier 29 that becomes alignment mask 27 in it, and this opening 63 is to form like this: form this opening than the regional wide zone that is formed with insulating barrier 29 in it.Therefore, the upper area of insulating barrier 29 is exposed.
Then, remove the photoresist film 62 that in operation before, uses, and shown in Figure 15 H, form new photoresist film 64.In photoresist film 64, form zone 35 and STI at alignment mask and form the zone and be formed with opening in 36, do not form opening and form zone 37 at EDI.That is to say that form in the zone 37 at EDI, (being also included within on the semiconductor layer 20 that has exposed) formed photoresist film 64 on the whole surface that stops film 61.Subsequently, use photoresist film 64 as mask and use first to imbed film 60 and stop film 61 as hard mask, thus etching and remove semiconductor layer 20 to desired depth and form groove 65 and 66.The groove 66 that forms in the zone 36 at STI becomes the groove that is used to constitute STI.The groove 65 that forms in the zone 35 at alignment mask is the grooves that will form diaphragm 30 in the subsequent handling thereon.Form in the zone 35 at alignment mask, etching is also removed the semiconductor layer 20 that surrounds insulating barrier 29 to forming the identical degree of depth of groove 66 in zone 36 with STI, and insulating barrier 29 also can be etched and remove.Yet because the difference of rate of etch, this insulating barrier 29 is held at the upside place of semiconductor layer 20 bottoms.That is to say that insulating barrier 29 is not etched to the downside of semiconductor layer 20.
After forming groove 65 and 66, the surperficial intermediate ion that forms the semiconductor layer 20 in zone 37 to EDI injects required impurity, thereby is formed for constituting the impurity diffusion layer 56 of EDI.
Then, remove the photoresist film 64 that forms on the film 61 stopping, and shown in Figure 15 I, stopping the dielectric film 67 that (being also included within on the groove 65 and 66 of semiconductor layer 20) formation is formed by SiO on the film 61.Therefore, form in the zone 35 at alignment mask, the top of the alignment mask 27 that is formed by insulating barrier 29 is insulated film 67 and is covered with.Form in the zone 36 at STI, dielectric film 67 is formed in the groove 66 as groove.Form in the zone 37 at EDI, dielectric film 67 forms and is formed with within it on the semiconductor 20 of impurity diffusion layer 56.
Then, shown in Figure 16 J, the dielectric film 67 that uses CMP method for example to remove to be formed by SiO is till the termination film 61 that is formed by SiN on the semiconductor layer 20 exposes.
Subsequently, shown in Figure 16 K, use hot phosphoric acid to remove termination film 61 and first and imbed film 60.Therefore, form in the zone 35 at alignment mask, the diaphragm 30 that is formed by dielectric film 67 as the top of the insulating barrier 29 of alignment mask 27 is covered with.Form the STI 52 that has formed in the zone 36 as element separation portion at STI, and form the EDI 53 that has formed in the zone 37 as element separation portion at EDI.The thickness of formed diaphragm 30 or be used to constitutes the thickness of dielectric film 67 of EDI 53 with being formed on the consistency of thickness that first on the silicon dioxide film 43 imbedded film 60 and stopped film 61.For the thickness of the dielectric film 67 of the thickness that makes diaphragm 30 or EDI 53 remains on about 100nm, be formed at the thickness that first on the silicon dioxide film 43 imbed film 60 and stop film 61 and be preferably about 100nm.
In the solid photographic device of present embodiment; form the zone at alignment mask and formed in 35 and be positioned at the groove 65 that the groove 66 with being used to constitute STI 52 on the insulating barrier 29 forms simultaneously, and in groove 65, formed the diaphragm 30 that forms simultaneously with the dielectric film 67 that is used to constitute STI 52.In etching and remove the termination film 61 and first that constitutes by SiN and imbed in the process of film 60, just can prevent to be used to constitute first the imbedding film 60 and do not needed the ground etching of insulating barrier 29 of alignment mask 27.
As a comparative example, with reference to Figure 17 A to Figure 18 D the method for using correlation technique is imbedded the situation that insulating barrier 29 that film 69 forms forms alignment mask 27 and described by imbedding film 60 and second by first below.Even in this comparative example, also will be to being used for forming operation that zone 35 forms alignment masks 27, being used for forming zone 36 and forming the operation of STI 52 and be used for forming the operations that zone 37 forms EDI 53 and illustrate concurrently at EDI at STI at alignment mask.In Figure 17 A to Figure 18 D, represent by identical Reference numeral with the each several part that those parts among Figure 13 A to Figure 16 K are corresponding, and omit description of them.
In this comparative example, shown in Figure 17 A, after form stopping film 61,, in this photoresist film 70, form the desired locations place that zone 36 and EDI form zone 37 at STI and be formed with opening 71 stopping forming photoresist film 70 on the film 61.That is to say, form in the zone 35 at alignment mask and do not form opening.Use photoresist film 70 comes etching as mask and removes first on the semiconductor layer 20 and imbed film 60, stop film 61 and silicon dioxide film 43.
Then, remove the photoresist film 70 that in operation before, uses, and shown in Figure 17 B, form new photoresist film 73.In photoresist film 73, form the zone at STI and be formed with opening in 36, form in the zone 37 and do not form opening and form zone 35 and EDI at alignment mask.That is to say, form photoresist film 73 stopping on the whole surface of film 61 (be also included within that alignment mask forms on the zone 35 and on EDI forms the semiconductor layer that has exposed 20 in the zone 37).Subsequently, use photoresist film 73 as mask and use first to imbed film 60 and stop film 61 as hard mask, thus etching and remove semiconductor layer 20 and form at STI to desired depth and form groove 66 in the zone 36.Groove 66 becomes the groove that is used to constitute STI.Subsequently, on forming the face side of zone 37 semiconductor layer 20, EDI is formed for constituting the impurity diffusion layer 56 of EDI.
Then, remove and be formed on the photoresist film 73 that stops on the film 61, and shown in Figure 17 C, (being also included within on the groove 66 that is formed in the semiconductor layer 20) forms the dielectric film 67 that is formed by SiO on stopping film 61.
Then shown in Figure 18 D, the dielectric film 67 that uses CMP method for example to remove to be formed by SiO is till the termination film 61 that is formed by SiN on the semiconductor layer 20 exposes.
Then, shown in Figure 18 E, the termination film 61 that uses hot phosphoric acid to remove to form and remove first and imbed film 60 by silicon nitride.Therefore, form in the zone 36, thereby dielectric film 67 is embedded in the STI 52 that forms to the groove 66 as element separation portion at STI.Form in the zone 37 at EDI, thereby dielectric film 67 forms the EDI 53 that forms on the semiconductor layer 20 that is formed with impurity diffusion layer 56 within it as element separation portion.
Yet, in such comparative example,, constitute first of alignment mask 27 and imbed film 60 and form in the zone 35 at alignment mask and expose when using hot phosphoric acid to remove to stop film 61 and first when imbedding film 60.Therefore, when the termination film 61 on removing semiconductor layer 20 and first was imbedded film 60, being used to constitute first of alignment mask 27, to imbed the top of film 60 (being illustrated by regional Z) simultaneously also etched.Therefore, produced the problem that illustrates with Figure 28 A and Figure 28 B.
In the solid photographic device of present embodiment, as mentioned above, be covered with insulating barrier 29 as alignment mask 27 by using diaphragm 30, the insulating barrier 29 that can prevent to be used to constitute alignment mask 27 is removed with not needing.Therefore, just can prevent the generation of the problem shown in Figure 28 A and Figure 28 B.
In the solid photographic device of present embodiment,, therefore do not increase the quantity of operation owing to can form diaphragm 30 simultaneously in the operation that is used for making STI 52.
Though what illustrate in the description of Figure 13 A to Figure 16 K is the method that is used to form alignment mask 27, also can forms electrode pad by the method identical and form the insulating barrier 28 around opening 26 of zone in 34 with the method that is used to form alignment mask 27.
Figure 19 shows in the present embodiment and is formed at alignment mask and forms insulating barrier 29 in the zone 35 similarly forms the insulating barrier 28 that forms in the desired region in zone 34 at electrode pad figure.Form in the zone 34 at electrode pad, use with Figure 13 A to Figure 16 K in be used to form the identical method of method of alignment mask 27, with formation insulating barrier 28 in semiconductor layer 20 accordingly round the zone that is formed at the electrode pad 25 in the multiple wiring layer 21.Electrode pad forms the periphery of the insulating barrier 28 of zone in 34 round the opening 26 that forms in subsequent handling, this opening 26 makes the rear side of electrode pad 25 towards semiconductor layer 20.Even form in the zone 34, also can use with the identical method of method and on insulating barrier 28, form diaphragm 31 at formation diaphragm 30 on the alignment mask 27 at electrode pad.
Figure 20 A to Figure 20 C shows in the solid-state imaging device manufacturing method of present embodiment, forms photodiode PD, pixel transistor (not shown) and insulating barrier 28 and 29 manufacturing process afterwards in semiconductor layer 20.
Shown in Figure 20 A, form the insulating barrier 28 in the zone 34 except forming alignment mask 27 or electrode pad, form photodiode PD, on the surface of semiconductor layer 20, form pixel transistor (not shown), on semiconductor layer 20, form multiple wiring layer 21 then.Multiple wiring layer 21 is by alternately forming interlayer dielectric 24 and required wiring 23 is formed.Form in the zone 34 at electrode pad, form electrode pad 25 by a wiring part of 23.
After forming multiple wiring layer 21 on the face side of semiconductor layer 20, supporting substrate 22 is adhered on the multiple wiring layer 21, and shown in Figure 20 B, whole member is overturn.Subsequently, remove substrate 39 on the rear side of semiconductor layer 20 and BOX layer 38 till exposing semiconductor layer 20.
Then, shown in Figure 20 C, electrode pad form the zone in 34 by 28 region surrounded of insulating barrier in form opening 26, thereby the electrode pad 25 that is formed in the multiple wiring layer 21 is exposed.By using alignment mask 27 to position, forming lens 33 on required color-filter layer 32 and the sheet on the back side of semiconductor layer 20.
So the solid photographic device of present embodiment is accomplished.
In the solid photographic device of present embodiment owing to formed diaphragm 30 and 31, therefore as the insulating barrier 29 of alignment mask 27 or be formed at electrode pad form insulating barrier 28 in the zone 34 can be not etched in manufacture process and remove.Therefore, kept insulating barrier 28 and 29 and semiconductor layer 20 between insulation.Therefore, form in the zone 34,, can not take place also that connect up in this outside or the short circuit of semiconductor layer 20 even when in opening 26, forming as the bonding wire of outside wiring etc. at electrode pad.
In the present embodiment, owing to used silicon nitride first to imbed film 60 to the opening 26, therefore can prevent the generation in space as imbedding with good imbedibility.In addition, form speed, therefore improved output owing to form the film of speed as second film of imbedding the polysilicon that film 69 is used faster than SiN.Forms by silicon nitride because first imbeds film 60, therefore when overturning above-mentioned member and remove the substrate 39 of formation SOI substrate 40 and during BOX layer 38, can prevent that insulating barrier 28 and 29 from excessively being removed.
In above-mentioned manufacture method, having described the diaphragm 30 of alignment mask 27 wherein and being formed at diaphragm 31 that electrode pad forms the insulating barrier 28 in the zone 34 is the examples that form in same operation with STI 52 as the element separation portion of peripheral circuit area.Alternative scheme is, the diaphragm 30 of alignment mask 27 (insulating barrier 29) and be formed at the diaphragm 31 that electrode pad forms the insulating barrier 28 in the zone 34 and can form in same operation with the EDI as the element separation portion of pixel region.To the example that side by side forms the diaphragm of the diaphragm of alignment mask and insulating barrier with EDI be described below.
Below with reference to Figure 21 A to Figure 23 the solid-state imaging device manufacturing method of fourth embodiment of the invention is described.The manufacturing process of Figure 21 A to Figure 23 is the operation that similarly is used to form alignment mask 27 with first to the 3rd embodiment, and will be illustrated concurrently with the operation that is used in peripheral circuit area formation element separation portion (STI) with the operation that is used in pixel region formation element separation portion (EDI).In Figure 21 A to Figure 23, represent by identical Reference numeral with the each several part that those parts among Figure 13 A to Figure 16 K are corresponding, and omit description of them.
From before up to the operation of Figure 21 A and the 3rd embodiment the operation of Figure 13 A to Figure 15 G similar, and omit description of them.
Shown in Figure 21 A, utilize photoresist film 62 to remove the silicon dioxide film 43 at desired locations place, first and imbed film 60 and stop film 61, and remove photoresist film 62 subsequently.
Then, shown in Figure 21 B, form new photoresist film 77.In photoresist film 77, form the zone at STI and 36 be formed with opening, form zone 37 and do not form opening and form zone 35 and EDI at alignment mask.That is to say, form zone 35 and EDI forms in the zone 37 at alignment mask, (being also included within on the semiconductor layer 20 that has exposed) forms photoresist film 77 on the whole surface of film 61 stopping.Subsequently, use photoresist film 77 as mask and use first to imbed film 60 and stop film 61 as hard mask, thus etching and remove semiconductor layer 20 and form at STI to desired depth and form groove 66 in the zone 36.
After forming groove 66, the surperficial intermediate ion that forms the semiconductor layer in zone 37 to EDI injects required impurity, thereby is formed for constituting the impurity diffusion layer 56 of EDI.
Then, remove the photoresist film 77 that forms on the film 61 stopping, and shown in Figure 21 C, on the groove 66 of semiconductor layer 20 or says and stopping the dielectric film 67 that (being also included within on the semiconductor layer 20) formation is formed by SiO on the film 61.Therefore, form in the zone 35 at alignment mask, the diaphragm 30 that the top of the alignment mask 27 that is formed by insulating barrier 29 quilt is formed by dielectric film 67 is covered with.Form in the zone 36 at STI, dielectric film 67 is formed in the groove 66 as groove.Form in the zone 37 at EDI, dielectric film 67 is formed on the semiconductor 20 that is formed with impurity diffusion layer 56 within it.
Then shown in Figure 22 D, the dielectric film 67 that uses CMP method for example to remove to be formed by SiO is till exposing the termination film 61 that is formed by SiN on the semiconductor layer 20.
Subsequently, shown in Figure 22 E, the termination film 61 that uses hot phosphoric acid to remove to form and remove first and imbed film 60 by silicon nitride.Therefore, form in the zones, be covered with as the protected film 30 in top of the insulating barrier 29 of alignment mask 27 at alignment mask 27.Form the STI 52 that has formed in the zone 36 as element separation portion at STI, and form the EDI 53 that has formed in the zone 37 as element separation portion at EDI.
In the solid photographic device of present embodiment; form in the zone 35 at alignment mask; the diaphragm 30 that is formed by dielectric film 67 as the top of the insulating barrier 29 of alignment mask 27 is covered with, and this dielectric film 67 is to form in same operation with the dielectric film 67 that is used for constituting EDI 53.Therefore, in etching and remove the insulating barrier 46 and first that is made of SiN and imbed in the process of film 60, the insulating barrier 29 that can prevent to be used to constitute alignment mask 27 is not needed the ground etching.
Though what illustrate in the description of Figure 21 A to Figure 22 E is the method that is used to form alignment mask 27, even but in the present embodiment, also can form at electrode pad and form insulating barrier 28 in the zone 34 by the method identical with the method that is used to form alignment mask 27.
Figure 23 shows and is formed at alignment mask and forms the insulating barrier 29 of zone in 35 similarly forms the insulating barrier 28 that forms in the desired region in zone 34 at electrode pad figure.Form in the zone 34 at electrode pad, with the operation that is used to form alignment mask 27 among Figure 21 A to Figure 22 E side by side, and in semiconductor layer 20, form insulating barrier 28 accordingly round the zone that is formed at the electrode pad 25 in the multiple wiring layer 21.Electrode pad forms the periphery of the insulating barrier 28 of zone in 34 round the opening 26 that forms in subsequent handling, this opening 26 makes the rear side of electrode pad 25 towards semiconductor layer 20.
Even form in the zone 34, also can use with the identical method of method that is used at formation diaphragm 30 on the alignment mask 27 and on insulating barrier 28, form diaphragm 31 at electrode pad.
Finished the solid photographic device of present embodiment with the operation identical with Figure 20 A to Figure 20 C.These operations are identical with those operations among the 3rd embodiment, and omit description of them.
Present embodiment can obtain the identical effect with first to the 3rd embodiment.In the present embodiment, the diaphragm 30 that forms on as the insulating barrier 29 of alignment mask 27 and be formed at electrode pad and form the diaphragm 31 that forms on the insulating barrier 28 in the zone 34 and can form simultaneously with the dielectric film 67 that is used to constitute EDI 53.Therefore, can under the prerequisite of the quantity that can not increase manufacturing process, form diaphragm 30 and 31.
In first and second embodiment, the diaphragm that the insulating barrier that is formed by SiN is formed by SiO is covered with; In third and fourth embodiment, the diaphragm that the insulating barrier that is formed by polysilicon and SiN is formed by SiO is covered with.The invention is not restricted to these materials but can use various materials.That is to say, can use following any configuration: as long as in this configuration, thereby be formed at the protected film of insulating barrier in the semiconductor layer be covered with make in subsequent handling not can be etched with remove.Though the example that forms diaphragm in the forming process of STI or EDI simultaneously has been described in first to fourth embodiment, has the invention is not restricted to this.For example, diaphragm can form in as the forming process of the element separation portion of the groove of several nanometers simultaneously with Si.
If as the insulating barrier of alignment mask or to be formed at the dielectric film that electrode pad forms in the zone be to be formed by SiO, then can use polysilicon as diaphragm.Polysilicon can and be formed at gate electrode on the semiconductor layer (oxidation film of grid that is formed by SiO is between this semiconductor layer and this gate electrode) and forms simultaneously.Therefore; for example; even when being used to remove the operation of oxidation film of grid near the top of semiconductor layer (being formed with the insulating barrier of being made by SiO in it), the diaphragm that this insulating barrier is also formed by polysilicon is covered with, this insulating barrier can not removed with not needing.
As diaphragm, can use the film that after the formation operation of the insulating barrier of semiconductor layer, is formed on this semiconductor layer face side.For example, multiple choices such as SiON, SiC, SiOC, TiN, metal silicide (silicide), cobalt silicide, titanium silicide, nickle silicide or tungsten can be arranged.As insulating barrier, can use SiO, SiN or SiON etc.
Though in first to fourth embodiment, the solid-state imaging device manufacturing method that has used the SOI substrate is illustrated, the invention is not restricted to this, also gone for wherein using the structure of block substrate (bulk substrate) etc.
Though in first to fourth embodiment, rear surface irradiation type CMOS type solid photographic device is illustrated as an example, the invention is not restricted to rear surface irradiation type CMOS type solid photographic device, also go for front illuminated type solid photographic device.
In first to fourth embodiment, the situation that is applied to following CMOS type solid photographic device is illustrated: in this CMOS type solid photographic device, be used for arranging in the mode of matrix as the unit pixel that physical quantity detects in response to the signal charge of incident light quantity.Yet, the invention is not restricted to be applied to this CMOS type solid photographic device.The invention is not restricted to row type solid photographic device (in this row type solid photographic device, in each pixel column of pixel cell, be furnished with column circuits, have a plurality of pixels arranging in the mode of two-dimensional matrix on the whole in the described pixel cell).
The distribution of incident light quantity that the invention is not restricted to be used to detect and absorb visible light is with the solid photographic device as image, and the distribution of amount of incident that also goes for being used for absorbing infrared ray or X ray or particle is with the solid photographic device as image.In addition, the present invention can be applicable to all solids image devices such as for example fingerprint detection transducer that are used for detecting and absorb such as the distribution of other physical quantitys such as pressure or static capacity in a broad sense.
In addition, the invention is not restricted to be used for each unit pixel of behavior unit scanning element unit successively and from the solid photographic device of each unit pixel read pixel signal.The present invention go for being used for selecting in the pixel cell any pixel and from pixel cell the X-Y address type solid-state imaging device of selected pixel read output signal.In addition, solid photographic device of the present invention can form a chip or form by pixel cell, signal processing unit or optical system being encapsulated the module with camera function that obtains.
The invention is not restricted to solid photographic device, also go for camera head.Camera head is meant: camera system such as digital camera or video camera for example; Or for example mobile phone etc. has the electronic installation of camera function.The module (that is camera model) that is assemblied in the electronic installation can be a camera head.
Below, will the electronic installation of fifth embodiment of the invention be described.Figure 24 shows the schematic diagram of structure of the electronic installation 200 of fifth embodiment of the invention.
The electronic installation 200 of present embodiment is equivalent to such embodiment: among this embodiment, the solid photographic device 1 of first embodiment of the invention is used for this electronic installation (camera).
The electronic installation 200 of present embodiment comprises solid photographic device 1, optical lens 210, shutter device 211, drive circuit 212 and signal processing circuit 213.
The periodicity of illumination and the shading cycle of shutter device 211 control solid photographic devices 1.
In the electronic installation 200 of present embodiment,, therefore can obtain the electronic installation 200 that reliability is improved owing in solid photographic device 1, improved the insulating barrier 28 that is formed in the semiconductor layer 20 and 29 reliability.
But the electronic installation 200 of applying solid picture pick-up device 1 is not limited to camera, for example also goes for digital camera or is used in such as the camera heads such as camera model in the mobile devices such as mobile phone.
Though in the electronic installation of present embodiment, be to use solid photographic device 1, also can have used produced solid photographic device in second to the 4th embodiment.
It will be understood by those of skill in the art that according to designing requirement and other factors, can in the scope of the appended claim of the present invention or its equivalent, carry out various modifications, combination, inferior combination and change.
Claims (34)
1. solid photographic device, it comprises:
Semiconductor layer;
Insulating material, it is in the opening that penetrates described semiconductor layer; And
Diaphragm, it has elching resistant, and is covered with an end of the described semiconductor layer of being positioned at of described insulating material inboard.
2. solid photographic device according to claim 1, wherein said semiconductor layer is provided with pixel region.
3. solid photographic device according to claim 2, wherein:
Described opening is arranged in the alignment area of described semiconductor layer, and
Described semiconductor layer is provided with the element separation zone between described alignment area and described pixel region.
4. solid photographic device according to claim 3, wherein said diaphragm are arranged in the groove at the place, described end of described opening of described semiconductor layer.
5. solid photographic device according to claim 3 also comprises:
Impurity diffusion layer in described element separation zone; And
Be formed at the dielectric film on the described diffusion layer.
6. solid photographic device according to claim 2 also comprises:
Be carried on the multiple wiring layer on the described semiconductor layer;
Outside the described pixel region of described semiconductor layer, be positioned at the electrode pad of described multiple wiring layer; And
The electrode pad opening that passes described semiconductor layer and described multiple wiring layer and described electrode pad is exposed.
7. solid photographic device according to claim 3 also comprises: a plurality of photodiodes in the described semiconductor layer in described pixel region.
8. solid photographic device according to claim 7 also comprises lens on the sheet of the described photodiode of each that be positioned at described pixel region top.
9. solid photographic device according to claim 8 also comprises: each the described colour filter of going up between lens and each the described photodiode.
10. solid photographic device according to claim 4, wherein said insulating material and described diaphragm are made by identical materials.
11. solid photographic device according to claim 1, wherein said insulating material contains silicon nitride.
12. a solid-state imaging device manufacturing method, it comprises the steps:
Formation penetrates the opening of semiconductor layer;
With the described opening of filling insulating material; And
Place, an end in the described semiconductor layer of being positioned at of described opening inboard forms the diaphragm with elching resistant.
13. method according to claim 12, wherein said semiconductor layer is provided with pixel region.
14. method according to claim 12, wherein:
Described opening is formed in the alignment area of described semiconductor layer, and
Described semiconductor layer is provided with the element separation zone between described alignment area and described pixel region.
15. method according to claim 14 also comprises the steps:
Before the step that forms described diaphragm, in described semiconductor layer, form groove, described groove is in the place, described end of the described semiconductor layer of being positioned at of described opening inboard,
Wherein, the step that forms described diaphragm comprises: form dielectric film in described groove.
16. method according to claim 14 also comprises the steps:
In described element separation zone, form impurity diffusion layer; And
On described diffusion layer, form dielectric film.
17. method according to claim 13 also comprises the steps:
On described semiconductor layer, form multiple wiring layer;
Outside the described pixel region of described semiconductor layer, in described multiple wiring layer, form electrode pad; And
In described semiconductor layer, form the electrode pad opening that described electrode pad is exposed.
18. method according to claim 14 also comprises the steps: to form in the described semiconductor layer in described pixel region a plurality of photodiodes.
19. method according to claim 18 also comprises the steps: to form lens on the sheet above each the described photodiode in described pixel region.
20. method according to claim 19 also comprises the steps: to form colour filter between lens on each described and each described photodiode.
21. method according to claim 15, wherein said insulating material and described diaphragm are made by identical materials.
22. method according to claim 15 wherein forms described diaphragm, so that described insulating material is kept intact after etching on described insulating material.
23. an electronic installation, it comprises optical lens and semiconductor device,
Described semiconductor device is arranged at the front of described optical lens, and described semiconductor device comprises:
1) semiconductor layer;
2) insulating material, it is in the opening that penetrates described semiconductor layer; And
3) diaphragm, it has elching resistant, and is covered with an end of the described semiconductor layer of being positioned at of described insulating material inboard.
24. electronic installation according to claim 23, wherein said semiconductor layer is provided with pixel region.
25. electronic installation according to claim 24, wherein:
Described opening is arranged in the alignment area of described semiconductor layer, and
Described semiconductor layer is provided with the element separation zone between described alignment area and described pixel region.
26. electronic installation according to claim 25, wherein said diaphragm is arranged in the groove of described semiconductor layer, and described groove is in the place, described end of the described semiconductor layer of being positioned at of described insulating material inboard.
27. electronic installation according to claim 25 also comprises:
Impurity diffusion layer in described element separation zone; And
Dielectric film on described diffusion layer.
28. electronic installation according to claim 25 also comprises:
Multiple wiring layer on described semiconductor layer;
Outside the described pixel region of described semiconductor layer, be positioned at the electrode pad of described multiple wiring layer; And
The electrode pad opening that passes described semiconductor layer and described multiple wiring layer and described electrode pad is exposed.
29. electronic installation according to claim 25 also comprises: a plurality of photodiodes in the described semiconductor layer in described pixel region.
30. electronic installation according to claim 25 also comprises: lens on the sheet above the described photodiode of each in described pixel region.
31. electronic installation according to claim 25 also comprises: each the described colour filter of going up between lens and each the described photodiode.
32. electronic installation according to claim 26, wherein said insulating material and described diaphragm are made by identical materials.
33. electronic installation according to claim 23, wherein said insulating material contains silicon nitride.
34. electronic installation according to claim 23 also comprises: the shutter device between described optical lens and described solid photographic device.
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| JP2009272442A JP5568969B2 (en) | 2009-11-30 | 2009-11-30 | SOLID-STATE IMAGING DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
| JP2009-272442 | 2009-11-30 |
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| CN102082156A true CN102082156A (en) | 2011-06-01 |
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| US (1) | US9059062B2 (en) |
| JP (1) | JP5568969B2 (en) |
| KR (1) | KR101683300B1 (en) |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050104148A1 (en) * | 2003-11-17 | 2005-05-19 | Sony Corporation | Solid-state imaging device and method of manufacturing solid-state imaging device background of the invention |
| US20060197007A1 (en) * | 2005-03-07 | 2006-09-07 | Sony Corporation | Solid-state image pickup device, electronic apparatus using such solid-state image pickup device and method of manufacturing solid-state image pickup device |
| CN101106149A (en) * | 2006-07-10 | 2008-01-16 | 佳能株式会社 | Photoelectric conversion device and image pickup system with photoelectric conversion device |
| US20080081466A1 (en) * | 2006-09-28 | 2008-04-03 | Mie Matsuo | Method for Fabricating Semiconductor Device |
| US20080308890A1 (en) * | 2007-06-14 | 2008-12-18 | Shinji Uya | Back-illuminated type imaging device and fabrication method thereof |
| US20090140365A1 (en) * | 2007-10-05 | 2009-06-04 | Yun-Ki Lee | Image sensor with back-side illuminated photoelectric converters |
| CN101494234A (en) * | 2008-01-21 | 2009-07-29 | 索尼株式会社 | Solid-state imaging device, method of fabricating solid-state imaging device and camera |
| CN101582393A (en) * | 2008-05-12 | 2009-11-18 | 索尼株式会社 | Method of manufacturing a solid-state imaging device and method for manufacturing electronic apparatus |
| CN101834192A (en) * | 2009-03-11 | 2010-09-15 | 索尼公司 | Solid-state image pickup apparatus and manufacture method thereof |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6195542A (en) * | 1984-10-17 | 1986-05-14 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2002057318A (en) | 2000-08-07 | 2002-02-22 | Sony Corp | Solid-state image sensing element and its manufacturing method |
| JP2002208629A (en) * | 2000-11-09 | 2002-07-26 | Toshiba Corp | Semiconductor device and method for manufacturing the same |
| US6746966B1 (en) * | 2003-01-28 | 2004-06-08 | Taiwan Semiconductor Manufacturing Company | Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area |
| JP2005268738A (en) * | 2004-02-17 | 2005-09-29 | Sony Corp | Solid-state imaging device and its manufacturing method, and semiconductor integrated circuit device and its manufacturing method |
| US20060134881A1 (en) * | 2004-12-17 | 2006-06-22 | Been-Jon Woo | Method of forming trench isolation device capable of reducing corner recess |
| JP2008182142A (en) * | 2007-01-26 | 2008-08-07 | Sony Corp | Solid-state image sensor, method of manufacturing the same, and imaging device |
| US7588993B2 (en) * | 2007-12-06 | 2009-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment for backside illumination sensor |
| JP2009272596A (en) * | 2008-04-09 | 2009-11-19 | Sony Corp | Solid-state imaging device, method of manufacturing the same, and electronic instrument |
| JP2010003928A (en) * | 2008-06-20 | 2010-01-07 | Toshiba Corp | Solid-state image pickup device and method for manufacturing the same |
| JP5268618B2 (en) * | 2008-12-18 | 2013-08-21 | 株式会社東芝 | Semiconductor device |
| JP2010171038A (en) * | 2009-01-20 | 2010-08-05 | Toshiba Corp | Solid-state image pickup device and method of manufacturing the same |
| JP2010225818A (en) * | 2009-03-23 | 2010-10-07 | Toshiba Corp | Solid-state image pickup device and method for manufacturing the same |
-
2009
- 2009-11-30 JP JP2009272442A patent/JP5568969B2/en not_active Expired - Fee Related
-
2010
- 2010-10-29 TW TW099137331A patent/TWI445167B/en not_active IP Right Cessation
- 2010-11-09 KR KR1020100110831A patent/KR101683300B1/en active IP Right Grant
- 2010-11-12 US US12/945,169 patent/US9059062B2/en active Active
- 2010-11-22 CN CN2010105532196A patent/CN102082156B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050104148A1 (en) * | 2003-11-17 | 2005-05-19 | Sony Corporation | Solid-state imaging device and method of manufacturing solid-state imaging device background of the invention |
| US20060197007A1 (en) * | 2005-03-07 | 2006-09-07 | Sony Corporation | Solid-state image pickup device, electronic apparatus using such solid-state image pickup device and method of manufacturing solid-state image pickup device |
| CN101106149A (en) * | 2006-07-10 | 2008-01-16 | 佳能株式会社 | Photoelectric conversion device and image pickup system with photoelectric conversion device |
| US20080081466A1 (en) * | 2006-09-28 | 2008-04-03 | Mie Matsuo | Method for Fabricating Semiconductor Device |
| US20080308890A1 (en) * | 2007-06-14 | 2008-12-18 | Shinji Uya | Back-illuminated type imaging device and fabrication method thereof |
| US20090140365A1 (en) * | 2007-10-05 | 2009-06-04 | Yun-Ki Lee | Image sensor with back-side illuminated photoelectric converters |
| CN101494234A (en) * | 2008-01-21 | 2009-07-29 | 索尼株式会社 | Solid-state imaging device, method of fabricating solid-state imaging device and camera |
| CN101582393A (en) * | 2008-05-12 | 2009-11-18 | 索尼株式会社 | Method of manufacturing a solid-state imaging device and method for manufacturing electronic apparatus |
| CN101834192A (en) * | 2009-03-11 | 2010-09-15 | 索尼公司 | Solid-state image pickup apparatus and manufacture method thereof |
Cited By (11)
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|---|---|---|---|---|
| CN103579269A (en) * | 2012-07-27 | 2014-02-12 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN103681713A (en) * | 2012-09-14 | 2014-03-26 | 索尼公司 | Solid-state imaging deivce and electronic device |
| CN103681713B (en) * | 2012-09-14 | 2018-02-09 | 索尼公司 | Solid state image pickup device and electronic installation |
| CN107482024A (en) * | 2012-10-18 | 2017-12-15 | 索尼公司 | Solid camera head and electronic equipment |
| CN107482024B (en) * | 2012-10-18 | 2020-10-27 | 索尼公司 | Solid-state imaging device and electronic apparatus |
| CN107833902A (en) * | 2013-07-05 | 2018-03-23 | 索尼公司 | Solid state image pickup device, its manufacture method and electronic equipment |
| CN107833902B (en) * | 2013-07-05 | 2022-07-22 | 索尼公司 | Solid-state imaging device, method of manufacturing the same, and electronic apparatus |
| US11532762B2 (en) | 2013-07-05 | 2022-12-20 | Sony Corporation | Solid state imaging apparatus, production method thereof and electronic device |
| CN104882454A (en) * | 2014-02-28 | 2015-09-02 | 瑞萨电子株式会社 | Semiconductor device and a manufacturing method thereof |
| CN108370423A (en) * | 2016-01-18 | 2018-08-03 | 索尼公司 | Solid-state image pickup element and electronic equipment |
| CN108121933A (en) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101683300B1 (en) | 2016-12-06 |
| US20110127629A1 (en) | 2011-06-02 |
| US9059062B2 (en) | 2015-06-16 |
| TW201138083A (en) | 2011-11-01 |
| KR20110060802A (en) | 2011-06-08 |
| JP2011114325A (en) | 2011-06-09 |
| TWI445167B (en) | 2014-07-11 |
| JP5568969B2 (en) | 2014-08-13 |
| CN102082156B (en) | 2013-11-06 |
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