CN102075485A - Sampling clock synchronization method for orthogonal frequency division multiplexing (OFDM) system - Google Patents

Sampling clock synchronization method for orthogonal frequency division multiplexing (OFDM) system Download PDF

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CN102075485A
CN102075485A CN2011100218436A CN201110021843A CN102075485A CN 102075485 A CN102075485 A CN 102075485A CN 2011100218436 A CN2011100218436 A CN 2011100218436A CN 201110021843 A CN201110021843 A CN 201110021843A CN 102075485 A CN102075485 A CN 102075485A
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sampling clock
frequency deviation
clock frequency
deviation
ofdm
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徐娟娟
祝常健
牛丽仙
孙洪亮
林炀炀
任丽丽
邢增谋
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SHENZHEN APAISI INDUSTRY Co Ltd
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SHENZHEN APAISI INDUSTRY Co Ltd
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Abstract

The invention relates to a sampling clock synchronization method for an orthogonal frequency division multiplexing (OFDM) system, which aims at providing the sampling clock synchronization method with the advantages of high precision, simple algorithm and little expense. The method comprises the following steps of: firstly, using two training sequences to estimate sampling clock frequency deviation, then, realizing the sampling rate conversion through the sampling clock frequency deviation information by using a polynomial interpolation filter, correcting the sampling clock frequency deviation, and using few frequency-domain discrete pilot frequencies for correcting the phase deflexion caused by residue sampling clock deviation. When the technical scheme is adopted, the defect of influence on a system caused by the sampling clock frequency deviation can be completely overcome, and the goal of high-precision sampling clock synchronization is reached.

Description

A kind of ofdm system sampling clock method for synchronous
Technical field
The invention belongs to communication technical field, relate to method for synchronous, relate in particular to the clock synchronizing method of sampling in the ofdm system with high order modulation.
Background technology
OFDM(Orthogonal Frequency Division Multiplexing is an orthogonal frequency division multiplexi) in the system, because the transmitting-receiving two-end sampling clock is not quite identical, its sampling frequency deviation that causes may cause the problem of following two aspects: be to make the deflection of subcarrier generation phase place on the one hand, introduce inter-carrier interference (ICI) simultaneously, cause the snr loss; Cause slow symbol timing deviation on the other hand, it is inaccurate that FFT is windowed, and disturbs between created symbol (ISI).And for ofdm system with high order modulation such as 1024QAM, these systems are more responsive to sampling clock deviation, need the support of high-precision sampling clock synchronized algorithm.Using more at present, the common order of modulation of ofdm system only reaches 64QAM(such as 802.11a, 802.16, DVB etc.), so present sampling clock simultaneous techniques great majority are purpose with the demand that satisfies the 64QAM modulation, lack high-precision sampling clock synchronized algorithm.
Summary of the invention
The objective of the invention is to provide a kind of precision height, algorithm is simple, the sampling clock method for synchronous that expense is little, this method at first utilizes two training sequences to estimate sample clock frequency deviation, utilize the polynomial interopolation filter to realize the conversion of sample rate by sample clock frequency deviation information then, correct sample clock frequency deviation,, use a small amount of frequency domain scattered pilot that it is corrected for the phase place deflection that residual sampling clock deviation (less than 5ppm) causes.Use this programme can overcome sample clock frequency deviation fully, reach the purpose of sampling with high precision clock synchronization the influence that system causes.
The technical scheme that the present invention adopts in order to realize its technical purpose is: a kind of method for synchronous of ofdm system sampling clock may further comprise the steps:
Steps A, sample clock frequency deviation is estimated;
Step B, the sample clock frequency deviation that utilizes steps A to estimate carry out three rank cubic interpolation filter filtering to realize sample rate conversion, correct sample clock frequency deviation;
Step C, utilize a small amount of scattered pilot symbol that the phase place deflection that remaining sample clock frequency deviation causes is corrected.
Further, in the method for synchronous of above-mentioned a kind of ofdm system sampling clock: be to utilize two training sequences sample clock frequency deviation to be estimated in the described steps A by following method:
　　
In the formula:
Figure 56411DEST_PATH_IMAGE002
Be the symbol of training sequence on each subcarrier after FFT and the channel equalization of receiving,
Figure 24367DEST_PATH_IMAGE003
Be the frequency pilot sign on each subcarrier of training sequence correspondence, Be the OFDM notation index, owing to have only two training sequences, so
Figure 756404DEST_PATH_IMAGE004
Get 1 and 2,
Figure 887171DEST_PATH_IMAGE005
Be the subcarrier number index,
Figure 494870DEST_PATH_IMAGE006
, With
Figure 514965DEST_PATH_IMAGE008
Value be respectively
Figure 500238DEST_PATH_IMAGE009
Figure 278838DEST_PATH_IMAGE010
Wherein
Obtain
Figure 871811DEST_PATH_IMAGE012
After, by
Figure 180432DEST_PATH_IMAGE013
, obtain sampling clock deviation
Figure 379201DEST_PATH_IMAGE014
, obtain final sampling clock deviation
Figure 140484DEST_PATH_IMAGE015
, wherein
Figure 466423DEST_PATH_IMAGE016
,
Figure 160710DEST_PATH_IMAGE017
The length that is respectively FFT adds the protection gap length, the length of FFT.
Further, in the method for synchronous of above-mentioned a kind of ofdm system sampling clock: adopt following method that the phase place deflection that remaining sample clock frequency deviation causes is corrected among the described step C:
Figure 281112DEST_PATH_IMAGE018
In the formula
Figure 44538DEST_PATH_IMAGE019
Be phase deviation,
Figure 439747DEST_PATH_IMAGE020
Be the symbol after the process phase compensation.
The present invention has following effect:
The first, the present invention for the estimated service life of sampling clock deviation two training sequences (all being frequency pilot sign on all subcarriers), and it is averaged, improved estimated accuracy greatly.
The second, the present invention just carried out sampling clock deviation and estimates that estimated result is directly used in the subsequent treatment to data message, has avoided time delay influence before data symbol receives.
The 3rd, the present invention has not only carried out the sample clock frequency deviation correction, and the phase place deflection that remaining sample clock frequency deviation causes is compensated, and has high accuracy, can fully satisfy the needs of the ofdm system that has high order modulation.
Below in conjunction with description of drawings and embodiment, the present invention is described in further detail.
Description of drawings
Fig. 1 is the embodiment of the invention 1 flow chart.
Fig. 2 is the planisphere that adopts the method for synchronous acquisition of present ofdm system sampling clock.
Fig. 3 is the planisphere that adopts embodiment 1 method to obtain.
Embodiment
Embodiment 1, as shown in Figure 1: present embodiment adopts functional module as shown in Figure 1: the sample clock frequency deviation estimation module, and based on the sample rate conversion module of polynomial interopolation filter, phase compensation block.
The first step utilizes two training sequences sample clock frequency deviation to be estimated method of estimation is
Figure 457382DEST_PATH_IMAGE001
Wherein
Figure 14265DEST_PATH_IMAGE002
Be the symbol of training sequence on each subcarrier after FFT and the channel equalization of receiving, Be the frequency pilot sign on each subcarrier of training sequence correspondence,
Figure 683461DEST_PATH_IMAGE004
Be the OFDM notation index, owing to have only two training sequences, so
Figure 79238DEST_PATH_IMAGE004
Get 1 and 2, Be the subcarrier number index,
Figure 295772DEST_PATH_IMAGE006
, With
Figure 759432DEST_PATH_IMAGE008
Value be
Figure 641806DEST_PATH_IMAGE009
Figure 883431DEST_PATH_IMAGE010
Wherein
Figure 892976DEST_PATH_IMAGE011
Obtain
Figure 739709DEST_PATH_IMAGE012
After, by
Figure 340455DEST_PATH_IMAGE013
, obtain sampling clock deviation
Figure 272639DEST_PATH_IMAGE014
, obtain final sampling clock deviation
Figure 335141DEST_PATH_IMAGE015
, wherein
Figure 301960DEST_PATH_IMAGE016
,
Figure 808028DEST_PATH_IMAGE017
The length that is respectively FFT adds the protection gap length, the length of FFT.
Second step was utilized the sample clock frequency deviation that estimates
Figure 493087DEST_PATH_IMAGE021
Carry out three rank cubic interpolation filter filtering to realize sample rate conversion, correct sample clock frequency deviation.
This step is at list of references [1] F. M. Gardner, " Interpolation in Digital Modems Part-I:Fundamentals ", IEEE Trans. Comm., Vol. 41, No. 3, pp. 502-508, Mar. 1993. and list of references [2] L. Erup, F, M. Gardner, and F. A. Harris, " Interpolation in Digital Modems Part-Il:Fundamentals and Performance ", IEEE Trans.Comm., Vol. 41, No. 6, pp. 998-1008, have open in the method among the June. 1993.
The impulse response of filter For
Figure 196918DEST_PATH_IMAGE023
The crude sampling value is
Figure 591996DEST_PATH_IMAGE024
, be output as through interpolation filter
Figure 498772DEST_PATH_IMAGE025
, then
Wherein Be the integer index value,
Figure 443092DEST_PATH_IMAGE028
Be the decimal index value,
Figure 89361DEST_PATH_IMAGE029
Be the sampling period of transmitting-receiving two-end, the sample clock frequency deviation that estimates in its ratio available step one is obtained, promptly
Figure 782511DEST_PATH_IMAGE030
=1+
Figure 862779DEST_PATH_IMAGE032
Be Lagrangian coefficient, can from list of references [2], obtain.
The 3rd step utilized a small amount of scattered pilot symbol that the phase place deflection that remaining sample clock frequency deviation causes is corrected.
Obtain with reference to the method in the step 1
Figure 478568DEST_PATH_IMAGE033
,
Figure 506567DEST_PATH_IMAGE034
, wherein With Value according to the quantity of pilot tone, the symbol of modulating on place sub-carrier indices number and the pilot tone is determined.
Then
Figure 733969DEST_PATH_IMAGE036
Be phase deviation, Be the symbol after the process phase compensation.
In the above step, step 1 only need be located to carry out at first and second OFDM symbol (training sequence), and the data symbol of ensuing OFDM directly carries out the processing of step 2 and step 3 by the result that step 1 estimates.
Establish FFT length N=256 in the ofdm system below, the protection gap length is 16, Ns=272 then, and effectively the subcarrier number is 210, constellation mapping adopts 1024QAM to test.
The value of K is 105,
Figure 114321DEST_PATH_IMAGE038
Figure 704702DEST_PATH_IMAGE039
Value in the training sequence on each pilot tone
Figure 168362DEST_PATH_IMAGE041
,
Figure 965416DEST_PATH_IMAGE042
Can be self-defined.
Obtain by the calculating formula in the step 1
Figure 292361DEST_PATH_IMAGE043
,
Figure 669116DEST_PATH_IMAGE044
, and then
Figure 148639DEST_PATH_IMAGE045
?，
Figure 116595DEST_PATH_IMAGE046
?，
Figure 681568DEST_PATH_IMAGE047
Obtain and adopt
Figure 108352DEST_PATH_IMAGE048
The sample frequency deviation of clock
Figure 707961DEST_PATH_IMAGE031
, the method that provides according to step 2 calculates then
Figure 846818DEST_PATH_IMAGE030
Thereby, obtain
Figure 633508DEST_PATH_IMAGE049
,
Figure 617645DEST_PATH_IMAGE050
, through behind the interpolation filter by the crude sampling value
Figure 602918DEST_PATH_IMAGE048
Obtain new sampled value Carry out the phase compensation in the step 3 then, the pilot tone number of phase compensation is made as 8, A with
Figure 904773DEST_PATH_IMAGE008
Be defined as
Figure 958179DEST_PATH_IMAGE052
Obtain data-signal after the compensation by the calculating formula in the step 3.
Use planisphere of the present invention as shown in Figure 3, under 40DB white Gaussian noise environment, 1024QAM, use the comparison of the planisphere of embodiment of the invention front and back when having the 10ppm sample clock frequency deviation, the preceding planisphere of present embodiment method that is to use shown in Figure 2 this shows that the present invention has higher robustness for the ofdm system with high order modulation.

Claims (3)

1. the method for synchronous of an ofdm system sampling clock is characterized in that: may further comprise the steps:
Steps A, sample clock frequency deviation is estimated;
Step B, the sample clock frequency deviation that utilizes steps A to estimate carry out three rank cubic interpolation filter filtering to realize sample rate conversion, correct sample clock frequency deviation;
Step C, utilize a small amount of scattered pilot symbol that the phase place deflection that remaining sample clock frequency deviation causes is corrected.
2. the method for synchronous of a kind of ofdm system sampling clock according to claim 1 is characterized in that: be to utilize two training sequences by following method sample clock frequency deviation to be estimated in the described steps A:
　　
Figure 806992DEST_PATH_IMAGE001
In the formula:
Figure 756494DEST_PATH_IMAGE002
Be the symbol of training sequence on each subcarrier after FFT and the channel equalization of receiving, Be the frequency pilot sign on each subcarrier of training sequence correspondence,
Figure 95913DEST_PATH_IMAGE004
Be the OFDM notation index, owing to have only two training sequences, so
Figure 55779DEST_PATH_IMAGE004
Get 1 and 2,
Figure 176181DEST_PATH_IMAGE005
Be the subcarrier number index, ,
Figure 819969DEST_PATH_IMAGE007
With
Figure 103183DEST_PATH_IMAGE008
Value be respectively
Figure 379630DEST_PATH_IMAGE010
Wherein
Figure 578530DEST_PATH_IMAGE011
Obtain
Figure 716250DEST_PATH_IMAGE012
After, by
Figure 178455DEST_PATH_IMAGE013
, obtain sampling clock deviation
Figure 650894DEST_PATH_IMAGE014
, obtain final sampling clock deviation
Figure 122327DEST_PATH_IMAGE015
, wherein
Figure 645712DEST_PATH_IMAGE016
,
Figure 278818DEST_PATH_IMAGE017
The length that is respectively FFT adds the protection gap length, the length of FFT.
3. the method for synchronous of a kind of ofdm system sampling clock according to claim 2 is characterized in that: adopt following method that the phase place deflection that remaining sample clock frequency deviation causes is corrected among the described step C:
Figure 989286DEST_PATH_IMAGE018
In the formula
Figure 248097DEST_PATH_IMAGE019
Be phase deviation,
Figure 625989DEST_PATH_IMAGE020
Be the symbol after the process phase compensation.
CN2011100218436A 2011-01-20 2011-01-20 Sampling clock synchronization method for orthogonal frequency division multiplexing (OFDM) system Pending CN102075485A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103986683A (en) * 2014-05-30 2014-08-13 广东顺德中山大学卡内基梅隆大学国际联合研究院 OFDM symbol timing synchronization method based on high carrier number
CN104052707A (en) * 2014-05-21 2014-09-17 广东顺德中山大学卡内基梅隆大学国际联合研究院 Method for quickly synchronizing OFDM sampling frequencies with high carrier number
CN104243130A (en) * 2014-09-26 2014-12-24 南京芯度电子科技有限公司 PLC (power line communication) physical layer clock synchronizing method
CN109450837A (en) * 2018-11-30 2019-03-08 深圳市中科汉天下电子有限公司 A kind of estimation of sampling frequency offset and compensation method and system
CN111371717A (en) * 2018-12-26 2020-07-03 深圳市力合微电子股份有限公司 Method for carrying out phase tracking by using symmetric pilot frequency in OFDM modulation
CN114845377A (en) * 2022-05-05 2022-08-02 中南大学 High-precision wireless clock synchronization method and system based on UWB

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CN101039292A (en) * 2006-03-16 2007-09-19 中国科学院上海微系统与信息技术研究所 Method and apparatus for correcting sampling frequency deviation in OFDM system
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CN101039292A (en) * 2006-03-16 2007-09-19 中国科学院上海微系统与信息技术研究所 Method and apparatus for correcting sampling frequency deviation in OFDM system
US20090279421A1 (en) * 2008-05-07 2009-11-12 Wipro Techno Centre (Singapore) Pte Ltd Apparatus and methods for estimating and compensating sampling clock offset

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104052707A (en) * 2014-05-21 2014-09-17 广东顺德中山大学卡内基梅隆大学国际联合研究院 Method for quickly synchronizing OFDM sampling frequencies with high carrier number
CN104052707B (en) * 2014-05-21 2017-07-28 广东顺德中山大学卡内基梅隆大学国际联合研究院 High carrier number OFDM sample frequency fast synchronization methods
CN103986683A (en) * 2014-05-30 2014-08-13 广东顺德中山大学卡内基梅隆大学国际联合研究院 OFDM symbol timing synchronization method based on high carrier number
CN104243130A (en) * 2014-09-26 2014-12-24 南京芯度电子科技有限公司 PLC (power line communication) physical layer clock synchronizing method
CN109450837A (en) * 2018-11-30 2019-03-08 深圳市中科汉天下电子有限公司 A kind of estimation of sampling frequency offset and compensation method and system
CN109450837B (en) * 2018-11-30 2021-04-30 深圳昂瑞微电子技术有限公司 Sampling frequency offset estimation and compensation method and system
CN111371717A (en) * 2018-12-26 2020-07-03 深圳市力合微电子股份有限公司 Method for carrying out phase tracking by using symmetric pilot frequency in OFDM modulation
CN111371717B (en) * 2018-12-26 2022-08-05 深圳市力合微电子股份有限公司 Method for carrying out phase tracking by using symmetric pilot frequency in OFDM modulation
CN114845377A (en) * 2022-05-05 2022-08-02 中南大学 High-precision wireless clock synchronization method and system based on UWB
CN114845377B (en) * 2022-05-05 2024-02-23 中南大学 UWB-based high-precision wireless clock synchronization method and system

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