CN102055325A - Multiphase voltage reduction converter with phase compensation and phase compensation method thereof - Google Patents
Multiphase voltage reduction converter with phase compensation and phase compensation method thereof Download PDFInfo
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- CN102055325A CN102055325A CN2009101744605A CN200910174460A CN102055325A CN 102055325 A CN102055325 A CN 102055325A CN 2009101744605 A CN2009101744605 A CN 2009101744605A CN 200910174460 A CN200910174460 A CN 200910174460A CN 102055325 A CN102055325 A CN 102055325A
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Abstract
The invention relates to a multiphase voltage reduction converter with phase compensation. The multiphase voltage reduction converter is characterized in that: an error amplifier is connected with the output end of the multiphase voltage reduction converter to detect the output voltage of the multiphase voltage reduction converter so as to generate a simulation error signal; an analog-digital converter is connected with the error amplifier to convert the simulation error signal into a digital error signal; a digital compensation circuit is connected with the analog-digital converter to compensate the digital error signal; a digital pulse width modulation circuit is connected with the digital compensation circuit to provide a plurality of pulse width modulation signals according to the compensated digital error signal; and a plurality of phase circuits are connected in parallel between the digital pulse width modulation circuit and the output end of the multiphase voltage reduction converter, and each phase circuit converts input voltage into the output voltage according to the respective pulse width modulation signal, wherein the digital compensation circuit changes a compensation coefficient of the digital compensation circuit on the digital error signal along with the number of the phase circuits in the operation process.
Description
Technical field
The present invention relates to a kind of multi-phase and step-down formula transducer, specifically, is a kind of multi-phase and step-down formula transducer with phase masked (phase shedding) mechanism.
Background technology
Fig. 1 is known numeral four phase buck-converter with phase masked mechanism, and it comprises that four circuitry phases 10 are in order to be converted to output voltage V o with input voltage Vi, error amplifier 18 produces error signal EA in order to detect output voltage V o, analog-digital converter 16 is converted to the error signal e [n] of numeral in order to the error signal EA with simulation, digital compensation circuit 14 is in order to compensating error signal e[n] the generation error signal e ' [n], and digital pulse width modulation circuit 12 is according to error signal e ' [n] generation pulse-width modulation signal PWM1, PWM2, PWM3 and PWM4 drive four circuitry phases 10.Digital pulse width modulation circuit 12 can be according to the load current Io decision operation number of phases, sends enable signal EN1, EN2, EN3 and EN4 with unlatching out of the ordinary or close four circuitry phases 10, and then the usefulness of the described buck-converter of optimization.Fig. 2 is the power supply usefulness curves of described four phase buck-converter when the different operation numbers of phases, wherein curve 20 is four power supply usefulness curves when operating mutually, power supply usefulness curve when curve 22 is three-phase operation, power supply usefulness curve when the power supply usefulness curve when curve 24 is operated for two-phase, curve 26 are single-phase the operation.As shown in Figure 2, when operating the number of phases more after a little while, described buck-converter has preferable usefulness under low load current, opposite, and when operating the number of phases more for a long time, described buck-converter has preferable usefulness under high load currents.Therefore digital pulse width modulation circuit 12 will start more circuitry phase 10 when high load currents Io, and will reduce the number of the circuitry phase 10 that starts when hanging down load current Io.
Yet when operating the number of phases not simultaneously, the control of described buck-converter also changes to output voltage (control-to-output voltage) transfer function.When supposing single-phase operation, toot (resonant) frequency altogether of described buck-converter is fc, and when two-phase and four was operated mutually, toot the frequency altogether of described buck-converter may be respectively 1.414fc and 2fc so.In traditional design, described buck-converter has only a digital compensation circuit 14, so the design of digital compensation circuit 14 will be based on the control of single-phase or four phases to the output voltage transfer function.
With the loop gain frequency range is that 40KHz and phase margin (phase margin) are design object for about 60 °.Fig. 3 is that the design of numerical digit compensating circuit 14 is when single-phase, the frequency response of described buck-converter, resulting frequency response when wherein curve 30 and 32 is single-phase operation, resulting frequency response when curve 34 and 36 is operated for two-phase, curve 38 and 40 are four resulting frequency responses when operating mutually.Fig. 4 be the design of numerical digit compensating circuit 14 when single-phase, described buck-converter is at phase margin and frequency range single-phase, when two-phase and four is operated mutually.Fig. 5 is that the design of numerical digit compensating circuit 14 is based on four phase times, the frequency response of described buck-converter, resulting frequency response when wherein curve 42 and 44 is single-phase operation, resulting frequency response when curve 46 and 48 is operated for two-phase, curve 50 and 52 are four resulting frequency responses when operating mutually.Fig. 6 be the design of numerical digit compensating circuit 14 based on four phase times, described buck-converter is at phase margin and frequency range single-phase, when two-phase and four is operated mutually.With reference to Fig. 3 to Fig. 6, when the design of digital compensation circuit 14 based on single-phase control during to the output voltage transfer function, when four operate mutually, will there be enough phase margins, on the other hand, when the design of digital compensation circuit 14 based on the control of four phases during to the output voltage transfer function, frequency range when single-phase and two-phase is operated will diminish, the transient response variation when this will cause single-phase and two-phase operation.
Therefore known multi-phase and step-down formula transducer exists above-mentioned all inconvenience and problem.
Summary of the invention
Purpose of the present invention is to propose a kind of multi-phase and step-down formula transducer that changes penalty coefficient with the operation number of phases.
For achieving the above object, technical solution of the present invention is:
A kind of multi-phase and step-down formula transducer of tool number of phases compensation is characterized in that comprising:
Error amplifier connects the output of described multi-phase and step-down formula transducer, and the output voltage that detects described multi-phase and step-down formula transducer produces analog error signal;
Analog-digital converter connects described error amplifier, and described analog error signal is converted to digital error signal;
Digital compensation circuit connects described analog-digital converter, compensates described digital error signal;
The digital pulse width modulation circuit connects described digital compensation circuit, provides a plurality of pulse-width modulation signals according to the digital error signal after the described compensation; And
A plurality of circuitry phases are connected in parallel between the output of described digital pulse width modulation circuit and described multi-phase and step-down formula transducer, and each described circuitry phase is converted to described output voltage in response to pulse-width modulation signal separately with input voltage;
Wherein, described digital compensation circuit changes its penalty coefficient to described digital error signal with the circuitry phase number in the operation.
The multi-phase and step-down formula transducer of tool number of phases compensation of the present invention can also be further achieved by the following technical measures.
Aforesaid transducer, wherein said digital compensation circuit comprises:
A plurality of multiplexers are chosen penalty coefficient according to the circuitry phase number in the described operation separately; And
A plurality of multipliers, delay circuit and adder produce digital error signal after the described compensation from described digital error signal and the more described penalty coefficient of choosing.
Aforesaid transducer, wherein said digital compensation circuit comprises:
A plurality of compensators are separately to described digital error signal compensation; And
Multiplexer is chosen one as the digital error signal after the described compensation from the output of described a plurality of compensators.
A kind of number of phases compensation method of multi-phase and step-down formula transducer is characterized in that comprising the following steps:
(A). the output voltage that detects described multi-phase and step-down formula transducer produces analog error signal;
(B). described analog error signal is converted to digital error signal;
(C). compensate described digital error signal with the decision of the circuitry phase number in operation penalty coefficient;
(D). provide a plurality of pulse-width modulation signals according to the digital error signal after the described compensation; And
(E). in response to described a plurality of pulse-width modulation signals input voltage is converted to described output voltage.
The number of phases compensation method of multi-phase and step-down formula transducer of the present invention can also be further achieved by the following technical measures.
Aforesaid compensation method, wherein said step C comprises:
Choose a plurality of penalty coefficients according to the circuitry phase number in the described operation; And
Produce digital error signal after the described compensation from described digital error signal and the more described penalty coefficient computing of choosing.
Aforesaid compensation method, wherein said step C comprises:
Separately described digital error signal is compensated with a plurality of penalty coefficients; And
Signal after described a plurality of compensation is chosen one as the digital error signal after the described compensation.
After adopting technique scheme, the multi-phase and step-down formula transducer and the number of phases compensation method thereof of tool number of phases compensation of the present invention have when heterogeneous and single-phase operation, and described buck-converter all has the identical frequency and the advantage of phase margin.
Description of drawings
Fig. 1 is known schematic diagram with numeral four phase buck-converter of phase masked mechanism;
Fig. 2 is the power supply usefulness curve chart of buck-converter under the different operation numbers of phases among Fig. 1;
Fig. 3 be the design of the digital compensation circuit among Fig. 1 when single-phase, the schematic diagram of the frequency response of described buck-converter;
Fig. 4 be the design of the digital compensation circuit among Fig. 1 when single-phase, described buck-converter is at single-phase, phase margin when two-phase and four is operated mutually and the schematic diagram of frequency range;
Fig. 5 be the design of the digital compensation circuit among Fig. 1 based on four phase times, the schematic diagram of the frequency response of described buck-converter;
Fig. 6 be the design of the digital compensation circuit among Fig. 1 based on four phase times, described buck-converter is at single-phase, phase margin when two-phase and four is operated mutually and the schematic diagram of frequency range;
Fig. 7 is the schematic diagram of embodiments of the invention;
Fig. 8 is the schematic diagram of first embodiment of the middle digital compensation circuit of Fig. 7;
Fig. 9 is the schematic diagram of second embodiment of the middle digital compensation circuit of Fig. 7; And
Figure 10 is the frequency response analogous diagram of four phase buck-converter when four phases, two-phase and single-phase operation among Fig. 7.
Among the figure, 10, circuitry phase 12, digital pulse width modulation circuit 14, numerical digit complementer 16, analog-digital converter 18, error amplifier 20, four power supply usefulness curves 22 when operating mutually, power supply usefulness curve 24 during three-phase operation, power supply usefulness curve 26 during the two-phase operation, power supply usefulness curve 30 during single-phase the operation, frequency response 32 during single-phase the operation, frequency response 34 during single-phase the operation, frequency response 36 during the two-phase operation, frequency response 38 during the two-phase operation, four frequency responses 40 when operating mutually, four frequency responses 42 when operating mutually, frequency response 44 during single-phase the operation, frequency response 46 during single-phase the operation, frequency response 48 during the two-phase operation, frequency response 50 during the two-phase operation, four frequency responses 52 when operating mutually, four frequency responses 60 when operating mutually, digital compensation circuit 62, delay circuit 64, delay circuit 66, delay circuit 68, multiplexer 70, multiplier 72, multiplexer 74, multiplier 76, multiplexer 78, multiplier 80, multiplexer 82, multiplier 84, add circuit 86, multiplexer 88, multiplier 90, multiplexer 92, multiplier 94, multiplexer 96, multiplier 98, delay circuit 100, delay circuit 102, delay circuit 104, multiplexer 106, four phase compensators 108, three-phase compensator 110, two-phase compensator 112, single-phase compensator 120, frequency response 122 during single-phase the operation, frequency response 124 during single-phase the operation, frequency response 126 during the two-phase operation, frequency response 128 during the two-phase operation, four frequency responses 130 when operating mutually, four frequency responses when operating mutually.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof the present invention is illustrated further.
Now see also Fig. 7, Fig. 7 is the embodiment of the design based on the numeral four phase buck-converter of Fig. 1.As shown in the figure, the described digital compensation circuit 60 that is connected between digital pulse width modulation circuit 12 and the analog-digital converter 16, can learn the number of the circuitry phase 10 in the present operation according to number of phases signal phx_num, and change its penalty coefficient according to the operation number of phases, thereby provide be fit to the error signal e of the operation number of phases at present ' [n].
Fig. 8 is first embodiment of the digital compensation circuit 60 among Fig. 7, wherein delay circuit 62 delay error signal e[n] generation signal e[n-1], delay circuit 64 inhibit signal e[n-1] and generation signal e[n-2], delay circuit 66 inhibit signal e[n-2] and the generation signal
Multitask 68 according to number of phases signal phx_num from penalty coefficient A00, A01, A02 and A03 choose one of them, penalty coefficient that multiplier 70 provides multiplexer 68 and error signal e [n] multiply each other and produce signal eA0[n], multiplexer 72 according to number of phases signal phx_num from penalty coefficient A10, A11, A12 and A13 choose one of them, penalty coefficient and signal e[n-1 that multiplier 74 provides multiplexer 72] multiplying each other produces signal eA1[n-1], multiplexer 76 according to number of phases signal phx_num from penalty coefficient A20, A21, A22 and A23 choose one of them, penalty coefficient and signal e[n-2 that multiplier 78 provides multiplexer 76] multiplying each other produces signal eA2[n-2], multiplexer 80 according to number of phases signal phx_num from penalty coefficient A30, A31, A32 and A33 choose one of them, penalty coefficient and signal e[n-3 that multiplier 82 provides multiplexer 80] multiplying each other produces signal eA3[n-3], delay circuit 98 delay error signal e ' [n] produce signal e ' [n-1], delay circuit 100 inhibit signal e ' [n-1] produce signal e ' [n-2], delay circuit 102 inhibit signal e, [n-2] produces signal e ' [n-3], multiplexer 86 according to number of phases signal phx_num from penalty coefficient B10, B11, B12 and B13 choose one of them, penalty coefficient that multiplier 88 provides multiplexer 86 and signal e ' [n-1] multiply each other and produce signal e ' B1[n-1], multiplexer 90 according to number of phases signal phx_num from penalty coefficient B20, B21, B22 and B23 choose one of them, penalty coefficient that multiplier 92 provides multiplexer 90 and signal e ' [n-2] multiply each other and produce signal e ' B2[n-2], multiplexer 94 according to number of phases signal phx_num from penalty coefficient B30, B31, B32 and B33 choose one of them, penalty coefficient that multiplier 96 provides multiplexer 94 and signal e ' [n-3] multiply each other and produce signal e ' B3[n-3], add circuit 84 is with signal eA0[n], eA1[n-1], eA2[n-2], eA3[n-3], e ' B1[n-1], e ' B2[n-2] and e ' B3[n-3] in conjunction with producing error signal e ' [n].
Fig. 9 is second embodiment of the digital compensation circuit 60 among Fig. 7, it comprises multiplexer 104, four phase compensators 106, three-phase compensator 108, two-phase compensator 110 and single-phase compensator 112, wherein the design of four phase compensators 106 is based on four controls when operating mutually to the output voltage transfer function, control when the design of three-phase compensator 108 is based on three-phase operation is to the output voltage transfer function, control when the design of two-phase compensator 110 is based on the two-phase operation is to the output voltage transfer function, and the control the when design of single-phase compensator 112 is based on single-phase the operation is to the output voltage transfer function.Multiplexer 104 sends one of them output of four phase compensators 106, three-phase compensator 108, two-phase compensator 110 and single-phase compensator 112 to digital pulse width modulation circuit 12 according to number of phases signal phx_num.
Figure 10 is the frequency response analogous diagram of four phase buck-converter when four phases, two-phase and single-phase operation among Fig. 7, resulting frequency response when wherein curve 120 and 122 is single-phase operation, resulting frequency response when curve 124 and 126 is operated for two-phase, curve 128 and 130 are four resulting frequency responses when operating mutually.As can be seen from Figure 10, when gain was 0dB, curve 120,124 and 128 almost overlapped, and the curve 122,126 and 130 of this moment also almost overlaps, in other words, when four phases, two-phase and single-phase operation, described buck-converter all has identical frequency and phase margin.
Above embodiment is only for the usefulness that the present invention is described, but not limitation of the present invention, person skilled in the relevant technique under the situation that does not break away from the spirit and scope of the present invention, can also be made various conversion or variation.Therefore, all technical schemes that are equal to also should belong to category of the present invention, should be limited by each claim.
Claims (6)
1. the multi-phase and step-down formula transducer of tool number of phases compensation is characterized in that comprising:
Error amplifier connects the output of described multi-phase and step-down formula transducer, and the output voltage that detects described multi-phase and step-down formula transducer produces analog error signal;
Analog-digital converter connects described error amplifier, and described analog error signal is converted to digital error signal;
Digital compensation circuit connects described analog-digital converter, compensates described digital error signal;
The digital pulse width modulation circuit connects described digital compensation circuit, provides a plurality of pulse-width modulation signals according to the digital error signal after the described compensation; And
A plurality of circuitry phases are connected in parallel between the output of described digital pulse width modulation circuit and described multi-phase and step-down formula transducer, and each described circuitry phase is converted to described output voltage in response to pulse-width modulation signal separately with input voltage;
Wherein, described digital compensation circuit changes its penalty coefficient to described digital error signal with the circuitry phase number in the operation.
2. multi-phase and step-down formula transducer as claimed in claim 1 is characterized in that described digital compensation circuit comprises:
A plurality of multiplexers are chosen penalty coefficient according to the circuitry phase number in the described operation separately; And
A plurality of multipliers, delay circuit and adder produce digital error signal after the described compensation from described digital error signal and the more described penalty coefficient of choosing.
3. multi-phase and step-down formula transducer as claimed in claim 1 is characterized in that described digital compensation circuit comprises:
A plurality of compensators are separately to described digital error signal compensation; And
Multiplexer is chosen one as the digital error signal after the described compensation from the output of described a plurality of compensators.
4. the number of phases compensation method of a multi-phase and step-down formula transducer is characterized in that comprising the following steps:
(A). the output voltage that detects described multi-phase and step-down formula transducer produces analog error signal;
(B). described analog error signal is converted to digital error signal;
(C). compensate described digital error signal with the decision of the circuitry phase number in operation penalty coefficient;
(D). provide a plurality of pulse-width modulation signals according to the digital error signal after the described compensation; And
(E). in response to described a plurality of pulse-width modulation signals input voltage is converted to described output voltage.
5. method as claimed in claim 4 is characterized in that, described step C comprises:
Choose a plurality of penalty coefficients according to the circuitry phase number in the described operation; And
Produce digital error signal after the described compensation from described digital error signal and the more described penalty coefficient computing of choosing.
6. method as claimed in claim 4 is characterized in that, described step C comprises:
Separately described digital error signal is compensated with a plurality of penalty coefficients; And
Signal after described a plurality of compensation is chosen one as the digital error signal after the described compensation.
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| CN200910174460.5A CN102055325B (en) | 2009-11-04 | 2009-11-04 | Multiphase voltage reduction converter with phase compensation and phase compensation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10375500B2 (en) | 2013-06-27 | 2019-08-06 | Clarion Co., Ltd. | Propagation delay correction apparatus and propagation delay correction method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020144163A1 (en) * | 2000-10-10 | 2002-10-03 | Ryan Goodfellow | System and method for highly phased power regulation using adaptive compensation control |
| US20060001408A1 (en) * | 2004-07-02 | 2006-01-05 | Southwell Scott W | Digital calibration with lossless current sensing in a multiphase switched power converter |
| CN1722585A (en) * | 2004-07-15 | 2006-01-18 | 英特赛尔美国股份有限公司 | Apparatus and method for sliding-mode control in a multiphase switching power supply |
| US20070013350A1 (en) * | 2004-07-02 | 2007-01-18 | Benjamim Tang | Multiphase power regulator with load adaptive phase control |
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- 2009-11-04 CN CN200910174460.5A patent/CN102055325B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020144163A1 (en) * | 2000-10-10 | 2002-10-03 | Ryan Goodfellow | System and method for highly phased power regulation using adaptive compensation control |
| US20060001408A1 (en) * | 2004-07-02 | 2006-01-05 | Southwell Scott W | Digital calibration with lossless current sensing in a multiphase switched power converter |
| US20070013350A1 (en) * | 2004-07-02 | 2007-01-18 | Benjamim Tang | Multiphase power regulator with load adaptive phase control |
| CN1722585A (en) * | 2004-07-15 | 2006-01-18 | 英特赛尔美国股份有限公司 | Apparatus and method for sliding-mode control in a multiphase switching power supply |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10375500B2 (en) | 2013-06-27 | 2019-08-06 | Clarion Co., Ltd. | Propagation delay correction apparatus and propagation delay correction method |
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