CN102054873A - Display and thin film transistor array substrate and thin film transistors thereof - Google Patents
Display and thin film transistor array substrate and thin film transistors thereof Download PDFInfo
- Publication number
- CN102054873A CN102054873A CN2009102096864A CN200910209686A CN102054873A CN 102054873 A CN102054873 A CN 102054873A CN 2009102096864 A CN2009102096864 A CN 2009102096864A CN 200910209686 A CN200910209686 A CN 200910209686A CN 102054873 A CN102054873 A CN 102054873A
- Authority
- CN
- China
- Prior art keywords
- disposed
- film transistor
- thin
- substrate
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention relates to a display and a thin film transistor array substrate and thin film transistors thereof. The display comprises the thin film transistor array substrate, an optically transparent electrode substrate and a display dielectric layer arranged between the thin film transistor array substrate and the optically transparent electrode substrate, wherein the thin film transistor array substrate comprises a plurality of thin film transistors with oxide semiconductor layers; grid electrodes and grid insulating layers of the thin film transistors are arranged on the substrate respectively; the grid electrodes are covered by the grid insulating layers; the oxide semiconductor layers cover on the grid insulating layers conformally and are provided with channel regions positioned above the grid electrodes; and source electrodes and drain electrodes of the thin film transistors are arranged on the oxide semiconductor layers respectively and are positioned on the two sides of each channel region. The oxide semiconductor layers are made of optically transparent materials, so that a manufacturing process for patterning the oxide semiconductor layers can be eliminated in a display manufacturing process so as to save manufacturing cost and shorten the time of the manufacturing process.
Description
Technical field
The present invention relates to a kind of display unit, particularly relate to a kind of display and the thin-film transistor array base-plate and thin-film transistor that can not produce the thin-film transistor of leakage current that have because of irradiation.
Background technology
Reflected displaying device is to utilize the light source of the incident ray of process reflection as display display frame.Because reflected displaying device does not need to dispose back light, make the power consumption (powerconsumption) of element reduce, and whole display in design can be comparatively frivolous, therefore paid much attention in display industry in recent years.
On the other hand, present display can be divided into active and passive according to its driving element mostly.General active display is as driving element mostly with thin-film transistor, and because amorphous silicon film transistor (amorphous silicon thin film transistor, a-Si TFT) manufacturing process is simple, cheap, therefore many at present with the driving element of amorphous silicon film transistor as active display.
Fig. 1 is the generalized section of thin-film transistor array base-plate in the single pixel of known active display.Please refer to Fig. 1, in the manufacturing process of thin-film transistor array base-plate 100, is to form grid 104 earlier on substrate 102, then forms the gate insulation layer 106 of cover grid 104 again.Afterwards, on gate insulation layer 106, form amorphous silicon semiconductor layer (figure does not show).Because amorphous silicon semiconductor layer is light tight, in order to increase this aperture ratio of pixels (aperture ratio), then must remove the amorphous silicon semiconductor layer of part, only stay be positioned at grid 104 tops part as channel layer 108.
Afterwards, on gate insulation layer 106, form source electrode 110 and drain electrode 112, to cover the channel layer 108 of part.At this moment, promptly roughly finish the making of thin-film transistor 101.Then, on substrate 102, form protective layer 114, to expose the drain electrode 112 of part with opening 116.And, on protective layer 114, form pixel electrode 118, and pixel electrode 118 is to insert in the opening 116 and electrically connect with drain electrode 112.
Yet, because amorphous silicon material has photoelectric characteristic, therefore if in reflected displaying device, use thin film transistor (TFT) array 100, then when surround lighting when thin-film transistor 101 tops are incident to channel layer 108, can in channel layer 108, produce leakage current, make thin film transistor (TFT) array 100 that undesired start take place, cause the problem of display generation display abnormality.
For addressing the above problem, known channel layer 108 tops that tie up to form metal light shield layer (figure does not show), produce leakage current to avoid ambient lighting to be mapped to channel layer 108.But avoid thin-film transistor 101 to produce leakage current in this way, must in the manufacturing process of reflected displaying device, add one light shield, and therefore increase the manufacturing process cost of reflected displaying device.
This shows that above-mentioned existing display and thin-film transistor array base-plate thereof and thin-film transistor obviously still have inconvenience and defective, and demand urgently further being improved in product structure, manufacture method (processing method) and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new display and thin-film transistor array base-plate and thin-film transistor, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The objective of the invention is to, overcome the defective that existing thin-film transistor exists, and provide a kind of new thin-film transistor, technical problem to be solved is to make the channel layer (channel layer) between its source electrode and the drain electrode not have a photoelectric characteristic, thereby can avoid when being subjected to irradiate light, producing leakage current, be very suitable for practicality.
Another object of the present invention is to, overcome the defective that existing thin-film transistor array base-plate exists, and provide a kind of new thin-film transistor array base-plate, technical problem to be solved is to make it can utilize the few and manufacturing process that cost is low of light shield to be made, and have not because of being subjected to rayed to produce the thin-film transistor of leakage current, thereby be suitable for practicality more.
A further object of the present invention is, overcome the defective that existing display exists, and a kind of new display is provided, technical problem to be solved is to make its thin-film transistor can not produce leakage current after being subjected to illumination, thereby can improve its demonstration usefulness, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of thin-film transistor that the present invention proposes, it comprises grid, gate insulation layer, source electrode, drain electrode and oxide semiconductor layer.Grid and gate insulation layer are disposed at respectively on first substrate, and the gate insulation layer cover grid.Oxide semiconductor layer conformally is disposed at the gate insulation layer top, and it has the channel region of position above grid.Source electrode is disposed at the gate insulation layer top respectively with drain electrode, and is positioned at the both sides of the channel region of oxide semiconductor layer.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of thin-film transistor array base-plate according to the present invention proposes comprises first substrate, many data lines, multi-strip scanning line, a plurality of above-mentioned thin-film transistor, protective layer and a plurality of pixel electrodes.Scan line and data line be haply perpendicular to each other, and define a plurality of pixel regions on first substrate.Each thin-film transistor is configured in the corresponding pixel region, and with corresponding data line and scan line electric connection.Protective layer covers on first substrate, and has the contact window of the part drain electrode that exposes each thin-film transistor.These pixel electrodes are configured in respectively in the corresponding pixel region, and insert the corresponding contact window opening and electrically connect with corresponding drain electrode.
The object of the invention to solve the technical problems realizes in addition more by the following technical solutions.According to a kind of display that the present invention proposes, comprise above-mentioned thin-film transistor array base-plate, euphotic electrode substrate and be configured in display dielectric layer between euphotic electrode substrate and the thin-film transistor array base-plate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In one embodiment of this invention, above-mentioned oxide semiconductor layer conformally covers on the gate insulation layer, and source electrode and drain configuration are on oxide semiconductor layer.
In one embodiment of this invention, on above-mentioned oxide semiconductor layer conformally covers source electrode and drains, and channel region is between source electrode and drain electrode.
In one embodiment of this invention, above-mentioned thin-film transistor also comprises first ohmic contact layer and second ohmic contact layer, wherein first ohmic contact layer is disposed between source electrode and the oxide semiconductor layer, and second ohmic contact layer then is to be disposed between drain electrode and the oxide semiconductor layer.
By technique scheme, display of the present invention and thin-film transistor array base-plate thereof and thin-film transistor have following advantage and beneficial effect at least: the present invention is with the channel layer of oxide semiconductor material as the thin-film transistor of display, and, therefore can avoid thin-film transistor behind irradiation, to produce the problem of leakage current because oxide semiconductor is not had a photoelectric characteristic.In addition,, therefore in the manufacturing process of display of the present invention, can omit the patterning manufacturing process of oxide semiconductor layer, to save the manufacturing process cost and to shorten manufacturing process time because the material of oxide semiconductor layer is the light-permeable material.
In sum, the invention relates to a kind of display and thin-film transistor array base-plate thereof and thin-film transistor.This display comprises thin-film transistor array base-plate, euphotic electrode substrate and is disposed between the two display dielectric layer.Thin-film transistor array base-plate comprises a plurality of thin-film transistors with oxide semiconductor layer, and wherein the grid of thin-film transistor and gate insulation layer are disposed on the substrate respectively, and the gate insulation layer cover grid.Oxide semiconductor layer conformally is covered on the gate insulation layer, and has the channel region of position above grid.The source electrode of thin-film transistor is disposed on the oxide semiconductor layer respectively with drain electrode, and is positioned at the both sides of channel region.Because the material of oxide semiconductor layer is the light-permeable material, therefore in the manufacturing process of this display, can omit the patterning manufacturing process of oxide semiconductor layer, to save the manufacturing process cost and to shorten manufacturing process time.The present invention has obvious improvement technically, and has tangible good effect, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the generalized section of thin-film transistor array base-plate in the single pixel of known active display.
Fig. 2 is the generalized section of display in one embodiment of the invention.
Fig. 3 is the generalized section of display in the another embodiment of the present invention.
Fig. 4 is the schematic diagram of thin-film transistor array base-plate in one embodiment of the invention.
Fig. 5 is the thin-film transistor array base-plate partial cutaway schematic in one embodiment of Fig. 4.
Fig. 6 is the thin-film transistor array base-plate partial cutaway schematic in another embodiment of Fig. 4.
Fig. 7 is the thin-film transistor array base-plate partial cutaway schematic in another embodiment of Fig. 4.
100,210: thin-film transistor array base-plate
101,300: thin-film transistor
102: substrate
104,310: grid
106,320: gate insulation layer
108: channel layer
110,340: source electrode
112,350: drain electrode
114,214: protective layer
116,217: opening
118,215: pixel electrode
200,201: display
211: the first substrates
212: data line
213: scan line
216: pixel region
220: display dielectric layer
230: the euphotic electrode substrate
232: the second substrates
234: transparency electrode
236: color filter film
330: oxide semiconductor layer
332: channel region
370,380: ohmic contact layer
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the display that foundation the present invention is proposed and embodiment, structure, method, step, feature and the effect thereof of thin-film transistor array base-plate and thin-film transistor thereof, describe in detail as after.
Fig. 2 is the generalized section of display in one embodiment of the invention.Please refer to Fig. 2, display 200 comprises thin-film transistor array base-plate 210, display dielectric layer 220 and euphotic electrode substrate 230, wherein euphotic electrode substrate 230 is to be positioned at thin-film transistor array base-plate 210 tops, and 220 of display dielectric layers are to be disposed between euphotic electrode substrate 230 and the thin-film transistor array base-plate 210.
On the other hand, display dielectric layer 220 can be microcapsules electrophoretic layer (microcapsuleelectrophoretic layer), little glass of electrophoretic layer (microcup electrophoretic layer), cholesterol liquid crystal layer (cholesteric liquid crystal layer), electric wettable layer (electro-wetting layer) or powder mobile layer (quick response-liquid powderlayer).
Specifically, in another embodiment, euphotic electrode substrate 230 can also comprise color filter film (color filter film) 236, and it is to be disposed between the transparency electrode 234 and second substrate 232, as shown in Figure 3.That is to say that the display 201 that Fig. 3 illustrated is color monitor.
Fig. 4 is the schematic diagram of thin-film transistor array base-plate in one embodiment of the invention.Please refer to Fig. 4, thin-film transistor array base-plate 210 comprises first substrate 211, many data lines 212, multi-strip scanning line 213, a plurality of thin-film transistor 300, protective layer 214 and a plurality of pixel electrodes 215.Wherein, the material of first substrate 211 can be glass or plastic cement.In the present embodiment, the material of first substrate 211 for example is identical with the material of second substrate 232, as PETG, Polyethylene Naphthalate or polymethyl methacrylate.In other words, the display 200 that Fig. 2 illustrated can be a flexible display.
These data lines 212 are to be disposed in parallel to each other on first substrate 211, and 213 of scan lines are roughly to be located vertically on first substrate 211 with data line 212, and define a plurality of pixel regions 216 with data line 212 on first substrate 211.These thin-film transistors 300 are to be configured in respectively in the corresponding pixel region 216, and electrically connect with corresponding scanning line 213 and data line 212.The structure of the thin-film transistor 300 of present embodiment below will be described in detail in detail.
Fig. 5 is the partial cutaway schematic of the thin-film transistor array base-plate of Fig. 4.Please refer to Fig. 5, thin-film transistor 300 comprises grid 310, gate insulation layer 320, oxide semiconductor layer 330, source electrode 340 and drains 350.Wherein, grid 310 is disposed at respectively on first substrate 211 with gate insulation layer 320, and gate insulation layer 320 cover grid 310.Oxide semiconductor layer 330 conformally is covered on the gate insulation layer 320, and it has the channel region 332 of position above grid 310.Source electrode 340 is disposed at respectively on the oxide semiconductor 330 with drain electrode 350, and is positioned at the both sides of channel region 332.Please be simultaneously with reference to Fig. 4 and Fig. 5, source electrode 340 is electrically connected to its pairing data line 212, drains 350 to be and the pixel electrode 215 (see figure 4)s electric connection that is configured in the pixel region 216.
The material of grid 310 is metal material or transparent conductive material.With present embodiment, the material of grid 310 for example is molybdenum or chromium, and its thickness for example is 2000 dusts (angstrom).The material of gate insulation layer 320 for example is a silica, and its thickness for example is 2000 dusts.The material of oxide semiconductor layer 330 for example is indium gallium zinc oxide (IGZO) or indium-zinc oxide (IZO), and its thickness for example is 900 dusts.Source electrode 340 then can be identical or different with grid 310 with the material of drain electrode 350, and with present embodiment, source electrode 340 can be molybdenum or chromium with the material of drain electrode 350, and its thickness for example is 2000 dusts.
What deserves to be mentioned is, in order to reduce the impedance between source electrode 340/ drain electrode 350 and the oxide semiconductor layer 330, in another embodiment, thin-film transistor 300 can also comprise ohmic contact layer 370 and ohmic contact layer 380, its be disposed between source electrode 340 and the oxide semiconductor layer 330 respectively and drain 350 and oxide semiconductor layer 330 between, as shown in Figure 6.Specifically, ohmic contact layer 370 can be indium gallium zinc oxide (IGZO) or the indium-zinc oxide (IZO) that conductivity is higher than oxide semiconductor layer 330 with the material of ohmic contact layer 380.Specifically, manufacturing process at thin-film transistor 300 (is a processing procedure, below all be called manufacturing process) in, it for example is in single plated film manufacturing process, makes oxide semiconductor layer 330, ohmic contact layer 370 and ohmic contact layer 380 simultaneously with different oxygen-supply quantities.
It should be noted that, the present invention is not limited to the position of oxide semiconductor layer 330 between gate insulation layer 320 and source electrode 340/ drain electrode 350, in another embodiment, source electrode 340 is to be disposed on the gate insulation layer 320 with drain electrode 350, oxide semiconductor layer 330 then is conformally to be covered in source electrode 340 and the drain electrode 350, and make 332 of its channel regions between source electrode 340 and drain electrode 350, as shown in Figure 7.Because this embodiment forms source electrode 340 and drain electrode 350 earlier on gate insulation layer 320, in source electrode 340 and drain electrode 350, form oxide semiconductor layer 330 more afterwards, therefore can avoid oxide semiconductor layer 330 in the patterning manufacturing process of source electrode 340 and drain electrode 350 because of the improper and impaired problem of etching.
And in the embodiment shown in fig. 7, thin-film transistor 300 equally also can comprise described ohmic contact layer 370 of previous embodiment and ohmic contact layer 380.
In aforementioned these embodiment, because oxide semiconductor layer 330 is not had a photoelectric characteristic, even therefore surround lighting is incident to oxide semiconductor layer 330 from thin-film transistor 300 tops, the problem of leakage current also can not take place in thin-film transistor 300.Specifically, owing to constitute the material light-permeable of oxide semiconductor layer 330, therefore in the manufacturing process of thin-film transistor array base-plate 210 of the present invention, the oxide semiconductor layer 330 that does not need to remove part can not impact the aperture opening ratio in its pairing pixel region (aperture ratio) yet.In other words, the manufacturing process of the manufacturing process of thin-film transistor array base-plate 210 of the present invention and known thin-film transistor array base-plate 100 in comparison, not only manufacturing process is simple and production cost is low.
Please referring again to Fig. 5, the protective layer 214 in the thin-film transistor array base-plate 210 is to be disposed on first substrate 211, and has a plurality of openings 217 (only drawing among the figure).These openings 217 are to correspond to each pixel region 216 respectively, with the part of the drain electrode 350 that exposes the thin-film transistor 300 in its pairing pixel region 216.What deserves to be mentioned is that the material of the protective layer 214 of present embodiment for example is a resin, and it for example is to be formed on first substrate 211 in the mode that is coated with (spin coating) that spins, thereby has preferable planarization effect.In addition, the thickness of protective layer 214 is about 2.5 microns.
In sum, the present invention has following advantage:
1. the present invention is with the channel layer of oxide semiconductor material as the thin-film transistor of display, and because oxide semiconductor is not had a photoelectric characteristic, therefore can avoid thin-film transistor to produce the problem of leakage current behind irradiation.
2. because oxide semiconductor layer film forming at room temperature, thereby can directly on the not good plastic substrate of heat resistance, finish manufacturing process.In other words, in the manufacturing process of the flexual display of tool, but with thin-film transistor with oxide semiconductor layer as the driving element simplified manufacturing technique and reduce cost.
3. because the material of oxide semiconductor layer is the light-permeable material, therefore in the manufacturing process of display of the present invention, can omit the patterning manufacturing process of oxide semiconductor layer, to save the manufacturing process cost and to shorten manufacturing process time.
4. the present invention can utilize resin to be used as protective layer on the thin-film transistor array base-plate, thereby can obtain good planarization effect.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (12)
1. thin-film transistor is characterized in that comprising:
One grid is disposed on one first substrate;
One gate insulation layer is disposed on this first substrate and covers this grid;
The monoxide semiconductor layer conformally is disposed at this gate insulation layer top, and this oxide semiconductor layer has a channel region, is positioned at this grid top;
One source pole is disposed at this gate insulation layer top, and is positioned at a side of this channel region; And
One drain electrode is disposed at this gate insulation layer top, and is positioned at the opposite side of this channel region.
2. thin-film transistor as claimed in claim 1 is characterized in that wherein this oxide semiconductor layer conformally covers on this gate insulation layer, and this source electrode and this drain configuration are on this oxide semiconductor layer.
3. thin-film transistor as claimed in claim 1 is characterized in that wherein this oxide semiconductor layer conformally covers in this source electrode and this drain electrode, and this channel region is between this source electrode and this drain electrode.
4. thin-film transistor as claimed in claim 1 is characterized in that also comprising:
One first ohmic contact layer is disposed between this source electrode and this oxide semiconductor layer; And
One second ohmic contact layer is disposed between this drain electrode and this oxide semiconductor layer.
5. thin-film transistor array base-plate is characterized in that comprising:
One first substrate;
Many data lines are disposed on this first substrate in parallel with each other;
The multi-strip scanning line is disposed on this first substrate, and those scan lines are parallel to each other and vertical those data lines, and defines a plurality of pixel regions on this first substrate;
A plurality of thin-film transistors are disposed at those corresponding pixel regions respectively in one of them, and with corresponding those data lines one of them and corresponding one of them electric connection of those scan lines, respectively this thin-film transistor comprises:
One grid is disposed on this first substrate;
One gate insulation layer is disposed on this first substrate and covers this grid;
The monoxide semiconductor layer conformally is disposed at this gate insulation layer top, and this oxide semiconductor layer has a channel region, is positioned at this grid top;
One source pole is disposed at this gate insulation layer top, and is positioned at a side of this channel region; And
One drain electrode is disposed at this gate insulation layer top, and is positioned at the opposite side of this channel region;
One protective layer is covered on this first substrate, and this protective layer has a plurality of contact windows of the part that exposes those drain electrodes respectively; And
A plurality of pixel electrodes are disposed at those corresponding pixel regions respectively in one of them, and respectively this pixel electrode insert in this corresponding contact window and with this corresponding drain electrode electric connection.
6. thin-film transistor array base-plate as claimed in claim 5 is characterized in that wherein respectively this oxide semiconductor layer of this thin-film transistor conformally covers on this gate insulation layer, and this source electrode and this drain configuration are on this oxide semiconductor layer.
7. thin-film transistor array base-plate as claimed in claim 5 is characterized in that wherein respectively this oxide semiconductor layer of this thin-film transistor conformally covers in this source electrode and this drain electrode, and this channel region is between this source electrode and this drain electrode.
8. thin-film transistor array base-plate as claimed in claim 5 is characterized in that wherein respectively this thin-film transistor also comprises:
One first ohmic contact layer is disposed between this source electrode and this oxide semiconductor layer; And
One second ohmic contact layer is disposed between this drain electrode and this oxide semiconductor layer.
9. display is characterized in that comprising:
One thin-film transistor array base-plate is characterized in that comprising:
One first substrate;
Many data lines are disposed on this first substrate in parallel with each other;
The multi-strip scanning line is disposed on this first substrate, and those scan lines are parallel to each other and vertical those data lines, and defines a plurality of pixel regions on this first substrate;
A plurality of thin-film transistors are disposed at those corresponding pixel regions respectively in one of them, and with corresponding those data lines one of them and corresponding one of them electric connection of those scan lines, respectively this thin-film transistor comprises:
One grid is disposed on this first substrate;
One gate insulation layer is disposed on this first substrate and covers this grid;
The monoxide semiconductor layer conformally be disposed at this gate insulation layer top, and this oxide semiconductor layer has a channel region that is positioned at this grid top;
One source pole is disposed at this gate insulation layer top, and is positioned at a side of this channel region; And
One drain electrode is disposed at this gate insulation layer top, and is positioned at the opposite side of this channel region;
One protective layer is covered on this first substrate, and this protective layer has a plurality of contact windows of the part that exposes those drain electrodes respectively; And
A plurality of pixel electrodes be disposed at those corresponding pixel regions respectively in one of them, and respectively this pixel electrode are inserted in this corresponding contact window, and electrically connect with corresponding this drain electrode;
One euphotic electrode substrate comprises:
One second substrate is disposed at this thin-film transistor array base-plate top; And
One transparency electrode is disposed on this second substrate, and between this thin-film transistor array base-plate and this second substrate; And
One display dielectric layer is disposed between this thin-film transistor array base-plate and this euphotic electrode substrate.
10. display as claimed in claim 9 is characterized in that wherein respectively this oxide semiconductor layer of this thin-film transistor conformally covers on this gate insulation layer, and this source electrode and this drain configuration are on this oxide semiconductor layer.
11. display as claimed in claim 9 is characterized in that wherein respectively this oxide semiconductor layer of this thin-film transistor conformally covers in this source electrode and this drain electrode, and this channel region is between this source electrode and this drain electrode.
12. display as claimed in claim 9 is characterized in that wherein respectively this thin-film transistor also comprises:
One first ohmic contact layer is disposed between this source electrode and this oxide semiconductor layer; And
One second ohmic contact layer is disposed between this drain electrode and this oxide semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209686.4A CN102054873B (en) | 2009-11-05 | 2009-11-05 | Display and thin film transistor array substrate and thin film transistors thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209686.4A CN102054873B (en) | 2009-11-05 | 2009-11-05 | Display and thin film transistor array substrate and thin film transistors thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102054873A true CN102054873A (en) | 2011-05-11 |
| CN102054873B CN102054873B (en) | 2014-03-05 |
Family
ID=43959028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910209686.4A Active CN102054873B (en) | 2009-11-05 | 2009-11-05 | Display and thin film transistor array substrate and thin film transistors thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102054873B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104051470A (en) * | 2013-03-12 | 2014-09-17 | 元太科技工业股份有限公司 | Pixel structure |
| WO2015192549A1 (en) * | 2014-06-19 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device |
| CN111856832A (en) * | 2019-04-23 | 2020-10-30 | 元太科技工业股份有限公司 | Reflective active element array substrate, manufacturing method thereof and reflective display device |
| US11921395B2 (en) | 2019-04-23 | 2024-03-05 | E Ink Holdings Inc. | Reflective active device array substrate and manufacturing method thereof and reflective display apparatus and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070108446A1 (en) * | 2005-11-15 | 2007-05-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US20070166859A1 (en) * | 2005-12-29 | 2007-07-19 | Lee Hye S | Array substrate for liquid crystal display device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007017798A (en) * | 2005-07-08 | 2007-01-25 | Alps Electric Co Ltd | Liquid crystal display device |
| KR101402189B1 (en) * | 2007-06-22 | 2014-06-02 | 삼성전자주식회사 | Oxide thin film transistor and etchant of Zn oxide |
-
2009
- 2009-11-05 CN CN200910209686.4A patent/CN102054873B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070108446A1 (en) * | 2005-11-15 | 2007-05-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US20070166859A1 (en) * | 2005-12-29 | 2007-07-19 | Lee Hye S | Array substrate for liquid crystal display device and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104051470A (en) * | 2013-03-12 | 2014-09-17 | 元太科技工业股份有限公司 | Pixel structure |
| CN104051470B (en) * | 2013-03-12 | 2017-01-11 | 元太科技工业股份有限公司 | Pixel structure |
| WO2015192549A1 (en) * | 2014-06-19 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device |
| CN111856832A (en) * | 2019-04-23 | 2020-10-30 | 元太科技工业股份有限公司 | Reflective active element array substrate, manufacturing method thereof and reflective display device |
| US11921395B2 (en) | 2019-04-23 | 2024-03-05 | E Ink Holdings Inc. | Reflective active device array substrate and manufacturing method thereof and reflective display apparatus and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102054873B (en) | 2014-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105527767B (en) | A kind of array substrate and liquid crystal display | |
| CN102314034B (en) | Active element, pixel structure, driving circuit and display panel | |
| CN103268878B (en) | The manufacture method of tft array substrate, tft array substrate and display unit | |
| US8259265B2 (en) | Liquid crystal display panel, liquid crystal display apparatus and manufacturing method thereof | |
| CN103904086A (en) | Thin-film transistor array substrate | |
| KR20090076572A (en) | Display substrate and electrophoretic display device having the same and manufacturing method of display substrate | |
| CN104966501B (en) | GOA circuit structure for narrow frame LCD | |
| EP2261730B1 (en) | Pixel designs of improving the aperture ratio in an LCD | |
| CN204422931U (en) | A kind of color membrane substrates and display panels | |
| CN102239440A (en) | Liquid crystal display device | |
| CN105652543A (en) | Array substrate and manufacturing method thereof and display device | |
| CN102969311B (en) | Array substrate and manufacturing method thereof, and display device | |
| CN102054873B (en) | Display and thin film transistor array substrate and thin film transistors thereof | |
| CN102566190A (en) | Electronic paper device | |
| CN109300995A (en) | A kind of thin film transistor and its manufacturing method, array substrate and display panel | |
| CN102520556A (en) | Pixel structure and manufacturing method thereof | |
| CN103278983B (en) | IPS liquid crystal display and color membrane substrates thereof | |
| US8723172B2 (en) | Display device, thin film transistor array substrate and thin film transistor having oxide semiconductor | |
| CN109449166A (en) | A kind of array substrate and preparation method thereof and display panel | |
| CN201876642U (en) | Pixel structure | |
| CN103094353A (en) | Thin film transistor structure, liquid crystal display device and manufacturing method | |
| CN104733478A (en) | Array substrate, manufacturing method thereof and display device | |
| CN103681695A (en) | Thin-film transistor array substrate, manufacturing method thereof and liquid crystal display device | |
| CN103280429B (en) | Manufacturing method of thin film transistor (TFT) array substrate and TFT array substrate | |
| CN103135302A (en) | Thin film transistor-liquid crystal display in mode of plane switch control and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |