CN102054735A

CN102054735A - Method for filling high-aspect ratio groove isolation area

Info

Publication number: CN102054735A
Application number: CN200910201728XA
Authority: CN
Inventors: 刘继全
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-10-28
Filing date: 2009-10-28
Publication date: 2011-05-11

Abstract

The invention discloses a method for filling a high-aspect ratio groove isolation area. The method comprises the following steps of: forming a groove on a silicon slice or a silicon epitaxial layer; sequentially forming an oxidation layer and a nitride layer on the surface of the groove; removing the oxidation layer and the nitride layer at the bottom of the groove through selective etching to expose silicon at the bottom of the groove; growing the silicon epitaxial layer by a selective epitaxial technical method to fill the groove; and performing high-temperature oxidation on the top of the silicon epitaxial layer to convert the silicon epitaxial layer into a silicon oxide layer. By the method, no void and no seam are generated in the groove isolation area after the groove isolation area is filled and the groove isolation area has high isolation performance.

Description

Fill the method for high aspect ratio trench quite isolated area

Technical field

The present invention relates to a kind of method of manufacturing technology of semiconductor integrated circuit, particularly relate to a kind of method of filling the high aspect ratio trench quite isolated area.

Background technology

In the manufacturing process of semiconductor integrated circuit, need usually to adopt certain technological means that two devices or assembly are kept apart, to prevent to produce the electric coupling of not expecting.

Shallow-trench isolation is a kind of common partition method.Shallow-trench isolation generally comprises following steps: at first form groove on silicon chip, use chemical gaseous phase depositing process deposition insulating layer in groove again, the method with cmp makes the insulating barrier planarization at last.

Along with the increase of the reducing of dimensions of semiconductor devices, density of components, it is more and more littler that the width of shallow trench isolation region also becomes.But because the needs of device isolation, the degree of depth of shallow trench isolation region can not reduce too much even also will increase, and this becomes increasing with regard to the depth-to-width ratio that has caused shallow trench isolation region.Depth-to-width ratio is meant the degree of depth of groove and the ratio of width.Depth-to-width ratio more than or equal to 3 is generally considered to be high-aspect-ratio.

For shallow grooved-isolation technique, trench fill is relatively more crucial, requires the insulating barrier fill process that step coverage is preferably arranged generally speaking.For chemical vapour deposition (CVD), the trench fill effect is very big with the depth-to-width ratio relation.For the groove of high-aspect-ratio, even the good high density plasma CVD of gradient coating performance still has to have hole or seam in groove, this is because the inhomogeneous growth of dielectric film on trenched side-wall causes.Far away more apart from the groove top, the trenched side-wall growth is slow more.The depth-to-width ratio of groove is high more, and the difference of the top of trenched side-wall and the growth rate of bottom is big more.So the depth-to-width ratio of groove is big more, groove inside is easy to generate hole or seam (referring to Fig. 1, label 3 expression insulating barriers wherein) more, and these holes and seam generally all are positioned at the top of groove.Behind the chemical vapour deposition (CVD) filling groove, generally to use chemical and mechanical grinding method and make its planarization, the space and the seam that are positioned at the groove top might be ground, and follow-up technology is caused harmful effect.The existence of groove mesopore and seam also can cause the trench isolations performance decrease, sometimes even can cause short circuit.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of method of filling the high aspect ratio trench quite isolated area, makes in the channel separating zone after the filling and does not produce hole and seam, and channel separating zone has the good isolation performance.

For solving the problems of the technologies described above, the method for filling high aspect ratio trench quite isolated area of the present invention comprises the steps: to form groove on silicon chip or silicon epitaxy layer; Form oxide layer, nitration case successively in described flute surfaces; With the nitration case and the oxide layer of selective etch removal channel bottom, expose the silicon of channel bottom; With selective silicon epitaxy technique method grown silicon epitaxial loayer groove is filled; High-temperature oxydation is carried out at the silicon epitaxy layer top, make it be converted into silicon oxide layer.

Adopt method of the present invention, owing to select for use selective silicon epitaxy technique method that groove is filled, only in the channel bottom grown silicon, trenched side-wall and top can grown silicon, and gradient coating performance is 100%, so can not produce hole and seam in the groove.

In addition, because insulating barrier is all arranged at trenched side-wall and groove top, conducting can not take place horizontal and vertical, can play the effect that closes on components and parts of isolating.Certainly, with respect to complete filling insulating barrier in the groove, the channel separating zone isolation performance that adopts method of the present invention to form has certain decline, but can remedy by the degree of depth of suitable increase groove.

Adopt in the high aspect ratio trench quite isolated area after method of the present invention can make filling and do not produce hole and seam, make this channel separating zone have the good isolation performance, can not satisfy the requirement of subsequent technique follow-up technology is exerted an influence.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 adopts existing method to fill the hole schematic diagram that produces after the high aspect ratio trench quite;

Fig. 2 is method one an embodiment etching groove schematic diagram of the present invention;

Fig. 3 is method one embodiment oxide layer of the present invention and nitration case growth schematic diagram;

Fig. 4 is that method one embodiment of the present invention removes channel bottom nitration case and oxide layer schematic diagram;

Fig. 5 is method one an embodiment selective epitaxial growth schematic diagram of the present invention;

Fig. 6 is method one an embodiment top silicon epitaxy layer oxidation schematic diagram of the present invention.

Embodiment

For shallow grooved-isolation technique, must guarantee lateral isolation and vertically isolation, prevent that it from conducting taking place just can play isolation effect on horizontal and vertical both direction.Given this purpose, in fact if on three directions of groove the growth insulating barrier, the insulating barrier of promptly growing in trenched side-wall and bottom is perhaps at the grown on top insulating barrier of trenched side-wall and trench filling.Generally trench filling to be arranged in the groove, to satisfy the requirement of follow-up technology.For general fill process, because the restriction of gradient coating performance may have the existence of space and seam after the trench fill.And these holes and seam generally all are positioned at the groove top, and behind follow-up cmp, these holes and seam can come out, and this generally is unallowed.

In order to obtain not have the high aspect ratio trench quite isolated area of hole and seam, the invention provides a kind of new method; High aspect ratio trench quite of the present invention is meant that the ratio of the degree of depth of groove and width more than or equal to 3, is 1.5 μ m with the degree of depth only below, and width is that the trench fill of 0.5 μ m specifies the process and the method for filling high aspect ratio trench quite for embodiment.

Step 1, referring to shown in Figure 2, on silicon chip 1 (perhaps on silicon epitaxy layer) to adopt dry etching or wet etching to form the degree of depth be 1.5 μ m, width is the groove 2 of 0.5 μ m.In other embodiments of the invention, the degree of depth of described groove is 0.1 μ m～5.0 μ m.

Step 2, in conjunction with shown in Figure 3, form the oxide layer 7 of one deck 100 dusts on the surface (two side and the bottom that comprise groove 2, the surface of silicon chip 1) of groove 2 with the method for high-temperature oxydation; Then, on this oxide layer 7, form the nitration case 4 of one deck 100 dusts with the method for chemical vapour deposition (CVD).Described oxide layer 7 and nitration case 4 are as the insulating barrier of groove 2.The purpose of growth nitration case 4 is sidewall and the grown on top silicon epitaxy layers that prevent groove 2, and in addition, the sidewall and the top of protection groove 2 when the silicon epitaxy layer high-temperature oxydation of back prevent that the silicon of the sidewall of groove 2 and silicon chip 1 upper surface is oxidized.And oxide layer 7 can reduce the stress between silicon and the nitration case 4.

Step 3, referring to shown in Figure 4, at the upper surface resist coating of silicon chip 1, protect the top of groove 2 with photoresist; Adopt the method for each diversity dry etching that etching is carried out in groove 2 bottoms, remove the insulating barrier of groove 2 bottoms, the silicon of groove 2 bottoms is come out for follow-up growing epitaxial silicon; And then photoresist removed.

Step 4, referring to Fig. 5, utilize the selective epitaxial growth technology, bottom silicon area exposed grown silicon epitaxial loayer 5 at groove 2, the sidewall of groove and top (being the upper surface of silicon chip 1) be grown silicon epitaxial loayer 5 (be on the nitration case 4 not grown silicon epitaxial loayer 5) not, until silicon epitaxy layer 5 filling groove wholly or in part; The final thickness of silicon epitaxy layer 5 is lower than the top 0.44 μ m of groove 2 in the present embodiment.During grown silicon epitaxial loayer 5, the silicon source predecessor of growing epitaxial silicon is a kind of in silane, dichloro-dihydro silicon, trichlorosilane and the tetrachloro hydrogen silicon.The thickness of silicon epitaxy layer 5 is 0.045 μ m～5.0 μ m, and is less than or equal to the degree of depth of groove 2.

Step 5, in conjunction with shown in Figure 5, high-temperature oxydation is carried out at silicon epitaxy layer 5 tops, make the certain thickness silicon epitaxy layer 5 in its top be converted into silicon oxide layer 6; Form the silicon oxide layer 6 of 0.8 μ m thickness in the present embodiment by high-temperature oxydation at the top of silicon epitaxy layer 5.Groove 2 is by complete filling after carrying out high-temperature oxydation, and perhaps silicon oxide layer 6 is a little more than the top of groove 2, and promptly the thickness sum of the thickness of silicon epitaxy layer 5 and silicon oxide layer 6 is more than or equal to the degree of depth of groove 2.If silicon oxide layer 6 is higher than the top of groove 2, can it be polished with cmp, make the flattening surface of groove 2.

More than by specific embodiment the present invention is had been described in detail, specific implementation method and the parameter described in each step of embodiment only is for the ease of understanding the present invention, is not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. a method of filling the high aspect ratio trench quite isolated area is characterized in that, comprises the steps: to form groove on silicon chip or silicon epitaxy layer; Form oxide layer, nitration case successively in described flute surfaces; With the nitration case and the oxide layer of selective etch removal channel bottom, expose the silicon of channel bottom; With selective silicon epitaxy technique method grown silicon epitaxial loayer groove is filled; High-temperature oxydation is carried out at the silicon epitaxy layer top, make it be converted into silicon oxide layer.

2. the method for claim 1, it is characterized in that: the degree of depth of described groove is 0.1 μ m～5.0 μ m.

3. the method for claim 1 is characterized in that: the method formation of described oxide layer employing high-temperature oxydation.

4. the method for claim 1 is characterized in that: the method formation of chemical vapour deposition (CVD) of described nitration case.

5. the method for claim 1, it is characterized in that: described selective etch is the upper surface resist coating at described silicon chip, protects the top of groove with photoresist; Adopt the method for each diversity dry etching that described channel bottom is carried out etching, remove the oxide layer and the nitration case of described channel bottom, and then remove described photoresist.

6. the method for claim 1 is characterized in that: the silicon area growth that described silicon epitaxy layer only exposes at described channel bottom, grown silicon epitaxial loayer not on the described nitration case.

7. the method for claim 1 is characterized in that: when growing described silicon epitaxy layer, the silicon source predecessor of growing epitaxial silicon is a kind of in silane, a chlorine hydrogen silicon, dichloro-dihydro silicon, trichlorosilane and the tetrachloro hydrogen silicon.

8. the method for claim 1, it is characterized in that: the thickness of described silicon epitaxy layer is 0.045 μ m～5.0 μ m, and is less than or equal to the degree of depth of described groove.

9. the method for claim 1, it is characterized in that: the thickness sum of the thickness of described silicon epitaxy layer and silicon oxide layer is more than or equal to the degree of depth of described groove.

10. as claim 1 or 9 described methods, it is characterized in that: the part that adopts cmp to exceed when described silicon oxide layer is higher than described groove top is removed, and makes the flattening surface of described groove.