CN102054685B - Passivation layer dry etching method - Google Patents
Passivation layer dry etching method Download PDFInfo
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- CN102054685B CN102054685B CN2009101980970A CN200910198097A CN102054685B CN 102054685 B CN102054685 B CN 102054685B CN 2009101980970 A CN2009101980970 A CN 2009101980970A CN 200910198097 A CN200910198097 A CN 200910198097A CN 102054685 B CN102054685 B CN 102054685B
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Abstract
The invention discloses a passivation layer dry etching method. The method comprises the following steps: depositing a second passivation layer and a first passivation layer above an aluminum gasket at the surface of a silicon wafer, wherein the second passivation layer is positioned below the first passivation layer; etching the first passivation layer and the second passivation layer through plasma containing argon Ar; and stopping using Ar and continuing to etching the second passivation layer when the thickness of the second passivation layer is reduced to a pre-set thickness. Through the invention, the PID is reduced.
Description
Technical field
The present invention relates to the semiconductor fabrication techniques field, be specifically related to the passivation layer dry etching method.
Background technology
Etching refers to removes the interconnection material that is deposited on silicon chip surface selectively, to form the circuitous pattern that is generated by photoetching technique.Etching technics is divided into two kinds: dry etching and wet etching.Dry etching is to be exposed to the plasma that produces in the gaseous state to silicon chip surface, and the window of plasma through leaving in the photoresist with silicon chip generation physics and/or chemical reaction, thereby removes the surfacing that exposes to the open air.
In the metallization processes that semiconductor is made, for increase interconnecting metal as: the resistance to corrosion of aluminium can increase passivation layers usually above the aluminium pad; Be called first passivation layer and second passivation layer; Wherein, second passivation layer is positioned at first passivation layer below, like this; Before etching aluminium pad, need earlier first and second passivation layer to be carried out etching.Fig. 1 is existing passivation layer dry etching method flow chart, and as shown in Figure 1, its concrete steps are following:
Step 101: adopt CF
4, CHF
3, O
2With the Ar plasma first passivation layer and second passivation layer are carried out main etching.
First passivation layer can be silicon nitride (SiN) or tetraethyl silica (TEOS), and second passivation layer can be TEOS or SiN.
Wherein, the pressure of etch chamber is generally: 15-250 millitorr (mt), etching power is generally: 500-3500 watt (w), CF
4Flow be generally: 20-300 ml/min (sccm), CHF
3Flow be generally: 5-60sccm, O
2Flow be generally: 5-30sccm, the flow of Ar is generally: 50-800sccm; The etching duration is generally: 40-70 second (s).
Step 102: adopt CF
4, CHF
3, Ar and N
2Plasma carries out over etching to second passivation layer.
Wherein, the pressure of etch chamber is generally: 15-250mt, etching power is generally: 500-3500w, CF
4Flow be generally: 20-300sccm, CHF
3Flow be generally: 5-60sccm, the flow of Ar is generally: 50-800sccm, N
2Flow be generally: 10-200sccm; The etching duration is generally: 70-140s.
Step 103: silicon chip is placed in the short annealing device anneals.
The pressure of annealing device is generally: 5-30mt, and power is generally: 0-600w, the flow of the CO of use is generally: 50-300sccm, the flow of Ar is generally: 100-800sccm; The annealing duration is generally: 1-30s.
Fig. 2 has provided existing passivation layer dry etching procedure chart, has wherein provided the silicon chip structural representation before the etching, after the main etching completion, after the over etching completion respectively.
During etching, comprising band can ion, the plasma of electronics and excited molecule can cause the Sensitive Apparatus on the silicon chip is caused plasma-induced damage (PID, Plasma Induce Damage).The second passivation layer etching is considered to produce the basic reason of PID phenomenon; Owing to act on the aluminium pad in second passivation layer etching process ionic medium cognition; And be delivered to gate oxide through the copper interconnecting line of aluminium pad anterior layer, and gate oxide is damaged, make the gate oxide leakage current increase.
At present, perhaps increase the thickness of source electrode and drain electrode gate oxide usually through the energy that reduces plasma, reduce PID.The former shortcoming is: the reduction of energy of plasma will make the etching homogeneity of whole silicon wafer reduce.The latter's shortcoming is: though increase the thickness of the gate oxide of source electrode and drain electrode, can increase protection to source electrode and drain electrode,, the increase of gate oxide thickness will make cut-in voltage and electric current increase, making can't operate as normal under the normal working voltage.
Summary of the invention
The present invention provides a kind of passivation layer dry etching method, to reduce PID.
Technical scheme of the present invention is achieved in that
A kind of passivation layer dry etching method, deposit second passivation layer and first passivation layer above the aluminium pad of silicon chip surface, wherein, second passivation layer is positioned at first passivation layer below, and this method comprises:
The plasma that use comprises argon Ar carries out etching to first passivation layer and second passivation layer, when the thickness of finding second passivation layer drops to preset thickness, stops using Ar, continues second passivation layer is carried out etching.
Further comprise in the time of the said Ar of stopping using: reduce etching power.
The plasma that said use comprises Ar carries out etching to first passivation layer and second passivation layer and comprises:
Use comprises Ar and oxygen O
2Plasma first passivation layer is carried out etching, when the signal value of finding the etching product drops to preset value, with O
2Replace with nitrogen N
2, begin second passivation layer is carried out etching.
The signal value of said discovery etching product drops to preset value and comprises:
Adopt light emission spectrum to detect the signal value of product, and, the product signal is taken a sample according to preset sampling frequency; When finding in the first preset duration; The excursion of product signal is then confirmed the product signal stabilization in preset range the time, calculates the mean value of product signal in this duration; With this mean value as product signal criterion value; Continuation is taken a sample to the product signal, when finding the relative product signal criterion of product signal value value descends in the second preset duration percentage all the time greater than preset percentage, confirms that the signal value of etching product drops to preset value.
The span of said preset percentage is 10-30%.
The span of said preset thickness is: be not less than 1500 nanometers.
When said second passivation layer is positioned at aluminium pad corner when top of silicon chip center, the span of said preset thickness is: be not less than 1600 nanometers;
When said second passivation layer was positioned at the top, aluminium pad center of silicon chip center, the span of said preset thickness was: be not less than 1800 nanometers;
When said second passivation layer is positioned at aluminium pad corner when top at silicon chip edge place, the span of said preset thickness is: be not less than 1500 nanometers;
When said second passivation layer was positioned at the top, aluminium pad center at silicon chip edge place, the span of said preset thickness was: be not less than 1650 nanometers.
Said continuation is carried out etching to second passivation layer and is comprised:
Employing comprises N
2Plasma second passivation layer is carried out etching,
Wherein, the etch chamber pressure limit is: 100-500 millitorr mt, the etching power bracket is: 100-500 watt of w, N
2Range of flow be: 0-100 ml/min sccm; Etching duration scope is: 20-90 second.
Said use comprises Ar and oxygen O
2Plasma first passivation layer carried out etching comprise:
The pressure limit of the etch chamber of using is: 15-250mt, the etching power bracket is: 500-3500w, O
2Range of flow be: 5-30sccm, the range of flow of Ar is: 50-800sccm;
Said when the signal value of finding the etching product drops to preset value, with O
2Replace with nitrogen N
2, begin that second passivation layer is carried out etching and comprise:
When the signal value of finding the etching product dropped to preset value, the pressure limit of the etch chamber of employing was: 15-250mt, and the etching power bracket is: 500-3500w; The range of flow of Ar is: 50-800sccm, N
2Range of flow be: 10-200sccm.
Compared with prior art, among the present invention, when the thickness of finding second passivation layer drops to preset thickness, stop using Ar, continue second passivation layer is carried out etching.The present invention has reduced the physical bombardment to gate oxide, thereby has reduced PID.
Description of drawings
Fig. 1 is existing passivation layer dry etching method flow chart;
Fig. 2 is existing passivation layer dry etching process sketch map;
The passivation layer dry etching method flow chart that Fig. 3 provides for the embodiment of the invention;
The passivation layer dry etching process sketch map that Fig. 4 provides for the embodiment of the invention;
Fig. 5-1 is after silicon chip is adopted existing passivation layer dry etching method, when silicon chip is carried out the PID test, and the cumulative probability value of each sampled point;
Fig. 5-2 for the passivation layer dry etching method that silicon chip is adopted the embodiment of the invention and provide after, when silicon chip is carried out the PID test, the cumulative probability value of each sampled point.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is remake further detailed explanation.
The passivation layer dry etching method flow chart that Fig. 3 provides for the embodiment of the invention, in the present embodiment, first and second passivation layer is positioned at aluminium pad top, and second passivation layer is positioned at first passivation layer below, and as shown in Figure 3, its concrete steps are following:
Step 301: adopt CF
4, CHF
3, O
2With the Ar plasma first passivation layer is carried out main etching, when the signal value of finding the etching product drops to preset value, confirm that main etching finishes, beginning execution in step 302.
Wherein, the pressure of etch chamber is generally: 15-250mt, etching power is generally: 500-3500w, CF
4Flow be generally: 20-300sccm, CHF
3Flow be generally: 5-60sccm, O
2Flow be generally: 5-30sccm, the flow of Ar is generally: 50-800sccm.
Here, when first passivation layer was SiN, the etching product was the C-N accessory substance.Can adopt the signal value of light emission spectrum detection product, and according to preset sampling frequency for example: 5 times/second, the product signal is taken a sample; When find the first preset duration as: in 3 seconds, the excursion of product signal value is then confirmed the product signal stabilization in preset range the time; Calculate the mean value of product signal in this duration; This mean value as product signal criterion value, after this, is continued the product signal is taken a sample; When finding, to confirm the first passivation layer etching is finished during like: the percentage that the relative product signal criterion of product signal value value descends in 1 second all the time greater than preset percentage at the second preset duration.Here, the span of preset percentage is 10-30%.
Step 302: adopt CF
4, CHF
3, Ar and N
2Plasma carries out first order over etching to second passivation layer, when the residual thickness of finding second passivation layer reaches preset value, stops first order over etching.
Here, preset value is the value that is not less than 1500 nanometers.Wherein, Because the silicon chip center is more serious than the plasma bombardment that silicon chip edge place suffers; Aluminium pad center is more serious than the plasma bombardment that aluminium pad corner suffers; Therefore, second passivation layer that is positioned at the silicon chip center needs remaining thickness big than second passivation layer that is positioned at the silicon chip edge place, and second passivation layer that is positioned at top, aluminium pad center needs remaining thickness big than second passivation layer that is positioned at aluminium pad corner top.
Usually, for the silicon chip center, the residual thickness that is positioned at second passivation layer of aluminium pad corner top should be not less than 1600 nanometers, and the residual thickness that is positioned at second passivation layer of top, aluminium pad center needs to be not less than 1800 nanometers; For the silicon chip edge place, the residual thickness that is positioned at second passivation layer of aluminium pad corner top should be not less than 1500 nanometers, and the residual thickness that is positioned at second passivation layer of top, aluminium pad center should be not less than 1650 nanometers.
Wherein, the pressure of etch chamber is generally: 15-250mt, etching power is generally: 500-3500w, CF
4Flow be generally: 20-300sccm, CHF
3Flow be generally: 5-60sccm, the flow of Ar is generally: 50-800sccm, N
2Flow be generally: 10-200sccm.
Step 303: reduce etching power, and stop using Ar, adopt CF
4, CHF
3And N
2Plasma carries out second level over etching to second passivation layer.
Here, usually etching power is reduced to original 1/5-1/7.
Wherein, the pressure of etch chamber is generally: 100-500mt, power is generally: 100-500w, CF
4Flow be generally: 150-250sccm, CF
4Flow and CHF
3The ratio of flow be generally: 8-15, N
2Flow be generally: 0-100sccm; The etching duration is generally: 20-90s, get 55s usually.
Step 304: silicon chip is placed in the short annealing device anneals.
The pressure of annealing device is generally: 5-30mt, and power is generally: 0-600w, the flow of the CO of use is generally: 50-300sccm, the flow of Ar is generally: 100-800sccm; The annealing duration is generally: 1-30s.
Fig. 4 has provided the passivation layer dry etching process sketch map that the embodiment of the invention provides, and has wherein provided the silicon chip structural representation before the etching, after the main etching completion, after the completion of first order over etching, after the completion of second level over etching respectively.With Fig. 4 and Fig. 2 contrast, can find:
One, embodiment of the invention method is identical with the plasma of the main etching process use of existing method, all is: CF
4, CHF
3, O
2And Ar, the plasma that the first order over etching process of embodiment of the invention method and the over etching process of existing method are used is identical, all is CF
4, CHF
3, N
2And Ar.Difference is: only first passivation layer is carried out etching in the main etching process of the embodiment of the invention, in first order over etching process, just second passivation layer is carried out etching; And in the existing method, in the main etching process, simultaneously first and second passivation layer is carried out etching.Because the CF that uses in the main etching process
4, CHF
3, O
2Stronger with the physical bombardment property of Ar plasma, and the CF that uses in the first order over etching process
4, CHF
3, N
2With the physical bombardment property of Ar plasma relatively a little less than, therefore, in the embodiment of the invention, the main etching process is only carried out etching to first passivation layer, then can reduce the damage to gate oxide, thereby reduces PID.
Two, in the embodiment of the invention method, adopting CF
4, CHF
3, Ar and N
2When plasma carries out first order over etching, reach preset value, then reduce etching power and stop using Ar if find the residual thickness of second passivation layer; Reduce etching power and can reduce damage obviously gate oxide; Thereby reduce PID, and because the Ar molecule is bigger, and physical bombardment property is stronger; Therefore, stop using Ar also can reduce PID.
After the etching of accomplishing silicon chip; Can carry out the PID test to silicon chip, the PID test process is: on silicon chip, add predeterminated voltage, test the leakage current of each sampled point then; Leakage current value is carried out logarithm operation, with the PID test cumulative probability of the value that obtains as this point.For example: if the leakage current of a sampled point is 10
-12Peace, then its PID test cumulative probability is :-lg10
-12%=12%.Usually, if the PID of sampled point test cumulative probability＜10.5%, then think PID test crash to this point.
After Fig. 5-1 has provided silicon chip has been adopted existing passivation layer dry etching method, when silicon chip is carried out the PID test, the cumulative probability value of each sampled point.
After Fig. 5-2 has provided the passivation layer dry etching method that the silicon chip employing embodiment of the invention is provided, when silicon chip is carried out the PID test, the cumulative probability value of each sampled point.
It is thus clear that, adopt existing passivation layer dry etching method, have the point of not testing on the silicon chip, and these some distributions disperse through PID.And behind the passivation layer dry etching method that the employing embodiment of the invention provides, do not have the point of not testing on the silicon chip through PID.
The above is merely process of the present invention and method embodiment, in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being made, is not equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. passivation layer dry etching method, deposit second passivation layer and first passivation layer above the aluminium pad of silicon chip surface, wherein, second passivation layer is positioned at first passivation layer below, and this method comprises:
The plasma that use comprises argon Ar carries out etching to first passivation layer and second passivation layer, when the thickness of finding second passivation layer drops to preset thickness, stops using Ar, continues second passivation layer is carried out etching;
The plasma that said use comprises Ar carries out etching to first passivation layer and second passivation layer and comprises: use to comprise Ar and oxygen O
2Plasma first passivation layer is carried out etching, when the signal value of finding the etching product drops to preset value, with O
2Replace with nitrogen N
2, begin second passivation layer is carried out etching.
2. the method for claim 1 is characterized in that, further comprises in the time of the said Ar of stopping using: reduce etching power.
3. the method for claim 1 is characterized in that, the signal value of said discovery etching product drops to preset value and comprises:
Adopt light emission spectrum to detect the signal value of product, and, the product signal is taken a sample according to preset sampling frequency; When finding in the first preset duration; The excursion of product signal is then confirmed the product signal stabilization in preset range the time, calculates the mean value of product signal in this duration; With this mean value as product signal criterion value; Continuation is taken a sample to the product signal, when finding the relative product signal criterion of product signal value value descends in the second preset duration percentage all the time greater than preset percentage, confirms that the signal value of etching product drops to preset value.
4. method as claimed in claim 3 is characterized in that, the span of said preset percentage is 10-30%.
5. according to claim 1 or claim 2 method is characterized in that the span of said preset thickness is: be not less than 1500 nanometers.
6. method as claimed in claim 5 is characterized in that,
When said second passivation layer is positioned at aluminium pad corner when top of silicon chip center, the span of said preset thickness is: be not less than 1600 nanometers;
When said second passivation layer was positioned at the top, aluminium pad center of silicon chip center, the span of said preset thickness was: be not less than 1800 nanometers;
When said second passivation layer is positioned at aluminium pad corner when top at silicon chip edge place, the span of said preset thickness is: be not less than 1500 nanometers;
When said second passivation layer was positioned at the top, aluminium pad center at silicon chip edge place, the span of said preset thickness was: be not less than 1650 nanometers.
7. according to claim 1 or claim 2 method is characterized in that said continuation is carried out etching to second passivation layer and comprised:
Employing comprises N
2Plasma second passivation layer is carried out etching,
Wherein, the etch chamber pressure limit is: 100-500 millitorr mt, the etching power bracket is: 100-500 watt of w, N
2Range of flow be: 0-100 ml/min sccm; Etching duration scope is: 20-90 second.
8. the method for claim 1 is characterized in that,
Said use comprises Ar and oxygen O
2Plasma first passivation layer carried out etching comprise:
The pressure limit of the etch chamber of using is: 15-250mt, the etching power bracket is: 500-3500w, O
2Range of flow be: 5-30sccm, the range of flow of Ar is: 50-800sccm;
Said when the signal value of finding the etching product drops to preset value, with O
2Replace with nitrogen N
2, begin that second passivation layer is carried out etching and comprise:
When the signal value of finding the etching product dropped to preset value, the pressure limit of the etch chamber of employing was: 15-250mt, and the etching power bracket is: 500-3500w; The range of flow of Ar is: 50-800sccm, N
2Range of flow be: 10-200sccm.
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| CN110060927A (en) * | 2019-04-22 | 2019-07-26 | 上海华力微电子有限公司 | The preparation method of semiconductor structure |
| CN116169226A (en) * | 2022-12-08 | 2023-05-26 | 江西兆驰半导体有限公司 | Etching method for Bragg reflection layer through hole in flip LED chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5960306A (en) * | 1995-12-15 | 1999-09-28 | Motorola, Inc. | Process for forming a semiconductor device |
| CN1495854A (en) * | 2002-09-11 | 2004-05-12 | ���µ�����ҵ��ʽ���� | Image forming method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5960306A (en) * | 1995-12-15 | 1999-09-28 | Motorola, Inc. | Process for forming a semiconductor device |
| CN1495854A (en) * | 2002-09-11 | 2004-05-12 | ���µ�����ҵ��ʽ���� | Image forming method |
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| JP特开2003-51443A 2003.02.21 |
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