CN102045133A - Chip for wireless sensor network node and on-chip digital baseband system - Google Patents
Chip for wireless sensor network node and on-chip digital baseband system Download PDFInfo
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Abstract
The invention provides a digital baseband system used for a wireless sensor network node chip. The digital baseband system comprises a baseband modulation unit, a baseband demodulation unit, an automatic gain control unit and a cyclic code checker, wherein the cyclic code checker transmits checked data to be sent to the baseband modulation unit; the baseband modulation unit performs modulation processing such as direct sequence spread spectrum, delay, digital signal shaping modulation and analog-to-digital conversion on the data and then sends the processed data out; the baseband demodulation unit performs demodulation processing such as analog-to-digital conversion, spectrum despreading, optimal coherent demodulation, bit synchronization sampling determination on the received data and then transmits the processed data to the cyclic code checker for data check; and the automatic gain control unit adjusts a gain determination threshold according to received signal strength indication (RSSI) and link quality indication (LQI) in the process of sending or receiving the data so as to control the transmitting gain and receiving gain.
Description
Technical Field
The invention relates to the field of wireless transmission, in particular to a chip for a wireless sensor network node and a digital baseband system on the chip.
Background
A Wireless Sensor Network (WSN) is a self-organizing Network application system formed by a large number of autonomous nodes densely deployed in a monitoring area. The method has wide application prospect, and can be widely applied to the fields of military affairs, environmental monitoring, medical health, traffic management, commercial application and the like. Although various applications exist in wireless sensor network nodes, the applications have the same requirements on the wireless sensor network nodes, and the most challenging requirements are how to make the wireless sensor network nodes have stronger computing power, wider application environment, lower power consumption, smaller size, lower cost and better communication quality.
Most of the current wireless sensor network nodes are realized by adopting a general embedded platform. Because the devices of the sensor network nodes are not specially designed for the wireless sensor network, the indexes such as processing capacity, power consumption and volume are often difficult to meet the requirements of practical application. With the development of the FPGA/ASIC technology and the emergence of the System on chip (System on chip) technology, a design method of implementing a wireless sensor network node platform on the FPGA by using the System on chip method and converting the wireless sensor network node platform into ASIC mass production in large-scale application becomes a key technical means for solving the problems of node processing capability, power consumption, volume and the like.
The signal acquisition, the signal processing and the networking communication are three functions of the wireless sensor network node. According to the functions, the wireless sensor network node is generally composed of a sensing module, a processing module, a wireless communication module and an energy module, the wireless communication module occupies most of the power consumption of the whole wireless sensor network node, the digital baseband in the wireless communication module plays the roles of controlling radio frequency transceiving gain, channel coding and decoding, inhibiting and controlling radio frequency carrier leakage, forming and modulating digital signals, optimal coherent demodulation, bit synchronization, sampling judgment and the like in the wireless communication module, these all affect the power consumption, performance, hardware cost and bit error rate of the wireless sensor network node, therefore, designing a digital baseband system with low power consumption, high performance and low bit error rate plays an important role in reducing the power consumption and hardware cost of the wireless sensor network node, improving the node communication quality and enhancing the adaptability of the node to the environment.
In order to meet the design goals of low power consumption and low cost of wireless sensor network nodes, the ZigBee alliance provides a ZigBee protocol for a WSN, so that the protocol becomes an emerging communication standard of a wireless sensor network. A physical layer (PHY) and a medium access layer (MAC) of the protocol are formulated by an IEEE802.15.4 working group, two frequency bands of 900MHz and 2.4GHz are defined in the IEEE802.15.4 standard formulated by the working group, 16 frequency channels are defined in the range of 2.405GHz-2.480GHz, the channel interval is 5MHz, the modulation mode is O-QPSK, the data transmission rate is 250Kb/s, a Direct Sequence Spread Spectrum (DSSS) technology based on a pseudo-random noise (PN) code is adopted, and the spread spectrum gain is 8. The application of the communication protocol is beneficial to the mutual communication among the wireless sensor network nodes generated by different manufacturers, the reduction of the power consumption and the cost of the wireless sensor network nodes and the popularization and the application of the wireless sensor network.
However, in the prior art, most of wireless sensors implemented by the system-on-chip design method use respective established communication standards, and digital baseband systems in the sensors are rarely designed according to the ieee802.15.4 standard. For example, although a wireless sensor network node WiseNet developed by CMES in switzerland adopts a technology of a system on chip and is specially designed for a wireless sensor network, a digital baseband in the node adopts 2FSK modulation, the highest data rate is 100kb/s, and the maximum data rate does not accord with the standard of ieee802.15.4, so that the chip does not have the universality of being compatible with other sensor network node chips which accord with the ieee802.15.4 standard.
In the prior art, digital baseband systems conforming to the ieee802.15.4 standard also exist, such as the digital baseband systems in the series of chips CC2431 and CC2510 of Chipcon corporation and JN5121 of JENNIC corporation, but the chips including these digital baseband systems still have certain limitations, including:
1. the digital baseband system of the chips can perform automatic gain control, the gain range can be configured through software, but the decision threshold involved in the automatic gain control process adopts a fixed threshold value and does not have the characteristic of self-adaptive adjustment. And the signal strength RSSI is generally adopted as a feedback value to control, the signal is amplified to saturation, and the receiving link quality LQI is rarely considered comprehensively. The narrow-band interference in the channel increases the RSSI but decreases the link quality LQI, so that it is inaccurate to use a single RSSI as feedback to adjust the reception gain. Considering the actual situation that the application environment of the wireless sensor network node is wide, in the actual application process, the problems of complex and variable channel conditions, uncertain transmission power, real-time change of communication distance and the like can be faced, which all affect the packet loss rate and energy consumption of the node, and the environmental adaptability of the node is reduced due to the adoption of a fixed threshold value judgment mode in the existing digital baseband system.
2. The digital baseband system of these chips does not adopt a schmitt trigger mode of a self-adaptive threshold when performing signal phase decision, but adopts a traditional zero-crossing trigger mode to perform signal phase decision, so that the increase of demodulation error rate caused by frequent jump of input phase cannot be avoided.
3. The digital baseband system of the chips adopts a fixed generator polynomial instead of software configurable when cyclic code check is carried out, so that the flexibility and the universality of the baseband are not strong.
4. The digital baseband system of the chips has no function of inhibiting carrier leakage, so the requirement on the quality of the radio frequency chip is high, and the node cost is increased.
Disclosure of Invention
An object of the present invention is to provide a digital baseband system capable of adaptively adjusting a decision threshold value for automatic gain control.
Another object of the present invention is to overcome the defect of an increased demodulation error rate caused by frequent jumps of an input phase in signal phase decision, thereby providing a digital baseband system capable of reducing the demodulation error rate.
It is a further object of this invention to provide a digital baseband system including a user configurable cyclic code checker that enhances the flexibility and versatility of the digital baseband.
It is a further object of the present invention to provide a digital baseband system including an automatic rf carrier leakage suppression circuit that reduces the quality requirements for rf chips and reduces the node cost.
In order to achieve the above object, the present invention provides a digital baseband system for a wireless sensor network node chip, comprising a baseband modulation unit, a baseband demodulation unit, an automatic gain control unit and a cyclic code checker; wherein,
the cyclic code checker transmits checked data to be transmitted to the baseband modulation unit, the baseband modulation unit completes modulation processing including direct sequence spread spectrum, delay, digital signal shaping modulation and analog-to-digital conversion, and then the processed data is transmitted;
the baseband demodulation unit carries out demodulation processing including analog-to-digital conversion, despreading, optimal coherent demodulation and bit synchronous sampling judgment on received data, and then transmits the processed data to the cyclic code checker for data check;
the automatic gain control unit adjusts the gain decision threshold according to the signal strength RSSI and the link quality LQI in the data receiving process, and the control of the transmitting gain and the receiving gain is realized by matching the working mode of software and hardware cooperation.
In the technical scheme, the device also comprises a carrier leakage restraining unit which is used for automatically monitoring the carrier leakage power, compensating and restraining the carrier leakage of the transmitting terminal; the unit is connected to an external transmitter.
In the above technical solution, the baseband modulation unit includes a direct sequence spread spectrum module, a delay module, an O-QPSK digital modulation module, a first digital-to-analog conversion module, and a second digital-to-analog conversion module; wherein,
the direct sequence spread spectrum module carries out spread spectrum coding on data to be sent according to a direct sequence spread spectrum coding table and converts the data after the spread spectrum coding into I, Q two paths of serial data; the delay module delays Q paths of data; the I, Q two paths of serial data are both shaped and modulated in the O-QPSK digital modulation module, and then are respectively analog-to-digital converted in the first digital-to-analog conversion module and the second digital-to-analog conversion module.
In the above technical solution, the O-QPSK digital modulation module is implemented by using two ROM memories respectively storing sine and cosine waveform code tables.
In the above technical solution, the baseband demodulation unit includes a first analog-to-digital conversion module, a second analog-to-digital conversion module, a first matched filter module, a second matched filter module, a third matched filter module, a fourth matched filter module, a first bit synchronization module, a second bit synchronization module, and a spread spectrum demodulation module; wherein,
the first analog-to-digital conversion module and the second analog-to-digital conversion module respectively convert an I path signal and a Q path signal of a received analog waveform signal into a waveform level digital signal; the first matched filter module, the second matched filter module, the third matched filter module and the fourth matched filter module respectively carry out filtering operation on signals, eliminate intersymbol interference of received signals and carry out optimal coherent demodulation on the signals; the filtered signals are integrated and compared to obtain output signals at the decision time, sampling decision pulses are extracted through the first bit synchronization module and the second bit synchronization module to carry out sampling decision, and demodulation results are output to the spread spectrum demodulation module; the spread spectrum demodulation module decodes the received chip code subjected to spread spectrum modulation into a data code stream and obtains a link quality LQI value at the same time; the strength RSSI of the aforementioned filtered signal and the link quality LQI value are transmitted to the automatic gain control module.
In the technical scheme, the first matched filter module, the second matched filter module, the third matched filter module and the fourth matched filter module are realized by circuit multiplexing, the calculation amount completed in one clock cycle is divided into a plurality of clock cycles to be completed by high-frequency clock driving, and a large number of parallel combinational logic circuits are divided into a small number of sequential logic circuits.
In the above technical solution, the first bit synchronization module and the second bit synchronization module adopt a schmitt trigger with a self-adaptive threshold to perform signal phase decision; wherein,
when the phase decision outputs 1, the output of the next time is 0 only when the output signal of the matched filter is greater than the threshold, otherwise, 1 is output; when the phase decision outputs 0, the output of the next time is 1 only when the output signal of the matched filter is smaller than the threshold, otherwise, 0 is output.
In the above technical solution, the threshold value in the schmitt trigger of the adaptive threshold is adaptively adjusted according to the RSSI, and the user dynamically configures the decision coefficient according to the channel environment.
In the above technical solution, the gain decision threshold of the automatic gain control unit is (k-1)/k of the maximum value of LQI and RSSI, where k represents a decision coefficient;
the automatic gain control unit has four states in the process of realizing gain control: an initial state, a locked state, an increased gain state, and a decreased gain state; in any state, when LQI is smaller than (k-1)/k of the maximum value and RSSI is smaller than (k-1)/k of the maximum value, entering a gain increasing state from the current state; in any state, when LQI is less than (k-1)/k of the maximum value and RSSI is greater than (k-1)/k of the maximum value, entering a gain reduction state from the current state; in any state, entering a locked state when LQI is greater than (k-1)/k of its maximum value; when the values of LQI and RSSI are both larger than the respective historical values, the LQI and RSSI are out of the locking state, the corresponding values are stored in a maximum value register, then the LQI and RSSI enter the initial state, and gain adjustment is carried out again until the LQI and RSSI are in the locking state.
In the above technical solution, the threshold initial value, the gain initial value and the decision coefficient k of the automatic gain control unit are all set by a user.
In the above technical solution, the polynomial coefficient generated by the cyclic code checker is configured according to the user requirement.
In the above technical solution, the carrier leakage suppression module includes an AD sampling unit, a low-pass filtering unit, a sliding window integrating unit, and a dc compensation algorithm unit; the baseband signal is subjected to AD sampling by the AD sampling unit, low-pass filtering by the low-pass filtering unit and integration by the sliding window integrating unit in sequence to obtain the direct current intensity of the transmitting signal, and the direct current compensation algorithm unit generates a compensation value for inhibiting carrier leakage according to the direct current intensity of the transmitting signal.
The invention also provides a chip for the wireless sensor network node, which comprises the digital baseband system.
The invention has the advantages that:
1. the digital baseband system adopts an automatic gain control mechanism based on the self-adaptive threshold of the comprehensive feedback of the signal strength RSSI and the link quality LQI in the gain control, and achieves the purposes of reducing the node error rate and saving the power consumption on the premise of ensuring certain communication quality, thereby being suitable for complex and changeable application environments.
2. The digital baseband system can support the IEEE802.15.4 communication protocol standard, so that a chip adopting the digital baseband system is compatible with other electronic devices supporting the IEEE802.15.4 communication protocol standard.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a sensor network node chip including a digital baseband system;
FIG. 2 is a schematic diagram of a baseband modulation unit in a digital baseband system;
fig. 3 is a schematic structural diagram of a baseband demodulation unit and an automatic gain control unit in a digital baseband system;
FIG. 4 is a schematic diagram of a matched filter in a digital baseband system;
FIG. 5 is a diagram illustrating a bit synchronization module in a digital baseband system to implement phase decision;
FIG. 6 is a state transition diagram of an AGC unit in a digital baseband system;
FIG. 7 is a block diagram of a cyclic code checker in a digital baseband system;
FIG. 8 is a schematic diagram of another embodiment of a sensor network node chip including a digital baseband system;
fig. 9 is a block diagram of a carrier leakage suppression module.
Detailed Description
The invention is described below with reference to the accompanying drawings and the detailed description.
Fig. 1 shows an embodiment of a chip for a wireless sensor network node according to the present invention, and the structure of the chip is described below with reference to fig. 1. As can be seen from the figure, the chip of the invention comprises a processor 1, a program memory 2, a data memory 3, a MAC protocol module 4, a digital baseband module 5, a radio frequency module 6 and other modules 7. The processor 1 is connected with the data memory 3, the MAC protocol module 4, the digital baseband module 5, the wireless radio frequency module 6 and other modules 7 through a bus, and the processor 1 is connected with the program memory 2 through a program reading line; the MAC protocol module 4 is connected with the digital baseband module 5 through a bidirectional data line, and a data transceiving path is also established between the digital baseband module 5 and the wireless radio frequency module 6 through a data line. The specific functions and implementations of the various components in the chip are described below.
The processor 1 is a logic device which completes corresponding operations according to the program codes in the program memory 2, and can be implemented by selecting the existing IP module or open source codes, such as MC8051 processor source codes of Oregano Systems, ARM series processor modules and the like. The processor 1, under the control of the program code, performs various operations including initialization setting and control on other components in the chip, and in the following description of the other components, when the processor 1 is referred to, a detailed description will be given of specific functions of the processor 1.
The program memory 2 is used for storing programs to be run by the processor 1. The program memory 2 can be realized by using a mature process design method such as FLASH or EEPROM.
The data memory 3 is used for storing data to be used by the processor 1, and can be implemented by using a well-established DRAM or SRAM technology.
The MAC protocol module 4 sets the operating frequency, sleep mode, collision avoidance mechanism, transmission power, and channel selection of the radio frequency module 6 under the control of the processor 1, and the processor 1 configures the objects to be transmitted and received and the allocation of the operating sleep time, thereby completing the analysis of the data packet, the judgment of the channel occupancy, the random collision backoff, and the like. The MAC protocol module 4 may be implemented using any IP module in the prior art that conforms to the ieee802.15.4 communication standard or other MAC protocols.
The radio frequency module 6 is used for modulating and transmitting the analog part of the wireless transmission data and demodulating and receiving the analog part of the wireless reception data. The module comprises a transmitting unit 61, a receiving unit 62. An existing IP module implementation conforming to the ieee802.15.4 communication standard may be selected.
The other modules 7 are used for implementing various functions including power supply control, sensor control, input and output, and can also be implemented by the prior art.
The digital baseband module 5 has a plurality of functions such as controlling the radio frequency transceiving gain, direct sequence spread spectrum, digital signal shaping modulation, digital-to-analog/analog-to-digital conversion, despreading, bit synchronization sampling judgment, cyclic code check, and the like. The digital baseband module 5 can be further divided according to its above-mentioned functions, and one implementation of the digital baseband module 5 is given in fig. 1, which includes a baseband modulation unit 51, a baseband demodulation unit 52, an automatic gain control unit 53, and a cyclic code checker 54. After receiving data from the MAC protocol module 4, the cyclic code checker 54 connected to the MAC protocol module 4 through a data line sends the checked data to the baseband modulation unit 51, and the baseband modulation unit 51 sends the modulated data to the radio frequency module 6 and transmits the modulated data through the radio frequency module 6. After receiving the data, the radio frequency module 6 sends the received data to the baseband demodulation unit 52 for data demodulation, sends the demodulated data to the cyclic code checker 54 for data check, sends the checked data to the MAC protocol module 4, and during the data demodulation, realizes the automatic gain adjustment through the automatic gain control unit 53. The digital baseband module 5 of the present invention, when implemented, satisfies the ieee802.15.4 standard, and the detailed structure and operation principle of each unit involved in the module will be separately explained in the following description.
Fig. 2 shows a schematic structural diagram of the baseband modulation unit 51, and the baseband modulation unit 51 should perform various operations including direct sequence spreading, delay, digital signal shaping modulation, and analog-to-digital conversion according to the relevant provisions of the ieee802.15.4 standard. According to the above function, the unit includes a direct sequence spreading module 511, a delay module 512, an O-QPSK digital modulation module 513, and digital-to-analog conversion (DAC) modules 514, 515.
The direct sequence spread spectrum module 511 implements code table transformation of the transmitted data, and specifically, performs one-to-one mapping spread spectrum coding on 4-bit 2-ary data according to a direct sequence spread spectrum coding table provided by the ieee802.15.4 communication standard, and the obtained codes are pseudo-random noise codes and are mutually orthogonal. The direct sequence spread spectrum module 511 may be implemented by using a ROM, and after receiving the serial data from the MAC protocol module 4, performs serial-parallel conversion on the serial data, reads a corresponding code pattern from a direct sequence spread spectrum coding table stored in the ROM, converts the data stream into a 2-system chip code sequence through 8-fold spread spectrum gain, and finally converts the data stream into I, Q two-way serial data by using an FIFO.
The delay module 512 delays the Q-path signal by T/2(T represents a symbol period) compared with the I-path signal, the delayed Q-path serial data is transmitted to the O-QPSK modulation module 513, and the I-path signal is directly transmitted to the O-QPSK modulation module 513 without passing through the delay module 512.
The O-QPSK digital modulation module 513 is configured to perform a shaping modulation on the digital signal. The O-QPSK digital modulation module 513 may use a shaping filter to implement shaping modulation on the digital signal, but in this embodiment, as a preferred implementation manner, the O-QPSK digital modulation module 513 may use two ROM memories respectively storing sine and cosine waveform code tables, and when performing shaping modulation, directly output the filtered level from the waveform code table according to the modulation code pattern. Compared with the implementation mode adopting the forming filter, the implementation mode can save the forming filter, can reduce unnecessary energy consumption and hardware overhead as much as possible, and meets the requirements of low cost and low power consumption of the sensor network node.
The DAC modules 514 and 515 respectively perform analog-to-digital conversion on the I-path signal and the Q-path signal, and convert the modulated waveform level digital signal into an analog waveform signal. The DA module may be implemented by using an independent IP unit or a general DA chip, and as a preferred implementation manner, in this embodiment, the DA module uses an independent IP unit.
Fig. 3 shows a schematic diagram of the structures of the baseband demodulation unit 52 and the automatic gain control unit 53. The baseband demodulation unit 52 should perform various operations including analog-to-digital conversion, despreading, optimal coherent demodulation, and bit synchronization sampling decision, and according to the above functions, the baseband demodulation unit 52 includes analog-to-digital conversion (ADC) modules 521 and 522, matched filter modules 523, 524, 525 and 526, bit synchronization modules 527 and 528, and a spread spectrum demodulation module 529.
The ADC modules 521 and 522 convert the I-path signal and the Q-path signal of the analog waveform signal demodulated by the radio frequency module 6 into waveform level digital signals, respectively. Similar to the aforementioned DA module, the AD module can also be implemented by using a separate IP unit or a general AD chip, and as a preferred implementation, in this embodiment, a separate IP unit is used.
Matched filters 523, 524, 525, 526 respectively filter the signals to remove intersymbol interference of the received signals and perform optimal coherent demodulation. The filtered result is passed through an integrator and a comparator to obtain an output signal s _ diff at the decision time y1-y0, and then the sampling decision pulse is extracted by the bit synchronization modules 527 and 528 to perform sampling decision, and the demodulation result is output to the spread spectrum demodulation module 529. In the process, the strength of the signal passing through the matched filter is also obtained, and the strength value is obtained as RSSI y1+ y0, and this strength value is output as feedback to the automatic gain control module 53 to realize gain control. When the signal intensity is calculated, matched filtering is firstly carried out, which is beneficial to shielding background noise, so that more accurate received signal intensity is obtained.
As can be seen from the above description, the matched filter functions to implement the filtering operation on the signal, and thus the related filter in the prior art can be theoretically used in the present invention. However, in consideration of the characteristics of low cost and low power consumption required by the wireless sensor network node, fig. 4 shows a preferred implementation manner of the matched filter in hardware. As can be seen from the figure, in this implementation, according to the idea of circuit multiplexing, the high-frequency clock driving is adopted, the computation amount completed in one clock cycle is divided into a plurality of clock cycles, and the parallel large number of combinational logic circuits are divided into a small number of sequential logic circuits, and these sequential logic circuits are multiplexed for a plurality of cycles, so as to implement the same computation function, so as to reduce the number of hardware implementation units, such as reducing multipliers and adders, and achieve the purpose of reducing the hardware resource overhead while ensuring the performance of the linear filter. As in one example, assuming a 24MHz AD sampling rate, the chip rate is 2MHz, so 12 multiply-add operations are performed per sample period, requiring 12 adders and multipliers if parallel calculations are to be made. Through multiplex design, a clock with the sampling frequency being 6 times that of the matched filter module is adopted to drive the matched filter module, 6 clock cycles are calculated in one sampling cycle, only two adders and multipliers are used in each cycle, the filter is realized by using the least multipliers and adders, compared with the traditional parallel filter, the hardware resource of 5/6 is saved, the purpose of reducing the hardware cost is realized, and the requirement of low cost of a sensor network node is met.
The bit synchronization module is used for adjusting the phase of the local synchronous sampling pulse of the receiving end to be consistent with the phase of the received demodulation signal, so that the demodulation signal can be accurately sampled. In the prior art, when the bit synchronization module determines the phase of the received demodulation signal, a method of directly performing zero-crossing detection on the output of the matched filter is used to determine the phase of the output demodulation signal. Because the shape of a signal (including frequency, phase, amplitude, arrival time and the like) needs to be completely known to achieve an ideal optimal receiving condition when a matched filter is designed, in practical application, any problem of frequency error, random phase, random amplitude, inaccurate timing and the like can cause that the optimal receiving condition of the matched filter cannot be met, so that the output of the matched filter is subjected to multiple zero-crossing triggers at zero-crossing positions, bit synchronization input can frequently jump between 0 and 1 states, the bit synchronization effect is influenced, and the demodulation error rate is increased.
In view of the above-mentioned shortcomings of the prior art in implementing bit synchronization modules, fig. 5 shows a way of using a schmitt trigger adaptive to thresholds to perform signal phase decision, thereby avoiding frequent jumps of the input phase. In this implementation, when the current phase decision outputs 1, the next output is 0 only when the filter output signal is greater than the threshold, otherwise, 1 is output, and when the current phase decision outputs 0, the next output is 1 only when the filter output signal is less than the threshold, otherwise, 0 is output. Because the wireless sensor network node needs to adapt to various complex communication environments, the optimal receiving condition cannot be met under the severe communication environment, and the amplitude of the output signal of the matched filter is smaller than that under the normal condition, the threshold value during phase judgment should be self-adaptive and adjustable so as to avoid phase judgment errors. Specifically, the decision threshold is adaptively adjusted by using the aforementioned signal strength value RSSI as a feedback value, and the decision coefficient k can be dynamically configured according to the channel environment, so as to achieve higher controllability and flexibility. It can be seen from the figure that when the current phase decision outputs 1, the next output is 0 only when the filter output signal s _ diff is greater than k times of the RSSI, otherwise, 1 is output, when the current phase decision outputs 0, the next output is 1 only when the filter output signal s _ diff is less than-k times of the RSSI, otherwise, 0 is output. The judgment method can ensure that the judgment threshold changes in real time according to the signal intensity, ensure the accuracy of the judgment result, ensure that the error rate of the system is not obviously reduced due to the severe environment, and meet the requirement of being suitable for various communication environments. After the phase of the demodulation signal is obtained, the invention adopts a digital phase-locking method to carry out bit synchronization. The error is compared with the output signal s _ diff of the matched filter obtained from the comparator, and one or more pulses are added or subtracted in the pulse sequence output by the signal clock by a controller, so as to achieve the purpose of synchronizing the output sampling decision signal with the received signal. The bit synchronization pulse and the 2-ary chip code sequence finally obtained by the bit synchronization module are input into the spread spectrum demodulation module 529 for correlation demodulation.
The spread spectrum demodulation module 529 is configured to decode the received chip code subjected to spread spectrum modulation into a data code stream. According to the IEEE802.15.4 protocol, direct sequence spreading is to map every 4 bits of data into one symbol to select 16 quasi-orthogonal pseudo-random sequences, each consisting of 32-bit chip codes. Each 32-bit code is divided into I, Q two paths of 16-bit sub-codes. Because of the orthogonality of the 16 pseudorandom sequences, the small cross-correlation coefficient and the large autocorrelation coefficient, the spread spectrum demodulation module 529 firstly performs correlation operation on the I path of the received signal and the I path of each symbol, extracts the maximum value according to the maximum likelihood criterion, performs correlation operation on the maximum value and the Q path signal, and performs symbol judgment on the correlation result to obtain corresponding decoded 4-bit data. And in the decoding process, the correlation coefficient between the chip code of each piece of received data and the original chip code during decoding is counted at the same time, the higher the correlation coefficient is, the better the link quality performance of the channel is, and the average value of the correlation coefficients is mapped into a link quality LQI value. The data code stream obtained after the spread spectrum demodulation is sent to the cyclic code checker 54, and the calculated LQI value is sent to the automatic gain control unit 53.
The automatic gain control unit 53 includes transmission gain control and reception gain control. In the transmission gain control, a user adjusts the transmission gain through software according to the link quality LQI, a processor 1 pays a value to a configuration register, and an MAC protocol module 4 reads at the time of sending preprocessing. In the receiving gain control, the gain decision threshold is adjusted based on the comprehensive feedback result of the signal strength RSSI and the link quality LQI of the received signal. The implementation of the method is described below with reference to fig. 6.
How the signal strength RSSI and the link quality LQI are obtained has already been described in the foregoing description, and a description thereof is not repeated. And (k-1)/k of the maximum value of the LQI and the RSSI is respectively used as a gain decision threshold, wherein k represents a decision coefficient and can be set by a user. As can be seen from fig. 6, there are four states in the gain control process: initial state, locked state, increased gain state, decreased gain state. In any state, when LQI is smaller than (k-1)/k of the maximum value and RSSI is smaller than (k-1)/k of the maximum value, entering a gain increasing state from the current state; in any state, when LQI is less than (k-1)/k of the maximum value and RSSI is greater than (k-1)/k of the maximum value, entering a gain reduction state from the current state; in any state, entering a locked state when LQI is greater than (k-1)/k of its maximum value; when the values of LQI and RSSI are both larger than the respective historical values, the LQI and RSSI are out of the locking state, the corresponding values are stored in a maximum value register, then the LQI and RSSI enter the initial state, and gain adjustment is carried out again until the LQI and RSSI are in the locking state. In addition, before the gain decision threshold is adaptively adjusted, the threshold initial value and the gain initial value can be set by a user, so that the system can be suitable for various communication environments according to requirements.
Compared with the existing automatic gain control method, in the method shown in fig. 6, the threshold of automatic gain control is adaptive to the received signal strength RSSI and link quality LQI after passing through the matched filter, so that the decision threshold for determining the optimal value of gain changes with the changes of the channel environment, the transmission power and the communication distance. When the channel environment is good, the transmitting power is large and the communication distance is short, the RSSI and the LQI are increased, the gain is reduced, the judgment threshold is increased, signals cannot be amplified to saturation, and certain receiving power consumption is saved. When the channel environment is poor, the transmitting power is small and the communication distance is long, the RSSI and the LQI are reduced, the gain is increased, the judgment threshold is reduced, the better received signal quality is obtained, and the packet loss rate of the node is reduced. In addition, according to actual measurement results, in a region where the RSSI is within 10m, the fading trend of the RSSI with distance is approximately the same as the link quality LQI, but when the distance is increased, the fading curve of the RSSI is relatively flat and is obviously higher than that of the LQI, and the fading curve of the LQI increases and oscillates with the increase of the distance and has larger irregular fading. This phenomenon indicates that the influence of multipath interference, diffraction and obstacles on the signal quality is significantly higher than the influence on the signal strength when the distance is increased, and the RSSI may not change significantly when the received signal is saturated due to large received gain, but because the saturated signal exceeds the linear range of AD, the demodulation code rate is increased and the LQI is decreased, so that it is inaccurate to adopt a single RSSI as the feedback to adjust the received gain. On the other hand, because the oscillation change of the LQI along with the distance is larger, and the system stability is poorer again due to the fact that the single LQI is adopted as the feedback adjustment receiving gain, the automatic gain control algorithm based on the signal strength RSSI and the link quality Lqi comprehensive feedback can obtain more accurate control gain, the power consumption is saved, and meanwhile, the ideal link quality and more stable received signal quality are obtained
The cyclic code checker 54 is used to implement error detection and correction of the cyclic check code. The cyclic code checker 54 may adopt a conventional cyclic code checker using fixed generator polynomial coefficients, but the cyclic code checker can only support one cyclic check code, and has poor flexibility and universality. Fig. 7 shows a preferred implementation of the cyclic code checker 54, from which it can be seen that the generator polynomial coefficients of the cyclic code checker 54 can be configured by the processor 1 via a bus according to the needs of the user. When the cyclic check is performed on the data in the output data packet, 8-bit input data as high 8 bits and 8-bit 0 as low 8 bits are input into a buffer (equivalent to 8-step increase of the input information code), then the data enter a shift register sequence, and are subjected to bitwise XOR (equivalent to division by generated polynomial complementation) with a generated polynomial coefficient, the obtained remainder is a supervision code element, the supervision code element is added with the input information code increased by 8 steps for output, a system code coded by the cyclic code is obtained, the input data is subjected to cyclic calculation, and finally the check code of the whole data packet is obtained. When the data in the received data packet is circularly checked, repeating the calculation process to obtain the calculated check code of the received data packet, comparing the calculated check code with the last byte check codes received, and checking whether the data packet has errors. The polynomial coefficients generated by the cyclic code checker 54 can be configured through a bus, so that the requirements of checking various cyclic codes can be met, the checks of various cyclic check codes such as CRC-16, CRC-CCITT, CRC-12 and the like can be met, and the communication standard applicable to the digital baseband is wider and has stronger flexibility.
In another preferred embodiment, as shown in fig. 8, the digital baseband module 5 of the chip further includes a carrier leakage suppression unit 55 connected to the radio frequency module 6, and the unit is used for automatically monitoring carrier leakage power, compensating and suppressing carrier leakage at the transmitting end. The carrier leakage is generally caused by the fact that devices or processes are not ideal, a local oscillator high-frequency signal leaks through an antenna and is mixed with a useful signal to cause the carrier leakage, the carrier leakage does not belong to the useful signal, interference is caused after the carrier leakage leaks to a transmitter port, the demodulation effect of a receiving end is affected, and the bit error rate and the packet loss rate are improved. When the digital baseband module 5 has the unit 55 for suppressing carrier leakage, the wireless rf module 6 further includes a rf switch 63, and the wireless rf module 6 has two working modes, i.e. a normal working mode and a configuration mode for suppressing carrier leakage, and the switching between the two working modes is realized by the rf switch 63.
Fig. 9 shows a block diagram of the carrier leakage suppression unit 55, which simultaneously opens the data channels of the receiving unit 62 and the transmitting unit 61 through the rf switch 63 when the wireless rf module 6 operates in the carrier leakage suppression configuration mode. Since carrier leakage can be equivalent to that there is a direct current component in the IQ path of the transmitting end, and a corresponding direct current component is generated after down-conversion in the receiving end, which interferes with baseband demodulation, therefore, the carrier leakage suppression unit 55 performs AD sampling 551, low-pass filtering 552 and sliding window integration 553 on the baseband signal demodulated by radio frequency to obtain the direct current strength of the transmitting signal received and monitored, and the direct current compensation algorithm unit 554 is connected to the processor bus, and configures its initial control signal value by a software program, so that it has flexible controllability. The AD sampling unit 551 can be implemented by an independent IP unit or a general AD chip, for example, an independent IP unit; the low-pass filtering unit 552 and the sliding window integrating unit 553 may be implemented using a general digital lattice filter and a circular accumulator; the dc compensation algorithm unit 554 may be implemented by using a ROM, and maps 8-bit data of the IQ transmit signal dc intensity obtained after sampling, filtering and integrating into a compensation value of a register for suppressing carrier leakage of the control radio frequency, and feeds back the compensation value to the radio frequency transmit module to perform IQ path dc compensation, thereby achieving the purpose of adaptively suppressing carrier leakage, reducing the requirement on the performance of the radio frequency module, improving the yield of radio frequency chips, and reducing the node cost.
It can be seen from the description of the above embodiments that the digital baseband system of the present invention employs an automatic gain control mechanism based on an adaptive threshold comprehensively fed back by RSSI and LQI in gain control, so as to achieve the purposes of reducing node error rate and saving power consumption on the premise of ensuring a certain communication quality, thereby adapting to a complex and variable application environment.
The digital baseband system of the invention adopts a mode of a Schmitt trigger of a self-adaptive threshold to judge the signal phase in the in-place synchronization, thereby achieving the purpose of avoiding the increase of the demodulation error rate caused by the frequent jump of the input phase and reducing the error rate of the node.
The matched filter in the digital baseband system adopts a design method of multiplexing the adder and the multiplier of the filter, thereby achieving the purposes of reducing the hardware resource expenditure and reducing the cost while ensuring the performance of the linear filter.
The digital baseband system is compatible with the IEEE802.15.4 communication standard and is provided with the cyclic code checker capable of generating polynomial coefficients through software configuration, so that the chip where the digital baseband system is located has universality compatible with other sensor network node chips in communication and has high flexibility.
The digital baseband of the wireless sensor network node is provided with the self-adaptive control module for inhibiting the carrier leakage, and the register for inhibiting the carrier leakage of the radio frequency chip can be configured according to the self-adaptive algorithm, so that the direct current compensation of IQ path signals is realized, the aim of inhibiting the carrier leakage in a self-adaptive manner is fulfilled, the requirement on the performance of the radio frequency module is lowered, the yield of the radio frequency chip is improved, and the node cost is lowered.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. A digital baseband system for a wireless sensor network node chip is characterized by comprising a baseband modulation unit (51), a baseband demodulation unit (52), an automatic gain control unit (53) and a cyclic code checker (54); wherein,
the cyclic code checker (54) transmits the checked data to be transmitted to the baseband modulation unit (51), the baseband modulation unit (51) completes modulation processing including direct sequence spread spectrum, delay, digital signal shaping modulation and analog-to-digital conversion, and then the processed data is transmitted;
the baseband demodulation unit (52) performs demodulation processing including analog-to-digital conversion, despreading, optimal coherent demodulation and bit synchronous sampling judgment on the received data, and then transmits the processed data to the cyclic code checker (54) for data check;
the automatic gain control unit (53) adjusts the gain decision threshold according to the signal strength RSSI and the link quality LQI in the data receiving process, thereby realizing the control of the transmitting gain and the receiving gain.
2. The digital baseband system for a wireless sensor network node chip according to claim 1, further comprising a carrier leakage suppression unit (55) for automatically monitoring carrier leakage power, compensating and suppressing carrier leakage at a transmitting end; the unit is connected to an external transmitter.
3. The digital baseband system for the wireless sensor network node chip according to claim 1 or 2, wherein the baseband modulation unit (51) comprises a direct sequence spread spectrum module (511), a delay module (512), an O-QPSK digital modulation module (513), and a first digital-to-analog conversion module (514), a second digital-to-analog conversion module (515); wherein,
the direct sequence spread spectrum module (511) carries out spread spectrum coding on data to be sent according to a direct sequence spread spectrum coding table, and converts the data after the spread spectrum coding into I, Q two paths of serial data; the delay module (512) delays Q path data; the I, Q two paths of serial data are both shaped and modulated in the O-QPSK digital modulation module (513), and then are respectively analog-to-digital converted in the first digital-to-analog conversion module (514) and the second digital-to-analog conversion module (515).
4. The digital baseband system for the node chip of the wireless sensor network according to claim 3, wherein said O-QPSK digital modulation module (513) is implemented by using two ROM memories respectively storing sine and cosine waveform code tables.
5. The digital baseband system for the wireless sensor network node chip according to claim 1 or 2, wherein the baseband demodulation unit (52) comprises a first analog-to-digital conversion module (521), a second analog-to-digital conversion module (522), a first matched filter module (523), a second matched filter module (524), a third matched filter module (525), a fourth matched filter module (526), a first bit synchronization module (527), a second bit synchronization module (528), and a spread spectrum demodulation module (529); wherein,
the first analog-to-digital conversion module (521) and the second analog-to-digital conversion module (522) respectively convert the I-path signal and the Q-path signal of the received analog waveform signal into waveform level digital signals; the first matched filter module (523), the second matched filter module (524), the third matched filter module (525) and the fourth matched filter module (526) respectively carry out filtering operation on signals, eliminate intersymbol interference of received signals and carry out optimal coherent demodulation on the signals; the filtered signals are integrated and compared to obtain output signals at the decision moment, then sampling decision is carried out by extracting sampling decision pulses through the first bit synchronization module (527) and the second bit synchronization module (528), and a demodulation result is output to the spread spectrum demodulation module (529); the spread spectrum demodulation module (529) decodes the received chip code which is subjected to spread spectrum modulation into a data code stream, and obtains a link quality LQI value at the same time; the strength RSSI of the signal after the aforementioned filtering and the link quality LQI value are transmitted to the automatic gain control module (53).
6. The digital baseband system for the wireless sensor network node chip according to claim 5, wherein the first matched filter module (523), the second matched filter module (524), the third matched filter module (525), and the fourth matched filter module (526) are implemented by circuit multiplexing, and are driven by a high frequency clock, the computation amount completed in one clock cycle is divided into a plurality of clock cycles, and a large number of parallel combinational logic circuits are divided into a small number of sequential logic circuits.
7. The digital baseband system for the wireless sensor network node chip according to claim 5, wherein the first bit synchronization module (527) and the second bit synchronization module (528) adopt a Schmitt trigger with an adaptive threshold to perform signal phase decision; wherein,
when the phase decision outputs 1, the output of the next time is 0 only when the output signal of the matched filter is greater than the threshold, otherwise, 1 is output; when the phase decision outputs 0, the output of the next time is 1 only when the output signal of the matched filter is smaller than the threshold, otherwise, 0 is output.
8. The digital baseband system of claim 7, wherein the threshold value of said adaptive threshold Schmitt trigger is adaptively adjusted according to the RSSI, and the decision coefficient is dynamically configured according to the channel environment.
9. The digital baseband system for the wireless sensor network node chip according to claim 1 or 2, wherein the gain decision threshold of the automatic gain control unit (53) is (k-1)/k of the maximum value of LQI and RSSI, where k represents a decision coefficient;
the automatic gain control unit (53) has four states in implementing gain control: an initial state, a locked state, an increased gain state, and a decreased gain state; in any state, when LQI is smaller than (k-1)/k of the maximum value and RSSI is smaller than (k-1)/k of the maximum value, entering a gain increasing state from the current state; in any state, when LQI is less than (k-1)/k of the maximum value and RSSI is greater than (k-1)/k of the maximum value, entering a gain reduction state from the current state; in any state, entering a locked state when LQI is greater than (k-1)/k of its maximum value; when the values of LQI and RSSI are both larger than the respective historical values, the LQI and RSSI are out of the locking state, the corresponding values are stored in a maximum value register, then the LQI and RSSI enter the initial state, and gain adjustment is carried out again until the LQI and RSSI are in the locking state.
10. The digital baseband system for a wireless sensor network node chip according to claim 9, wherein the threshold initial value, the gain initial value and the decision coefficient k of the automatic gain control unit (53) are all set by a user.
11. The digital baseband system for a wireless sensor network node chip according to claim 1 or 2, characterized in that the generator polynomial coefficients of the cyclic code checker (54) are configured according to user needs.
12. The digital baseband system for the wireless sensor network node chip of claim 2, wherein the carrier leakage suppression module (55) comprises an AD sampling unit (551), a low pass filtering unit (552), a sliding window integrating unit (553), and a dc compensation algorithm unit (554); the baseband signal is subjected to AD sampling by the AD sampling unit (551), low-pass filtering by the low-pass filtering unit (552) and integration by the sliding window integrating unit (553) in sequence to obtain the direct current intensity of the transmitting signal, and a compensation value for inhibiting carrier leakage is generated by the direct current compensation algorithm unit (554) according to the direct current intensity of the transmitting signal.
13. A chip for a wireless sensor network node, characterized in that it comprises a digital baseband system according to one of claims 1 to 11.
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