CN102045133A - Chip for wireless sensor network node and on-chip digital baseband system - Google Patents

Abstract

The invention provides a digital baseband system for wireless sensor network node chips, including a baseband modulation unit, a baseband demodulation unit, an automatic gain control unit, and a cyclic code checker; The data to be sent is transmitted to the baseband modulation unit, and the baseband modulation unit completes the modulation processing including direct sequence spread spectrum, delay, digital signal shaping modulation, analog-to-digital conversion, and then sends the processed data; the baseband demodulation unit The received data is subjected to demodulation processing including analog-to-digital conversion, despreading, optimal coherent demodulation, and bit synchronization sampling judgment, and then the processed data is transmitted to the cyclic code checker for data verification The automatic gain control unit adjusts the gain judgment threshold according to the signal strength RSSI and the link quality LQI in the process of data transmission or reception, so as to realize the control of the transmission gain and the reception gain.

Description

Chip and on-chip digital baseband system for wireless sensor network nodes

technical field

The invention relates to the field of wireless transmission, in particular to a chip used for wireless sensor network nodes and a digital baseband system on the chip.

Background technique

Wireless sensor network (Wireless Sensor Network, WSN) is a self-organizing network application system composed of a large number of autonomous nodes densely deployed in the monitoring area. It has broad application prospects and can be widely used in military, environmental monitoring, medical health, traffic management, and commercial applications. Although wireless sensor network nodes have various applications, these applications have some common requirements for wireless sensor network nodes. The most challenging requirement is how to make wireless sensor network nodes have stronger computing power and a better application environment. wide, lower power consumption, smaller size, lower cost, and better communication quality.

Most of the current wireless sensor network nodes are realized by common embedded platforms. Since the devices of such sensor network nodes are not specially designed for wireless sensor networks, indicators such as processing power, power consumption and volume are often difficult to meet the requirements of practical applications. With the development of FPGA/ASIC technology and the emergence of system on chip (System on chip) technology, the method of system on chip is used to realize the wireless sensor network node platform on FPGA, and it will be converted to ASIC mass production when there are large-scale applications. The design method will become a key technical means to solve the problems of node processing capacity, power consumption and volume.

Signal acquisition, signal processing and networking communication are the three major functions of wireless sensor network nodes. According to the above functions, a wireless sensor network node is usually composed of four parts: sensing module, processing module, wireless communication module, and energy module. The wireless communication module accounts for most of the power consumption of the entire wireless sensor network node. The digital baseband plays a role in the wireless communication module to control the gain of radio frequency transmission and reception, channel codec, control of radio frequency carrier leakage suppression, digital signal shaping modulation, optimal coherent demodulation, bit synchronization and sampling judgment, etc., all of which affect wireless The power consumption, performance, hardware cost and bit error rate of sensor network nodes. Therefore, designing a digital baseband system with low power consumption, high performance, and low bit error rate is important for reducing the power consumption and hardware cost of wireless sensor network nodes and improving node communication. The quality and enhancement of nodes play an important role in the adaptability of the environment.

In order to meet the design goals of low power consumption and low cost of wireless sensor network nodes, the ZigBee alliance has launched the ZigBee protocol for WSN, making this protocol an emerging communication standard for wireless sensor networks. The physical layer (PHY) and media access layer (MAC) of the protocol are formulated by the IEEE802.15.4 working group. The IEEE802.15.4 standard formulated by the working group defines two frequency bands, 900MHz and 2.4GHz, in 2.405GHz-2.480 A total of 16 channels are defined in the GHz range, the channel spacing is 5MHz, the modulation method is O-QPSK, and the data transmission rate is 250Kb/s, using direct sequence spread spectrum (DSSS) based on pseudo-random noise (PN) codes technology with a spreading gain of 8. The application of the above-mentioned communication protocol is beneficial to the mutual communication between the wireless sensor network nodes generated by different manufacturers, it is beneficial to reduce the power consumption and cost of the wireless sensor network nodes, and it is beneficial to the promotion and application of the wireless sensor network.

However, in the prior art, most wireless sensors implemented by SoC design methods adopt their own communication standards, and few digital baseband systems in sensors are designed according to the IEEE802.15.4 standard. For example, WiseNet, a wireless sensor network node developed by CMES in Switzerland, adopts system-on-chip technology and is specially designed for wireless sensor networks, but the digital baseband in this node adopts 2FSK modulation with a maximum data rate of 100kb/s, which does not comply with IEEE802 The standard of .15.4 makes the chip not compatible with other sensor network node chips that comply with the IEEE802.15.4 standard.

There are also digital baseband systems that comply with the IEEE802.15.4 standard in the prior art, such as the digital baseband systems in Chipcon's CC2431 and CC2510 and JENNIC's JN5121 series chips, but the chips containing these digital baseband systems still have certain limitations ,include:

1. The digital baseband system of these chips can do automatic gain control, and the gain range can be configured through software, but the decision threshold involved in the automatic gain control process adopts a fixed threshold value, which does not have the feature of adaptive adjustment. Moreover, the signal strength RSSI is generally used as the feedback value for control, and the signal is amplified to saturation, and the receiving link quality LQI is rarely considered comprehensively. The narrowband interference in the channel will increase the RSSI, but will reduce the link quality LQI, so it is inaccurate to use a single RSSI as feedback to adjust the acceptance gain. Considering the fact that wireless sensor network nodes have a wide range of application environments, in the actual application process, they will face problems such as complex and changeable channel conditions, uncertain transmission power, and real-time changes in communication distances, which will affect the node packet loss rate and energy consumption. The existing digital baseband system adopts a fixed threshold decision method, which will lead to a decrease in the environmental adaptability of the node.

2. The digital baseband system of these chips does not use the adaptive threshold Schmitt trigger method for signal phase judgment, but uses the traditional zero-crossing trigger method for signal phase judgment, so it cannot be avoided due to frequent jumps in the input phase. The change causes the demodulation error rate to increase.

3. The digital baseband system of these chips uses a fixed generator polynomial instead of software configurable when doing cyclic code verification, resulting in poor flexibility and versatility of the baseband.

4. The digital baseband system of these chips does not have the function of suppressing carrier leakage, so the quality requirements of radio frequency chips are very high, which increases the node cost.

Contents of the invention

An object of the present invention is to provide a digital baseband system capable of adaptively adjusting the decision threshold of automatic gain control.

Another object of the present invention is to overcome the defect that the demodulation bit error rate increases due to frequent input phase jumps during signal phase judgment, thereby providing a digital baseband system capable of reducing the demodulation bit error rate.

Another object of the present invention is to provide a digital baseband system including a user-configurable cyclic code checker, which enhances the flexibility and versatility of the digital baseband.

Another object of the present invention is to provide a digital baseband system including automatic suppression of radio frequency carrier leakage, which reduces the quality requirements for radio frequency chips and reduces node costs.

In order to achieve the above object, the present invention provides a digital baseband system for a wireless sensor network node chip, including a baseband modulation unit, a baseband demodulation unit, an automatic gain control unit, and a cyclic code checker; wherein,

The cyclic code checker transmits the verified data to be sent to the baseband modulation unit, and the baseband modulation unit completes the process including direct sequence spread spectrum, delay, digital signal shaping modulation, and analog-to-digital conversion. Internal modulation processing, and then send the processed data out;

The baseband demodulation unit performs demodulation processing on the received data including analog-to-digital conversion, despreading, optimal coherent demodulation, and bit synchronization sampling judgment, and then transmits the processed data to the Cyclic code checker for data check;

The automatic gain control unit adjusts the gain judgment threshold according to the signal strength RSSI and the link quality LQI in the data receiving process, and cooperates with the working mode of software and hardware, so as to realize the control of the transmission gain and the reception gain.

The above technical solution also includes a suppressing carrier leakage unit for automatically monitoring the carrier leakage power, compensating and suppressing the carrier leakage of the transmitting end; the unit is connected with the external transmitting end.

In the above technical solution, the baseband modulation unit includes a direct sequence spread spectrum module, a delay module, an O-QPSK digital modulation module, a first digital-to-analog conversion module, and a second digital-to-analog conversion module; wherein,

Described direct sequence spread spectrum module carries out spread spectrum coding to the data to be sent according to direct sequence spread spectrum coding table, and the data after spread spectrum coding is converted into I, Q two-way serial data; Described delay module delay Q road data; described I, Q two road serial data all do shape modulation in described O-QPSK digital modulation module, then respectively in described first digital-to-analog conversion module and the second digital-to-analog conversion module Do analog-to-digital conversion.

In the above technical solution, the O-QPSK digital modulation module is realized by using two ROM memories respectively storing waveform code tables of sine and cosine.

In the above technical solution, the baseband demodulation unit includes a first analog-to-digital conversion module, a second analog-to-digital conversion module, a first matched filter module, a second matched filter module, a third matched filter module, a fourth A matched filter module, a first bit synchronization module, a second bit synchronization module and a spread spectrum demodulation module; wherein,

The first analog-to-digital conversion module and the second analog-to-digital conversion module respectively convert the I-channel signal and the Q-channel signal of the received analog waveform signal into a waveform-level digital signal; the first matched filter module, The second matched filter module, the third matched filter module, and the fourth matched filter module respectively perform filtering operations on the signal, eliminate the intersymbol interference of the received signal and perform optimal coherent demodulation on it; the filtered signal is integrated , obtain the output signal of the judgment moment after comparison, then extract the sampling judgment pulse by the first bit synchronization module and the second synchronization module to carry out sampling judgment, and output the demodulation result to the spread spectrum demodulation module; The demodulation module decodes the received chip code through spread spectrum modulation into a data code stream, and obtains the link quality LQI value at the same time; the strength RSSI and the link quality LQI value of the signal after the aforementioned filtering are transmitted to the automatic gain control module.

In the above technical solution, the first matched filter module, the second matched filter module, the third matched filter module, and the fourth matched filter module are implemented by circuit multiplexing, driven by a high-frequency clock, and a clock The amount of calculation completed in a cycle is divided into several clock cycles, and a large number of parallel combinational logic circuits are divided into a small number of sequential logic circuits.

In the above technical solution, the first bit synchronization module and the second bit synchronization module use a Schmitt trigger with an adaptive threshold to determine the signal phase; wherein,

When this phase judgment outputs 1, only when the output signal of the matched filter is greater than the threshold, the next output is 0, otherwise it outputs 1; when this phase judgment outputs 0, only when the matched filter When the output signal of the device is less than the threshold, the next output will be 1, otherwise it will output 0.

In the above technical solution, the threshold value in the Schmitt trigger of the adaptive threshold is adaptively adjusted according to the signal strength RSSI, and at the same time, the user dynamically configures the decision coefficient according to the channel environment.

In the above technical scheme, the gain decision threshold of the automatic gain control unit is (k-1)/k of the maximum value of LQI and RSSI, wherein k represents the decision coefficient;

The automatic gain control unit has four states in the process of realizing gain control: initial state, locked state, increased gain state, and reduced gain state; wherein, in any state, when the LQI is less than (k-1 of its maximum value )/k and RSSI is less than (k-1)/k of its maximum value, enter the state of increasing gain from the current state; in any state, when LQI is less than (k-1)/k of its maximum value and RSSI is greater than its maximum (k-1)/k of the value, enter the state of reducing the gain from the current state; in any state, enter the locked state when the LQI is greater than (k-1)/k of its maximum value; when the values of LQI and RSSI are greater than Their respective historical record values will jump out of the locked state, store the corresponding value in the maximum value register, and then enter the initial state, and re-adjust the gain until the locked state.

In the above technical solution, the initial value of the threshold, the initial value of the gain and the decision coefficient k of the automatic gain control unit are all set by the user.

In the above technical solution, the generator polynomial coefficients of the cyclic code checker are configured according to user requirements.

In the above technical solution, the described carrier leakage suppression module includes an AD sampling unit, a low-pass filter unit, a sliding window integration unit, and a DC compensation algorithm unit; After low-pass filtering and integration by the sliding window integration unit, the DC intensity of the transmitted signal is obtained, and the DC compensation algorithm unit generates a compensation value for suppressing carrier leakage according to the DC intensity of the transmitted signal.

The invention also provides a chip for wireless sensor network nodes, including the digital baseband system.

The advantages of the present invention are:

1. The digital baseband system of the present invention adopts the automatic gain control mechanism based on the self-adaptive threshold of the comprehensive feedback of signal strength RSSI and link quality LQI in the gain control, so as to reduce the bit error rate of nodes and save The purpose of power consumption, so as to adapt to the complex and changeable application environment.

2. The digital baseband system of the present invention can support the IEEE802.15.4 communication protocol standard, so that the chip using the digital baseband system is compatible with other electronic devices supporting the IEEE802.15.4 communication protocol standard.

Description of drawings

Fig. 1 is a schematic structural diagram of an embodiment of a sensor network node chip comprising a digital baseband system;

FIG. 2 is a schematic structural diagram of a baseband modulation unit in a digital baseband system;

Fig. 3 is a schematic structural diagram of a baseband demodulation unit and an automatic gain control unit in a digital baseband system;

Fig. 4 is a schematic structural diagram of a matched filter in a digital baseband system;

Fig. 5 is the schematic diagram that the bit synchronization module in the digital baseband system realizes the phase decision;

6 is a state transition diagram of an automatic gain control unit in a digital baseband system;

Fig. 7 is a structural diagram of a cyclic code checker in a digital baseband system;

FIG. 8 is a schematic structural diagram of another embodiment of a sensor network node chip including a digital baseband system;

FIG. 9 is a structural diagram of a carrier leakage suppression module.

Detailed ways

The present invention will be described below in conjunction with the accompanying drawings and specific embodiments.

FIG. 1 shows an embodiment of a chip used in a wireless sensor network node according to the present invention. The structure of the chip will be described below in conjunction with FIG. 1 . It can be seen from the figure that the chip of the present invention includes a processor 1 , a program memory 2 , a data memory 3 , a MAC protocol module 4 , a digital baseband module 5 , a radio frequency module 6 and other modules 7 . Wherein, the processor 1 is connected to the data memory 3, the MAC protocol module 4, the digital baseband module 5, the radio frequency module 6 and other modules 7 through a bus, and the processor 1 is connected to the program memory 2 through a program reading line; The MAC protocol module 4 is connected to the digital baseband module 5 through a bidirectional data line, and a data transceiving path is also established between the digital baseband module 5 and the radio frequency module 6 through the data line. The specific function and implementation of each component in the chip will be described below.

Processor 1 is a logic device that completes corresponding operations according to the program code in program memory 2. Existing IP modules or open source codes can be selected for implementation, such as Oregano Systems’ MC8051 processor source code, ARM series processor modules, etc. Under the control of the program code, processor 1 will perform various operations on other components in the chip, including initialization settings and control. In the following description of other components, when it comes to processor 1, the processor 1 in detail.

The program memory 2 is used to store programs to be run by the processor 1 . The program memory 2 can generally be realized by using mature process design methods such as FLASH or EEPROM.

The data memory 3 is used to store the data to be used by the processor 1, and generally can be realized by a mature technology such as DRAM or SRAM.

The MAC protocol module 4 sets the operating frequency, dormancy mode, collision avoidance mechanism, transmission power and channel selection of the wireless radio frequency module 6 under the control of the processor 1, and configures its transmission and channel selection by the processor 1. The object of receiving data and the distribution of work sleep time, complete the analysis of data packets, the judgment of channel occupancy and the random backoff of conflicts, etc. The realization of the MAC protocol module 4 can adopt any IP module conforming to the IEEE802.15.4 communication standard or other MAC protocols in the prior art.

The wireless radio frequency module 6 is used for analog partial modulation transmission of wireless transmission data and analog partial demodulation reception of wireless reception data. This module includes a transmitting unit 61 and a receiving unit 62 . The existing IP module conforming to the IEEE802.15.4 communication standard can be selected for implementation.

Other modules 7 are used to realize multiple functions including power supply control, sensor control, input and output, and this module can also be realized by existing technologies.

The digital baseband module 5 has many functions such as control of radio frequency transceiver gain, direct sequence spread spectrum, digital signal shaping modulation, digital-to-analog/analog-to-digital conversion, despreading, bit synchronous sampling judgment, and cyclic code check. According to the above-mentioned functions of the digital baseband module 5, this module can be further divided, and a kind of realization mode of the digital baseband module 5 has been provided in Fig. A control unit 53 and a cyclic code checker 54 . Wherein, after receiving data from the MAC protocol module 4, the cyclic code checker 54 connected with the MAC protocol module 4 through the data line sends the verified data to the baseband modulation unit 51, and the baseband modulation unit 51 sends the modulated data into the wireless radio frequency module 6, and transmitted through the wireless radio frequency module 6. After the radio frequency module 6 receives the data, it will send the received data to the baseband demodulation unit 52 for data demodulation, and the demodulated data will be sent to the cyclic code checker 54 for data verification. The data is sent to the MAC protocol module 4, and in the process of data demodulation, automatic gain adjustment is also realized through the automatic gain control unit 53. The digital baseband module 5 of the present invention meets the IEEE802.15.4 standard when implemented, and the specific structure and working principle of each unit involved in the module will be described in the following description.

Figure 2 shows a schematic structural diagram of the baseband modulation unit 51. According to the relevant regulations of the IEEE802.15.4 standard, the baseband modulation unit 51 should complete the functions including direct sequence spread spectrum, delay, digital signal shaping modulation, and analog-to-digital conversion. Various operations. According to the functions described above, the unit includes a direct sequence spread spectrum module 511 , a delay module 512 , an O-QPSK digital modulation module 513 and a digital-to-analog conversion (DAC) module 514 , 515 .

The direct-sequence spread spectrum module 511 realizes the code table conversion of the transmitted data, specifically, it is a spread-spectrum code that performs one-to-one mapping of 4-bit binary data according to the direct-sequence spread spectrum code table provided by the IEEE802.15.4 communication standard, The resulting codes are pseudorandom noise codes and are mutually orthogonal. Direct sequence spread spectrum module 511 can adopt a ROM to realize, after receiving the serial data from MAC protocol module 4, do serial-to-parallel conversion to this serial data, then from the direct sequence spread spectrum coding table that ROM saves Read the corresponding code pattern in the middle, after 8 times the spread spectrum gain, the data stream is converted into a binary chip code sequence, and finally converted into I and Q two-way serial data with a FIFO.

The delay module 512 delays the Q-channel signal by T/2 (T represents the symbol period) compared with the I-channel signal, and the delayed Q-channel serial data is transmitted to the O-QPSK modulation module 513, while the I-channel signal does not pass through the delay module 512 is directly transmitted to the O-QPSK modulation module 513.

The O-QPSK digital modulation module 513 is used for shaping and modulating the digital signal. The O-QPSK digital modulation module 513 can use a shaping filter to realize the shaping modulation of the digital signal, but in this embodiment, as a preferred implementation, the O-QPSK digital modulation module 513 can use two The ROM memory of the cosine waveform code table directly outputs the filtered level from the waveform code table according to the modulation pattern when performing shaping modulation. Compared with the aforementioned implementation using a shaping filter, this implementation can omit the shaping filter, minimize unnecessary energy consumption and hardware overhead, and meet the requirements of low-cost and low-power consumption of sensor network nodes.

The DAC modules 514 and 515 respectively perform analog-to-digital conversion on the I-channel signal and the Q-channel signal, and convert the modulated waveform-level digital signal into an analog waveform signal. The DA module can be implemented by using an independent IP unit or a general DA chip. As a preferred implementation manner, in this embodiment, the DA module uses an independent IP unit.

FIG. 3 shows a schematic structural diagram of the baseband demodulation unit 52 and the automatic gain control unit 53 . The baseband demodulation unit 52 should complete multiple operations including analog-to-digital conversion, despreading, optimal coherent demodulation, and bit synchronous sampling judgment. According to the above-mentioned functions, the baseband demodulation unit 52 includes an analog-to-digital conversion (ADC) module 521, 522, matched filter modules 523, 524, 525, 526, bit synchronization modules 527, 528, spread spectrum demodulation module 529.

The ADC modules 521 and 522 respectively convert the I-channel signal and the Q-channel signal of the analog waveform signal demodulated from the radio frequency module 6 into waveform-level digital signals. Similar to the DA module mentioned above, the AD module can also be realized by using an independent IP unit or a common AD chip. As a preferred implementation, in this embodiment, an independent IP unit is used.

The matched filters 523, 524, 525, and 526 perform filtering operations on the signals respectively, eliminate the intersymbol interference of the received signals and perform optimal coherent demodulation on them. The filtered result is passed through the integrator and comparator to obtain the output signal s_diff=y1-y0 at the decision time, and then the sampling decision pulse is extracted through the bit synchronization modules 527 and 528 for sampling and judgment, and the demodulation result is output to the spread spectrum demodulation module 529. In this process, the strength of the signal after passing through the aforementioned matched filter is also obtained, and the strength is represented by RSSI=y1+y0, and this strength value will be output to the automatic gain control module 53 as feedback to realize gain control. When calculating the signal strength, it is beneficial to shield the background noise by doing matched filtering first, so as to obtain a more accurate received signal strength.

It can be seen from the above description that the function of the matched filter is to realize the filtering operation on the signal, so the correlation filters in the prior art can be used in the present invention theoretically. However, considering that the wireless sensor network nodes require low cost and low power consumption, Figure 4 shows a preferred implementation of the matched filter in hardware. It can be seen from the figure that in this implementation, according to the idea of circuit multiplexing, by using high-frequency clock drive, the calculation amount completed in one clock cycle is divided into several clock cycles to complete, and a large number of parallel combinational logic circuits It is divided into a small number of sequential logic circuits, and these sequential logic circuits are multiplexed for several cycles to achieve the same calculation function, so as to reduce the number of hardware implementation units, such as reducing multipliers and adders, while ensuring the performance of linear filters. The purpose of reducing hardware resource overhead. For example, in an example, assume that there is an AD sampling rate of 24MHz, and the chip rate is 2MHz, so 12 multiplication and addition operations must be completed in each sampling period, and 12 adders and multipliers are required for parallel calculations. However, through the multiplex design, a clock that is 6 times the sampling frequency is used to drive the matched filter module. One sampling cycle calculates 6 clock cycles, and only two adders and multipliers are used in each cycle, using the least number of multipliers and adders. The filter is implemented, which saves 5/6 hardware resources compared with the traditional parallel filter, realizes the purpose of reducing hardware cost, and meets the requirement of low cost of sensor network nodes.

The bit synchronization module is used to adjust the phase of the local synchronous sampling pulse at the receiving end to make it consistent with the phase of the received demodulated signal, so that the demodulated signal can be accurately sampled. In the prior art, the bit synchronization module adopts a method of directly performing zero-crossing detection on the output of the matched filter to determine the phase of the output demodulated signal when realizing the phase judgment of the received demodulated signal. Since it is required to completely know the signal shape (including frequency, phase, amplitude, arrival time, etc.) Any problem such as inaccurate timing will lead to the inability to meet the "best reception" condition of the matched filter, so that the output of the matched filter will trigger multiple zero-crossing triggers at the zero-crossing point, causing the bit synchronization input to be in the 0, 1 state Frequent jumps between them will affect the bit synchronization effect and cause an increase in the demodulation bit error rate.

In view of the above-mentioned shortcomings in the implementation of the bit synchronization module in the prior art, Fig. 5 shows a Schmitt trigger with an adaptive threshold to judge the signal phase, so as to avoid frequent jumps of the input phase. In this implementation, when this phase judgment outputs 1, the next output is 0 only when the filter output signal is greater than the threshold, otherwise it outputs 1. When this phase judgment outputs 0, only when the filter output signal is greater than the threshold When the output signal is less than the threshold, the next output will be 1, otherwise it will output 0. Since wireless sensor network nodes need to adapt to various complex communication environments, and often cannot meet the "best reception" condition in harsh communication environments, the output signal amplitude of the matched filter is smaller than normal, so the threshold value for phase judgment It should be adaptive and adjustable to avoid phase decision errors. Specifically, the above-mentioned signal strength value RSSI is used as a feedback value to adaptively adjust the decision threshold, and the decision coefficient k can be dynamically configured according to the channel environment to achieve higher controllability and flexibility. It can be seen from the figure that when the phase judgment outputs 1 this time, the next output is 0 only when the filter output signal s_diff is greater than k times of RSSI, otherwise the output is 1. When the phase judgment outputs 0 this time, Only when the filter output signal s_diff is less than -k times of RSSI, the next output is 1, otherwise the output is 0. The above-mentioned judgment method can make the judgment threshold change in real time according to the signal strength, guarantee the correct rate of the judgment result, prevent the bit error rate of the system from being significantly reduced due to the harsh environment, and meet the requirements of adapting to various communication environments. After obtaining the phase of the demodulated signal, the present invention adopts a digital phase-locking method for bit synchronization. It is not directly used for sampling judgment, but is compared with the output signal s_diff of the matched filter obtained from the comparator, and a controller adds or subtracts one or several pulses to the pulse sequence output by the signal clock to achieve the output sampling judgment The purpose of synchronizing the signal with the received signal. The bit synchronization pulse and the binary chip code sequence finally obtained by the bit synchronization module are input into the spread spectrum demodulation module 529 for correlation demodulation.

The spread spectrum demodulation module 529 is used for decoding the received spread spectrum modulated chip code into a data code stream. According to the IEEE 802.15.4 protocol, direct sequence spread spectrum is to map every 4 bits of data into a symbol to select 16 quasi-orthogonal pseudo-random sequences, and each pseudo-random sequence consists of 32-bit chip codes. Each 32-bit code is divided into two 16-bit subcodes, I and Q. Due to the orthogonality of the 16 pseudo-random sequences, the cross-correlation coefficient is very small and the auto-correlation coefficient is very large, so the spread spectrum demodulation module 529 first performs a correlation operation on the I road of the received signal and the I road of each symbol, According to the maximum likelihood criterion, the maximum value is taken out, and then the correlation operation is performed with the Q-channel signal, and the sign of the correlation result is judged to obtain the corresponding decoded 4-bit data. In the above decoding process, the correlation coefficient between the chip code of each received data and the original chip code is also counted at the same time. The higher the correlation coefficient, the better the link quality performance of the channel, and the average value of the correlation coefficient is mapped to is the link quality LQI value. The data code stream obtained after spread spectrum demodulation is sent to the cyclic code checker 54 , and the calculated LQI value is sent to the automatic gain control unit 53 .

The automatic gain control unit 53 includes transmit gain control and receive gain control. In the transmission gain control, the user adjusts the transmission gain through the software according to the link quality LQI, and the processor 1 pays the value to the configuration register, and the MAC protocol module 4 reads it at the time of sending preprocessing. This method of combining software and hardware The control gain not only reduces the complexity of the user's use to a certain extent, but also greatly increases the flexibility of the system to meet the needs of various communication environments and low power consumption. In receiving gain control, the gain decision threshold is adjusted based on the comprehensive feedback results of the signal strength RSSI of the received signal and the link quality LQI. The implementation process of this method will be described below with reference to FIG. 6 .

How to obtain the signal strength RSSI and the link quality LQI has been described in the previous description, and the description will not be repeated here. The (k-1)/k of the maximum value of LQI and RSSI are respectively used as the gain decision threshold, where k represents the decision coefficient, which can be set by the user. It can be seen from Figure 6 that there are four states in the gain control process: initial state, locked state, increased gain state, and reduced gain state. In any state, when LQI is less than (k-1)/k of its maximum value and RSSI is less than (k-1)/k of its maximum value, enter the state of increasing gain from the current state; in any state, when LQI is less than (k-1)/k of its maximum value and RSSI is greater than (k-1)/k of its maximum value, enter the state of reducing gain from the current state; in any state, when LQI is greater than (k-1) of its maximum value )/k to enter the locked state; when the values of LQI and RSSI are greater than their respective historical record values, it will jump out of the locked state, store the corresponding value into the maximum value register, and then enter the initial state, and re-adjust the gain. until locked. In addition, before the adaptive adjustment of the gain decision threshold, the initial value of the threshold and the initial value of the gain can be set by the user, so that the system can be applied to various communication environments according to requirements.

Compared with the existing automatic gain control method, in the method shown in Figure 6, the threshold of the automatic gain control is adaptive to the received signal strength RSSI and the link quality LQI after passing through the matched filter. , the transmission power and the communication distance change, the decision threshold for determining the optimal value of the gain will also change accordingly. When the channel environment is good, the transmission power is high, and the communication distance is short, the RSSI and LQI increase, the gain decreases, and the decision threshold increases, so that the signal will not be amplified to saturation and save a certain amount of receiving power consumption. When the channel environment is poor, the transmission power is small and the communication distance is long, the RSSI and LQI will decrease, the gain will increase, and the decision threshold will decrease, so as to obtain better received signal quality and reduce the packet loss rate of nodes. In addition, according to the actual measurement results, it can be known that in the area where the signal strength RSSI is within 10m, its fading trend with distance is roughly the same as that of the link quality LQI, but when the distance increases, the decay curve of RSSI is relatively flat, which is obviously higher than The attenuation curve of the LQI, and the fading curve of the LQI will increase the oscillation with the increase of the distance, and there will be a large irregular fading at the same time. This phenomenon shows that the impact of multipath interference, diffraction, and obstacles on signal quality is significantly higher than the impact on signal strength when the distance increases, and when the receiving gain is so large that the receiving signal is saturated, the RSSI may not be significantly affected. However, because the saturated signal will exceed the AD linear range, the demodulation bit rate will increase and the LQI will decrease. Therefore, it is inaccurate to use a single RSSI as feedback to adjust the receiving gain. On the other hand, since the LQI fluctuates greatly with the distance, using a single LQI as feedback to adjust the receiving gain will cause poor system stability. Therefore, an automatic gain control algorithm based on the comprehensive feedback of signal strength RSSI and link quality LQI is adopted. Can get more accurate control gain, while saving power consumption, get ideal link quality and more stable received signal

The cyclic code checker 54 is used to implement error detection and correction of the cyclic check code. The cyclic code checker 54 can adopt a traditional cyclic code checker using fixed generator polynomial coefficients, but this kind of cyclic code checker can only support one kind of cyclic check code, and its flexibility and versatility are not strong. FIG. 7 shows a preferred implementation of the cyclic code checker 54. It can be seen from the figure that the generator polynomial coefficients of the cyclic code checker 54 can be configured by the processor 1 according to user needs through the bus. When performing a cyclic check on the data in the output data packet, the 8-bit input data as the upper 8 bits and the 8-bit 0 as the lower 8 bits are input into the buffer in parallel (equivalent to raising the input information code by 8 steps), and then enter The shift register sequence is XORed bit by bit with the coefficient of the generator polynomial (equivalent to dividing by the generator polynomial to find the remainder), and the obtained remainder is the supervisory symbol, which is added to the input information code raised by 8th order Output, get the system code encoded by the cyclic code, calculate the input data cyclically, and finally get the check code of the entire data packet. When performing a cyclic check on the data in the received data packet, repeat the above calculation process to obtain the calculated check code of the received data packet, compare it with the last few byte check codes received, and check whether the data packet has any errors . Since the generator polynomial coefficients of the cyclic code checker 54 can be configured through the bus, it can meet the needs of various cyclic code checks, and can meet the calibration of various cyclic check codes such as CRC-16, CRC-CCITT, and CRC-12. experience, making the communication standards applicable to the digital baseband wider and more flexible.

The above is a description of an embodiment of the wireless sensor network node chip of the present invention. In another preferred embodiment, as shown in FIG. The carrier leakage unit 55 is used to automatically monitor the carrier leakage power, compensate and suppress the carrier leakage at the transmitting end. Carrier leakage is generally caused by the unsatisfactory device or process itself. The local oscillator high-frequency signal leaks through the antenna and mixes with the useful signal to cause carrier leakage. Carrier leakage is not a useful signal. When it leaks to the transmitter port, it will cause Interference affects the demodulation effect at the receiving end, resulting in an increase in the bit error rate and packet loss rate. When the digital baseband module 5 has a suppression carrier leakage unit 55, the wireless radio frequency module 6 also includes a radio frequency switch 63, and the wireless radio frequency module 6 has two kinds of operating modes, that is, a normal operating mode and a suppression carrier leakage preparation mode, two operating modes Switching among them is realized through the radio frequency switch 63 described above.

FIG. 9 shows a structural diagram of the carrier leakage suppression unit 55. When the radio frequency module 6 is working in the carrier leakage suppression configuration mode, the data channels of the receiving unit 62 and the transmitting unit 61 are simultaneously opened through the radio frequency switch 63. Since the carrier leakage can be equivalent to the presence of a DC component in the IQ path at the transmitting end, a corresponding DC component will be generated after down-conversion at the receiving end, which interferes with the baseband demodulation. Therefore, the carrier leakage suppression unit 55 performs AD sampling 551, low-pass filtering 552, sliding window integration 553 to obtain the DC strength of the transmitted signal received and monitored, the DC compensation algorithm unit 554 is connected to the processor bus, and its initial control signal value is configured through a software program to make it flexible and controllable sex. The AD sampling unit 551 can be realized by using an independent IP unit or a general-purpose AD chip, such as using an independent IP unit; the low-pass filter unit 552 and the sliding window integration unit 553 can use a general-purpose digital lattice filter and loop accumulation The DC compensation algorithm unit 554 can be realized by a ROM, and the 8-bit data of the DC intensity of the IQ channel transmission signal obtained after sampling, filtering and integrating is mapped to the compensation value of the suppressing carrier leakage register of the control radio frequency, and fed back to the radio frequency transmission module for further processing. The DC compensation of the IQ channel achieves the purpose of self-adaptive suppression of carrier leakage, reduces the performance requirements of the RF module, improves the yield of the RF chip, and reduces the node cost.

It can be seen from the description of the above embodiments that the digital baseband system of the present invention adopts an automatic gain control mechanism based on an adaptive threshold based on the comprehensive feedback of signal strength RSSI and link quality LQI in gain control, so as to achieve the premise of ensuring a certain communication quality The purpose of lowering the bit error rate of nodes and saving power consumption is to adapt to complex and changeable application environments.

The digital baseband system of the present invention uses an adaptive threshold Schmitt trigger to judge the signal phase in bit synchronization, so as to avoid the increase of the demodulation bit error rate caused by frequent input phase jumps, and reduce the Node error rate.

The matched filter in the digital baseband system of the present invention adopts the design method of multiplexing the adder and multiplier of the filter, and achieves the purpose of reducing hardware resource overhead and cost while ensuring the performance of the linear filter.

The digital baseband system of the present invention is compatible with the IEEE802.15.4 communication standard, and has a cyclic code checker that can be configured by software to generate polynomial coefficients, so that the chip where the digital baseband system is located has the versatility of being compatible with other sensor network node chips in communication, And has high flexibility.

The wireless sensor network node digital baseband of the present invention has a control module for adaptive carrier leakage suppression, and can configure the carrier leakage suppression register of the radio frequency chip according to an adaptive algorithm, thereby realizing DC compensation for IQ channel signals, and achieving adaptive suppression of carrier leakage The purpose is to reduce the performance requirements of radio frequency modules, improve the yield of radio frequency chips, and reduce node costs.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than limit them. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent replacements to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all of them should be included in the scope of the present invention. within the scope of the claims.

Claims (13)

1. A digital baseband system for a wireless sensor network node chip is characterized by comprising a baseband modulation unit (51), a baseband demodulation unit (52), an automatic gain control unit (53) and a cyclic code checker (54); wherein,

the cyclic code checker (54) transmits the checked data to be transmitted to the baseband modulation unit (51), the baseband modulation unit (51) completes modulation processing including direct sequence spread spectrum, delay, digital signal shaping modulation and analog-to-digital conversion, and then the processed data is transmitted;

the baseband demodulation unit (52) performs demodulation processing including analog-to-digital conversion, despreading, optimal coherent demodulation and bit synchronous sampling judgment on the received data, and then transmits the processed data to the cyclic code checker (54) for data check;

the automatic gain control unit (53) adjusts the gain decision threshold according to the signal strength RSSI and the link quality LQI in the data receiving process, thereby realizing the control of the transmitting gain and the receiving gain.

2. The digital baseband system for a wireless sensor network node chip according to claim 1, further comprising a carrier leakage suppression unit (55) for automatically monitoring carrier leakage power, compensating and suppressing carrier leakage at a transmitting end; the unit is connected to an external transmitter.

3. The digital baseband system for the wireless sensor network node chip according to claim 1 or 2, wherein the baseband modulation unit (51) comprises a direct sequence spread spectrum module (511), a delay module (512), an O-QPSK digital modulation module (513), and a first digital-to-analog conversion module (514), a second digital-to-analog conversion module (515); wherein,

the direct sequence spread spectrum module (511) carries out spread spectrum coding on data to be sent according to a direct sequence spread spectrum coding table, and converts the data after the spread spectrum coding into I, Q two paths of serial data; the delay module (512) delays Q path data; the I, Q two paths of serial data are both shaped and modulated in the O-QPSK digital modulation module (513), and then are respectively analog-to-digital converted in the first digital-to-analog conversion module (514) and the second digital-to-analog conversion module (515).

4. The digital baseband system for the node chip of the wireless sensor network according to claim 3, wherein said O-QPSK digital modulation module (513) is implemented by using two ROM memories respectively storing sine and cosine waveform code tables.

5. The digital baseband system for the wireless sensor network node chip according to claim 1 or 2, wherein the baseband demodulation unit (52) comprises a first analog-to-digital conversion module (521), a second analog-to-digital conversion module (522), a first matched filter module (523), a second matched filter module (524), a third matched filter module (525), a fourth matched filter module (526), a first bit synchronization module (527), a second bit synchronization module (528), and a spread spectrum demodulation module (529); wherein,

the first analog-to-digital conversion module (521) and the second analog-to-digital conversion module (522) respectively convert the I-path signal and the Q-path signal of the received analog waveform signal into waveform level digital signals; the first matched filter module (523), the second matched filter module (524), the third matched filter module (525) and the fourth matched filter module (526) respectively carry out filtering operation on signals, eliminate intersymbol interference of received signals and carry out optimal coherent demodulation on the signals; the filtered signals are integrated and compared to obtain output signals at the decision moment, then sampling decision is carried out by extracting sampling decision pulses through the first bit synchronization module (527) and the second bit synchronization module (528), and a demodulation result is output to the spread spectrum demodulation module (529); the spread spectrum demodulation module (529) decodes the received chip code which is subjected to spread spectrum modulation into a data code stream, and obtains a link quality LQI value at the same time; the strength RSSI of the signal after the aforementioned filtering and the link quality LQI value are transmitted to the automatic gain control module (53).

6. The digital baseband system for the wireless sensor network node chip according to claim 5, wherein the first matched filter module (523), the second matched filter module (524), the third matched filter module (525), and the fourth matched filter module (526) are implemented by circuit multiplexing, and are driven by a high frequency clock, the computation amount completed in one clock cycle is divided into a plurality of clock cycles, and a large number of parallel combinational logic circuits are divided into a small number of sequential logic circuits.

7. The digital baseband system for the wireless sensor network node chip according to claim 5, wherein the first bit synchronization module (527) and the second bit synchronization module (528) adopt a Schmitt trigger with an adaptive threshold to perform signal phase decision; wherein,

when the phase decision outputs 1, the output of the next time is 0 only when the output signal of the matched filter is greater than the threshold, otherwise, 1 is output; when the phase decision outputs 0, the output of the next time is 1 only when the output signal of the matched filter is smaller than the threshold, otherwise, 0 is output.

8. The digital baseband system of claim 7, wherein the threshold value of said adaptive threshold Schmitt trigger is adaptively adjusted according to the RSSI, and the decision coefficient is dynamically configured according to the channel environment.

9. The digital baseband system for the wireless sensor network node chip according to claim 1 or 2, wherein the gain decision threshold of the automatic gain control unit (53) is (k-1)/k of the maximum value of LQI and RSSI, where k represents a decision coefficient;

the automatic gain control unit (53) has four states in implementing gain control: an initial state, a locked state, an increased gain state, and a decreased gain state; in any state, when LQI is smaller than (k-1)/k of the maximum value and RSSI is smaller than (k-1)/k of the maximum value, entering a gain increasing state from the current state; in any state, when LQI is less than (k-1)/k of the maximum value and RSSI is greater than (k-1)/k of the maximum value, entering a gain reduction state from the current state; in any state, entering a locked state when LQI is greater than (k-1)/k of its maximum value; when the values of LQI and RSSI are both larger than the respective historical values, the LQI and RSSI are out of the locking state, the corresponding values are stored in a maximum value register, then the LQI and RSSI enter the initial state, and gain adjustment is carried out again until the LQI and RSSI are in the locking state.

10. The digital baseband system for a wireless sensor network node chip according to claim 9, wherein the threshold initial value, the gain initial value and the decision coefficient k of the automatic gain control unit (53) are all set by a user.

11. The digital baseband system for a wireless sensor network node chip according to claim 1 or 2, characterized in that the generator polynomial coefficients of the cyclic code checker (54) are configured according to user needs.

12. The digital baseband system for the wireless sensor network node chip of claim 2, wherein the carrier leakage suppression module (55) comprises an AD sampling unit (551), a low pass filtering unit (552), a sliding window integrating unit (553), and a dc compensation algorithm unit (554); the baseband signal is subjected to AD sampling by the AD sampling unit (551), low-pass filtering by the low-pass filtering unit (552) and integration by the sliding window integrating unit (553) in sequence to obtain the direct current intensity of the transmitting signal, and a compensation value for inhibiting carrier leakage is generated by the direct current compensation algorithm unit (554) according to the direct current intensity of the transmitting signal.

13. A chip for a wireless sensor network node, characterized in that it comprises a digital baseband system according to one of claims 1 to 11.

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