CN102044479A - Method for forming semiconductor device - Google Patents
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- CN102044479A CN102044479A CN2009101971153A CN200910197115A CN102044479A CN 102044479 A CN102044479 A CN 102044479A CN 2009101971153 A CN2009101971153 A CN 2009101971153A CN 200910197115 A CN200910197115 A CN 200910197115A CN 102044479 A CN102044479 A CN 102044479A
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Abstract
The invention relates to a method for forming a semiconductor device. The method comprises the following steps of: providing a semiconductor substrate; directly forming an interlaminar insulating layer on the semiconductor substrate, and forming a protective layer on the interlaminar insulating layer; forming patterned photoresist on the protective layer; etching the protective layer and the interlaminar insulating layer by using the patterned photoresist as a mask, and exposing the semiconductor substrate to form a metal channel; and filling metal in the metal channel to form metal leads. The method has the advantages that the interlaminar insulating layer is directly formed on the semiconductor substrate without depositing a barrier layer, which can lighten the damage to the protective layer in subsequent etching processes, guarantee that the characteristic size of the opening part of the metal channel cannot be enlarged, guarantee that a sufficient effective spacing distance can be reserved between adjacent metal leads and improve the electrical insulating property of the device.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor device, relate in particular to a kind of formation method of semiconductor device.
Background technology
Along with the develop rapidly of semiconductor device manufacturing technology, integrated circuit fabrication process becomes and becomes increasingly complex with meticulous.In order to improve integrated level, to reduce manufacturing cost, the critical size of element constantly diminishes, number of elements in the chip unit are constantly increases, plane routing has been difficult to satisfy the requirement that the element high density distributes, can only adopt polylaminate wiring technique, utilize the vertical space of chip, further improve the integration density of device.
At present, on the backend process that semiconductor device is made, generally be on semiconductor device, to form the first metal layer, be conducted by metal plug (plug) between the first metal layer and the semiconductor device, on the first metal layer, form second metal level again, be conducted by connector (via) between the first metal layer and second metal level, can also on second metal level, form the 3rd metal level and be conducted by connector.Every layer of metal level all comprises interlayer dielectric layer and is embedded in plain conductor in the interlayer dielectric layer.
The formation method of the plain conductor of plain conductor, especially copper material generally comprises following steps:
Referring to Fig. 1 a, provide Semiconductor substrate;
As shown in the figure, this Semiconductor substrate 10 is for having formed the silicon substrate of a plurality of metal-oxide-semiconductors, also formed the metal plug 100 that is connected with the active area and the grid of metal-oxide-semiconductor on the silicon substrate, corresponding therewith, follow-up will formation and the first metal layer of a plurality of metal plug 100 conductings.The preferred tungsten of the material of metal plug.
Certainly, can also be formed with metal level on the Semiconductor substrate, corresponding therewith, follow-up will formation and the another metal level of this metal level conducting.Be example only with the forming process of the first metal layer herein.
Referring to Fig. 1 b, on Semiconductor substrate, form interlayer dielectric layer;
The forming process of this interlayer dielectric layer 12 comprises successively: form barrier layer 121 on Semiconductor substrate, the material on barrier layer is the silicon nitride (NDC) of carbon dope, and the barrier layer is used to keep the stability of Semiconductor substrate; On barrier layer 121, form interlayer insulating film 122, the material of interlayer insulating film be the silica that mixes of carbon (Black Diamond, BD), interlayer insulating film is to be used for the main material that inter-level dielectric is isolated, it has the advantage that dielectric constant is low, transmission delay is little; Form protective layer 123 on interlayer insulating film 122, the material of protective layer is a silicon dioxide, be raw material formation with tetraethoxysilance (TEOS), and protective layer compactness is good, can play a protective role to interlayer insulating film.
Referring to Fig. 1 c, on interlayer dielectric layer, form the photoresist of patterning;
Spin coating photoresist on interlayer dielectric layer 12, soft baking makes light see through mask photoresist is exposed, and the back of developing forms the photoresist 13 of patterning.
Referring to Fig. 1 d, be mask with the photoresist of patterning, the etching interlayer dielectric layer forms metal valley to the exposure Semiconductor substrate.
At first, be mask with the photoresist 13 of patterning, the etching protective layer forms patterned protective layer; Secondly, the photoresist with patterning is a mask again, the etching interlayer insulating film, and the interlayer insulating film of formation patterning, this etching is terminal point with the barrier layer; At last, continue etching barrier layer again, the exposure Semiconductor substrate forms metal valley 14, and the metal plug 100 that metal valley 14 exposures need be electrically connected can be removed the technology that remains photoresist afterwards.
Referring to Fig. 1 e, in metal valley, fill metal, form plain conductor, a plurality of plain conductors promptly constitute described the first metal layer.
Can in metal valley 14, form Ta or TaN resilient coating earlier, and then fill metal.Metallic copper has been widely used in the metal interconnected circuit framework owing to have high-melting-point, low-resistance coefficient, and especially reaching in the more advanced technology in 130 nanometers becomes topmost interconnecting metal material.Carry out CMP technology afterwards again, adopt the mode of cmp that the metal that exceeds metal valley is carried out planarization and remove metal on the interlayer dielectric layer, CPM technology is grinding endpoint with the interlayer dielectric layer, forms plain conductor 15.
Electrical property in order to ensure the chip of follow-up formation, need carry out electrical properties to plain conductor measures, wherein one is the electrical insulation capability test between the adjacent metal lead, method is to add certain voltage between adjacent two plain conductors, the direct current of 40V for example, and whether the electric current of measuring between these two plain conductors surpasses certain limit, if surpass, illustrate that the leakage current between these two plain conductors is bigger, the formation technology of plain conductor is undesirable, must improve.Along with the microminiaturization development of semiconductor element, the distance between the plain conductor is more and more littler, and the leakage problem between the plain conductor is more and more outstanding.
Summary of the invention
Technical problem to be solved by this invention is that the formation method to plain conductor in the semiconductor fabrication process improves, overcomes in the prior art, and along with reducing of semiconductor element size, the deficiency that the leakage phenomenon between the plain conductor is serious.
The technical solution adopted in the present invention is: a kind of formation method of semiconductor device comprises the steps: to provide Semiconductor substrate; Directly on Semiconductor substrate, form interlayer insulating film, on interlayer insulating film, form protective layer; On protective layer, form the photoresist of patterning; Photoresist with patterning is mask etching protective layer and interlayer insulating film, and the exposure Semiconductor substrate forms metal valley; In metal valley, fill metal, form plain conductor.
Preferably, after the formation interlayer insulating film, before the formation protective layer, also comprise the step that forms adhering layer with ammonia processing interlayer insulating film.
Because the enforcement of technique scheme; the present invention has the following advantages: directly form interlayer insulating film on Semiconductor substrate; and deposited barrier layer not; can alleviate injury in the subsequent etching process to protective layer; the characteristic size that guarantees metal groove opening portion is not extended; guaranteeing has enough significant interval distances between the adjacent metal lead, improve the electrical insulation capability of device.Adopt ammonia to handle interlayer insulating film, the plating phenomenon in the time of can avoiding forming metal plug plays the effect that improves the device electrical insulation capability equally.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 a to 1e is the forming process of the plain conductor of prior art;
Fig. 2 is to the analysis chart of leakage phenomenon between the plain conductor in the prior art;
Fig. 3 is the process chart of embodiment one;
Fig. 4 a to Fig. 4 g is the schematic flow sheet of embodiment one;
Fig. 5 c to Fig. 5 g is the schematic flow sheet of embodiment two;
Fig. 6 is the electrical insulation capability test result comparison diagram of embodiment two and prior art.
Embodiment
[embodiment one]
Referring to Fig. 2, be the schematic diagram of the first metal layer that forms in the prior art, the leakage current between first plain conductor 151 and second plain conductor 152 is bigger.The inventor adopts SEM (secondary electron microscope) that device is carried out labor; discovery is at the peristome of metal valley; protective layer is subjected to over etching; the sidewall that causes the metal valley peristome is to the protective layer intramedullary expansion; in protective layer; significant interval distance D between first plain conductor 151 and second plain conductor 152 furthers, and causes leakage current to increase.
By analysis, the inventor finds that the main cause that causes protective layer to be subjected to over etching is when the dry etching barrier layer, simultaneously also to an etching protection layer part, because the etching selectivity of two kinds of films is not high.After protective layer sustains damage, cause the opening of metal valley to increase, form top hem width trapezoidal down, fill metal afterwards when forming plain conductor in metal valley, the distance between the adjacent metal lead is just furthered, and influence leakage current and tests effect.
For above-mentioned phenomenon is improved, the inventor proposes a kind of semiconductor device formation method of improvement, referring to Fig. 3, comprises the steps:
S1 provides Semiconductor substrate; S2 forms interlayer insulating film on Semiconductor substrate, form protective layer on interlayer insulating film; S3, the photoresist of formation patterning on protective layer; S4 is the mask etching protective layer with the photoresist of patterning, is the mask etching interlayer insulating film with the photoresist of patterning, and the exposure Semiconductor substrate forms metal valley; S5 fills metal in metal valley, form plain conductor.
Referring to Fig. 4 a to 4g, be example with the forming process of the first metal layer, present embodiment is described in detail.
S1 provides Semiconductor substrate.
Described Semiconductor substrate can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes or the substrate that is not patterned.
Referring to Fig. 4 a, this Semiconductor substrate 20 is for having formed the silicon substrate of a plurality of metal-oxide-semiconductors, also formed the metal plug 200 that is connected with the active area and the grid of metal-oxide-semiconductor on the silicon substrate, corresponding therewith, follow-up will formation and the first metal layer of a plurality of metal plug 200 conductings.The preferred tungsten of the material of metal plug.
Certainly, can also be formed with metal level on the Semiconductor substrate 20, corresponding therewith, follow-up will formation and the another metal level of this metal level conducting.Be example only with the forming process of the first metal layer herein.
S2 forms interlayer insulating film on Semiconductor substrate, form protective layer on interlayer insulating film;
Referring to Fig. 4 b, on Semiconductor substrate 20, form interlayer insulating film 21, in the present embodiment, do not form the step on barrier layer, therefore the follow-up step that does not yet have etching barrier layer.
Described interlayer insulating film 21 materials are selected from the silica that carbon mixes, and (Black Diamond, BD), described interlayer insulating film 21 thickness are 3500 dust to 4500 dusts.
Described interlayer insulating film 21 is used for inter-level dielectric and isolates, and the interlayer insulating film 21 of the silica that described carbon mixes is low except having dielectric constant, the advantage that transmission delay is little, also possess with barrier layer 120 selective etchings than high advantage.
Described interlayer insulating film 21 forms technology and can select the medium chemical vapor depsotition equipment for use, concrete technological parameter is: reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure is that 4 holders are to 6 holders, power is 400 watts to 600 watts, oxygen flow is that per minute 100 standard cubic centimeters are to per minute 300 standard cubic centimeters, helium gas flow is that per minute 800 standard cubic centimeters are to per minute 1200 standard cubic centimeters, prestox cyclisation tetrasiloxane flow is that per minute 2000 standard cubic centimeters are to per minute 4000 standard cubic centimeters, until the interlayer insulating film 21 that forms 3500 dust to 4500 dusts.
Referring to Fig. 4 c, on interlayer insulating film 21, form protective layer 22.
Described protective layer 22 materials are selected from silicon dioxide, and described protective layer 22 compactness are good, can play the effect of protection interlayer insulating film 21.
Described protective layer 22 forms technology and can select low-pressure chemical vapor deposition (LPCVD) equipment for use; concrete technological parameter is: reaction chamber pressure is 6 to 9 holders; reaction temperature is that 300 degree are to 500 degree; reacting gas is TEOS (tetraethoxysilance) and oxygen; with the helium is carrier gas, thereby generates silicon dioxide (SiO
2).The thickness of protective layer 22 is 150 dust to 600 dust scopes.
S3, the photoresist of formation patterning on protective layer.
At described protective layer 22 surperficial spin coating photoresists; then by exposure with on the mask with the corresponding figure transfer of metal valley to photoresist; utilize developer solution that the photoresist of corresponding site is removed then, to form the photoresist 23 of patterning, referring to Fig. 4 d.The photoresist 23 of described patterning is used for defining the metal valley figure.
S4 is the mask etching protective layer with the photoresist of patterning, with the photoresist of patterning be the mask etching interlayer insulating film to the exposure Semiconductor substrate, form metal valley.
Described etching technics can be known plasma etching or chemical reagent etching, in the present embodiment, is exemplary illustrated with the plasma etching.
The technology of etching protective layer 22 can be: the etching apparatus chamber pressure is 100 millitorr to 200 millitorrs, and the top radio-frequency power is 700 watts to 900 watts, and the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow be per minute 10 standard cubic centimeters to per minute 50 standard cubic centimeters, the CO flow be per minute 100 standard cubic centimeters to per minute 200 standard cubic centimeters, the Ar flow is that per minute 300 standard cubic centimeters are to per minute 600 standard cubic centimeters, O
2Flow is that per minute 10 standard cubic centimeters are to per minute 50 standard cubic centimeters.
The technology of etching interlayer insulating film can be: etching apparatus chamber pressure 100 millitorr to 200 millitorrs, 100 to 200 watts of top radio-frequency powers, 400 to 500 watts of bottom radio-frequency powers, CF
4Flow is per minute 100 standard cubic centimeter to 150 standard cubic centimeters, CHF
3Flow is per minute 8 to 13 standard cubic centimeters, and the Ar flow is that per minute 150 standard cubic centimeters are to per minute 300 standard cubic centimeters, O
2Flow is less than per minute 1 standard cubic centimeter.Wore interlayer insulating film and over etching quarter 2 seconds, and formed metal valley 24, referring to Fig. 4 e.CHF
3Adding can guarantee that protective layer is injury-free when the etching interlayer insulating film.
Owing in preceding road technology, do not adopt the barrier layer; etching herein only needs to consider protective layer and interlayer insulating film, and protective layer is dense, and the quality of interlayer insulating film is more loose; the etching selection of the two is bigger, therefore can protect the opening size of protective layer also not extended.Referring to Fig. 4 e, after etching finished, the characteristic size of protective layer pattern there was not expansion.
Referring to Fig. 4 f, remove the photoresist 23 of patterning.Adopt cineration technics, the concrete parameter of described cineration technics is: the etching apparatus chamber pressure is 50 millitorr to 100 millitorrs, and radio-frequency power is 300 watts to 500 watts, O
2Flow is that per minute 50 standard cubic centimeters are to per minute 250 standard cubic centimeters, N
2Flow be per minute 20 standard cubic centimeters to per minute 40 standard cubic centimeters, the CO flow is that per minute 50 standard cubic centimeters are to per minute 90 standard cubic centimeters.
S5 fills metal in metal valley, form plain conductor.
The material of described metal is selected from aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is selected from the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.In the present embodiment, because metallic copper has the ability of high-melting-point, low-resistance coefficient and high anti-electron transfer, preferably do exemplary illustrated with copper.
Before filling copper; usually also can in metal valley 24, (being the sidewall and the bottom of metal valley 24) form resilient coating 25; described cushioning layer material is selected from tantalum, tantalum nitride, titanium or titanium nitride; described resilient coating can be single layer structure or multilayer overlaying structure, and described resilient coating is used to stop metal material to spread in Semiconductor substrate 20, interlayer dielectric layer 21 and protective layer 22.The technology on described formation barrier layer can be known depositing operation, for example physical gas-phase deposition or chemical vapor deposition method.
Form after the resilient coating 25; the copper seed crystal of on resilient coating 25, growing; the physical gas-phase deposition of usefulness or electroplating technology are filled copper in metal valley then; adopt worn unnecessary copper, the exposure protective layer 22 that is deposited on the protective layer 22 of CMP technology afterwards again; form plain conductor 26, also promptly form the first metal layer.
In S4 technology; the opening shape protection characteristic size comparatively complete, opening of protective layer is not extended; in S5 technology; the characteristic size at plain conductor 26 tops is not extended near preset value, plain conductor 26 tops; significant interval distance between the adjacent metal lead 26 can be guaranteed; guarantee that electrical insulation capability between the adjacent metal lead 26 is better, leakage current is less, guarantee the reliability of semiconductor device.
[embodiment two]
The semiconductor device that adopts above-mentioned technology to form, the leakage current between the adjacent metal lead reduces, but still has room for improvement.The inventor finds that when filling metallic copper in metal valley 24, copper toward the faying face diffusion of interlayer dielectric layer 21 with protective layer 22, causes the plating phenomenon easily, causes the leakage current of adjacent metal lead to increase.
In order to improve the plating phenomenon, the inventor proposes further improved process, and this technology and technology shown in Figure 3 are roughly the same; only after forming interlayer dielectric layer 21; adopt ammonia to handle interlayer dielectric layer 21, form adhering layer 27, on adhering layer 27, form protective layer 22 afterwards.
The processing step of this embodiment can be referring to the description of Fig. 4 a, Fig. 4 b, Fig. 5 c to Fig. 5 g.
Referring to Fig. 4 a, provide Semiconductor substrate 20;
Referring to Fig. 4 b, on Semiconductor substrate 20, form interlayer insulating film 21;
Referring to Fig. 5 c, adopt ammonia that interlayer insulating film 21 is handled, form adhering layer 27, on adhering layer 27, form protective layer 22;
Referring to Fig. 5 d, on protective layer 22, form the photoresist 23 of patterning;
Referring to Fig. 5 e, be mask etching protective layer 22 with the photoresist 23 of patterning, be mask etching adhering layer 27 with the photoresist 23 of patterning, be mask etching interlayer insulating film 21 with the photoresist 23 of patterning, exposure Semiconductor substrate 20 forms metal valley 24;
Referring to Fig. 5 f, remove the photoresist 23 of patterning;
Referring to Fig. 5 g, in metal valley 24, fill metal, form plain conductor 26.
Repeat no more with embodiment one same section in the above technology, the technology that wherein adopts ammonia to handle interlayer dielectric layer 21, formation adhering layer 27 is:
Board is the board on growth barrier layer, 500 to 600 watts of power, and treatment temperature is 350 to 450 degree, chamber pressure 3.5 to 4.5 holders, ammonia flow 900 to 1200 standard cubic centimeters, the processing time is 15 to 25 seconds, forming thickness is the adhering layer 27 of 150 dust to 600 dusts.The material of interlayer insulating film 21 is the silica that carbon mixes; the material of protective layer 22 is a silica; adhering layer 27 can increase the nitrogen content in the interlayer insulating film 21; adhering layer 27 is self dense materials not only; and can increase the degree of adhesion of interlayer insulating film 21 and protective layer 22; avoid the generation in slit, the plating phenomenon when reducing plain conductor 26 formation can further reduce the leakage current between the plain conductor 26.
The plain conductor that adopts present embodiment technology to form is compared the plain conductor that adopts existing technology to form, and the tolerance of voltage is had clear improvement.Referring to Fig. 6, abscissa is withstand voltage Vb, and Vb leaks electricity when flowing to predetermined value by adding direct voltage between adjacent two plain conductors, measuring, and the numerical value of direct voltage is withstand voltage Vb; Ordinate is the cumulative distribution function, is meant corresponding to a certain abscissa value, and withstand voltage accounts for the ratio of device sum less than the device of this abscissa value.Among Fig. 6, the data of square (series 2) expression present embodiment, the data of the existing technology of rhombus (series 1) expression, as shown in the figure, by implementing this technology, corresponding to a certain abscissa, rhombus is positioned at the square top, show existing technology can not tolerate that device is more, can not to tolerate device after the technology that adopts this enforcement less, adopts this technology can improve withstand voltage between the adjacent metal lead, the electrical insulation capability of enhance device.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the formation method of a semiconductor device comprises the steps:
Semiconductor substrate is provided;
Directly on Semiconductor substrate, form interlayer insulating film, on interlayer insulating film, form protective layer;
On protective layer, form the photoresist of patterning;
Photoresist with patterning is mask etching protective layer and interlayer insulating film, and the exposure Semiconductor substrate forms metal valley;
In metal valley, fill metal, form plain conductor.
2. method according to claim 1, it is characterized in that: described plain conductor is the plain conductor of the first metal layer, described Semiconductor substrate comprises the metal plug between semiconductor device and described semiconductor device and the first metal layer, and the material of described metal plug is a tungsten.
3. method according to claim 1 is characterized in that: the material of described interlayer insulating film is the silica that carbon mixes.
4. method according to claim 3, it is characterized in that: the formation technology of described interlayer insulating film is: the medium chemical vapor depsotition equipment, reaction temperature is 300 degrees centigrade to 400 degrees centigrade, chamber pressure is that 4 holders are to 6 holders, power is 400 watts to 600 watts, oxygen flow is that per minute 100 standard cubic centimeters are to per minute 300 standard cubic centimeters, helium gas flow be per minute 800 standard cubic centimeters to per minute 1200 standard cubic centimeters, prestox cyclisation tetrasiloxane flow is that per minute 2000 standard cubic centimeters are to per minute 4000 standard cubic centimeters.
5. method according to claim 1 is characterized in that: the material of described protective layer is a silicon dioxide.
6. method according to claim 5; it is characterized in that: the formation technology of described protective layer is: low pressure chemical vapor deposition equipment, reaction chamber pressure are 6 to 9 holders, and reaction temperature is that 300 degree are to 500 degree; reacting gas is tetraethoxysilance and oxygen, is carrier gas with the helium.
7. method according to claim 1 is characterized in that: the material of described plain conductor is a copper.
8. method according to claim 1; it is characterized in that: also comprise after the described formation interlayer insulating film, form before the protective layer; handle the step that interlayer insulating film forms adhering layer with ammonia, protective layer is formed on the described adhering layer, and the material of described adhering layer is the nitrogen doped silicon oxide.
9. method according to claim 8, it is characterized in that: described step with ammonia processing interlayer insulating film formation adhering layer is: treatment temperature is 350 to 450 degree, chamber pressure 3.5 to 4.5 holders, ammonia flow 900 to 1200 standard cubic centimeters, the processing time is 15 to 25 seconds.
10. according to carving the described method of claim 1, it is characterized in that: the technology of described etching interlayer insulating film is etching apparatus chamber pressure 100 millitorr to 200 millitorrs, 100 to 200 watts of top radio-frequency powers, 400 to 500 watts of bottom radio-frequency powers, CF
4Flow is per minute 100 standard cubic centimeter to 150 standard cubic centimeters, CHF
3Flow is per minute 8 to 13 standard cubic centimeters, and the Ar flow is that per minute 150 standard cubic centimeters are to per minute 300 standard cubic centimeters, O
2Flow is less than per minute 1 standard cubic centimeter.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI501317B (en) * | 2012-07-26 | 2015-09-21 | ||
| CN104344981B (en) * | 2013-08-05 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of TEM sample |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1614764A (en) * | 2003-11-06 | 2005-05-11 | 株式会社瑞萨科技 | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1614764A (en) * | 2003-11-06 | 2005-05-11 | 株式会社瑞萨科技 | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI501317B (en) * | 2012-07-26 | 2015-09-21 | ||
| CN104344981B (en) * | 2013-08-05 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of TEM sample |
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