CN102044439A - Manufacture method of active area - Google Patents
Manufacture method of active area Download PDFInfo
- Publication number
- CN102044439A CN102044439A CN200910197673XA CN200910197673A CN102044439A CN 102044439 A CN102044439 A CN 102044439A CN 200910197673X A CN200910197673X A CN 200910197673XA CN 200910197673 A CN200910197673 A CN 200910197673A CN 102044439 A CN102044439 A CN 102044439A
- Authority
- CN
- China
- Prior art keywords
- sige
- condensate
- active area
- msa
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a manufacture method of an active area. The method comprises the following steps of: forming a polysilicon gate electrode on a silicon substrate; constructing silicon substrate dents at both sides of the polysilicon gate electrode; filling a Si-Ge polymer into the silicon substrate dents; constructing a source electrode and a drain electrode based on the Si-Ge polymer; and carrying out laser quick thermal annealing MSA (Measurement System Analysis) treatment on a wafer, controlling the MSA treatment temperature to be between 1150 DEG C to 1250 DEG C and controlling laser scanning time between 650 microseconds to 750 microseconds. The invention can effectively lessen the stress relaxation occurring on a Si-Ge polymer layer.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, particularly the manufacture method of active area.
Background technology
The metal oxide layer semiconductor field-effect transistor, be called for short metal-oxide half field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), be a kind of field-effect transistor (field-effect transistor) that can be widely used in analogous circuit and digit circuit.MOSFET can be divided into the MOSFET of n-type and p-type according to the polarity difference of its " passage ", is called NMOSFET and PMOSFET usually again, and other are called for short and also comprise NMOS FET, PMOSFET, nMOSFET, pMOSFET etc.
In the manufacture process of MOSFET, include the manufacturing in source region, Fig. 1 a is the profile of typical active area, and the manufacture method of active area is a flow process shown in Figure 2 at present, and this method may further comprise the steps:
Step 201: on silicon base 101, form polysilicon gate (G) 104.Described polysilicon gate comprises gate oxide and the polysilicon layer that is positioned at successively on the silicon base.
Step 202: carry out etching in polysilicon gate (G) 104 two side areas, structure silicon base 101 depressions.
This step specifically comprises: carry out photoetching earlier, form the photoetching district in polysilicon gate (G) 104 two side areas; Then, the photoetching district is etched into certain depth form depression, shown in Fig. 1 b.
Step 203: in silicon base 101 depressions of structure, insert SiGe condensate (Si
1-xGe
x).
In the depression of step 202 structure, carry out epitaxial growth, insert the SiGe condensate.
Step 204: with described SiGe condensate is base configuration source electrode (S) 103 and drain electrode (D) 102.
This step specifically comprises: based on described SiGe condensate, carry out ion and inject.
Step 205: wafer is carried out laser rapid thermal annealing (MSA, Milliseconed Anneal) handle, the temperature of carrying out the MSA processing is controlled at about 1250 degrees centigrade, and the laser scanning time is 800 microseconds (um).
When MSA handles, scan realization annealing fast by wafer being carried out laser, at present, the temperature of laser scanning surface is chosen as about 1250 degrees centigrade, and the selection of time of wafer being carried out laser scanning is 800um.
The core of MOSFET is the mos capacitance that is positioned at central authorities, and the left and right sides then is its source electrode and drain electrode.The characteristic of source electrode and drain electrode must be all n-type (being NMOS) or be all p-type (being PMOS).If be NMOS, source electrode shown in Figure 1 has " N+ ", " N+ " representing two meanings with upward normal sign that drain: (1) N representative doping (doped) impurity polarity in source electrode and drain region is N; (2) on behalf of this zone, "+" be high-dopant concentration zone (heavily doped region), and just the electron concentration in this district is far above other zones.Between source electrode and drain electrode, separated just so-called base stage (or claiming matrix) zone by an opposite polarity zone.If NMOS, the doping of its matrix area is exactly p-type so.Otherwise for PMOS, matrix should be n-type, and source electrode and drain electrode then are p-type (and being heavily doped P+).The doping content of matrix does not need as source electrode or drain electrode so high.
Recent decades in past, the size of MOSFET constantly diminishes.In the early stage semiconductor circuit MOSFET processing procedure, passage length is about several microns grade.But to the semiconductor circuit processing procedure of today, this parameter has been dwindled tens times even above 100 times.To the end of the nineties, the MOSFET size is constantly dwindled, and allows the usefulness of semiconductor circuit promote greatly, and from viewpoint of history, the progress of these technical breakthroughs and manufacture of semiconductor has the inseparable relation of work.At the beginning of 2006, Intel begins to make the microprocessor of a new generation, and actual element passage length is also more and more littler.Along with the area of MOSFET is more little, the cost of making chip just can reduce, and can load more highdensity chip in same encapsulation.The wafer size that a slice integrated circuit processing procedure uses is fixed, so if chip area is more little, onesize wafer just can the more chip of output, so that cost just becomes is lower.
But the reducing of MOSFET size also can bring some negative problems.For example, channel width diminishes and can make passage equivalent electric resistive big.Therefore, often adopt the mode that increases stress to improve mobility, and then increase current strength for the less MOSFET of critical size.The stress of passage area can change the level structure of silicon, and tensile stress can improve electron mobility, and compression stress can improve hole mobility.
In the flow process of Fig. 2, what adopt in the step 203 is that the SiGe condensate caves in and inserts, and can improve the performance of MOS like this.Because the lattice constant (lattice constant) of SiGe polymer reduces, thereby improve the intensity of hole mobility and then rising drive current under the effect of compression stress.Also adopt silicon to replace the polymeric effect of SiGe in some cases; When adopting silicon, then do not need to carry out 202 and 203.The SiGe condensate is compared with silicon, and the ion that step 204 is injected when adopting the SiGe condensate has higher activity, thereby the resistance of the source-drain electrode of SiGe condensate formation is lower, and the MOSFET that makes at last has more performance.And by changing the concentration of Ge in the SiGe condensate, this technology can be applied to the processing procedure of reduced size.The SiGe condensate source-drain electrode that adopts meticulous controlled doping concentration to make with low resistance characteristic, and be control complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, the CMOS) key factor of size by the short-channel effect that minimizes that the shallow-layer doping way forms.
In the flow process of Fig. 2, the MSA that step 205 adopts handles has very high annealing temperature, and the duration is very short, when higher doping activity is provided, reduced the doping diffusivity, gradually as the necessary step in the high-performance CMOS device fabrication.
Select parameter to be when carrying out MSA in the prior art: be 800us sweep time (dwell time), and scanning temperature (Temp) is about 1250 degrees centigrade.Adopt this parameter combinations, can cause the SiGe condensate in the source-drain electrode under hot environment, stress relaxation to occur; Occur at the SiGe condensate under the effect of stress relaxation, the SiGe condensate may relative displacement occur and cause stacked dislocation (the OVL problem often is embodied on the wafer distortion for Overlay, OVL) problem etc., and then causes device performance to descend; And bad situation also appears at from the SiGe polymer layer and spreads to the defective of going deep into silicon base, causes connecting leak rate and significantly rises.Therefore, reducing the SiGe condensate stress relaxation occurs and becomes problem that urgent need overcomes in the semiconductor integrated circuit manufacturing process.
Summary of the invention
In view of this, the present invention proposes a kind of manufacture method of active area, can effectively reduce the stress relaxation that the SiGe polymer layer occurs.
A kind of manufacture method of active area, this method comprises:
On silicon base, form polysilicon gate;
In polysilicon gate both sides structure silicon base depression;
The SiGe condensate is inserted the recess of silicon base;
With described SiGe condensate is base configuration source electrode and drain electrode;
Wafer is carried out laser rapid thermal annealing MSA handle, the temperature that will carry out the MSA processing is controlled between 1150 degrees centigrade to 1250 degrees centigrade, and the laser scanning time is controlled between 650 microsecond to 750 microseconds.
Preferably, the temperature that MSA handles is chosen as 1214 degrees centigrade, and the laser scanning time is 700 microseconds.
Preferably, for N type metal oxide semiconductor field-effect transistor, described is that base configuration source electrode and drain electrode comprise with described SiGe condensate:
Based on described SiGe condensate, inject arsenic or phosphorus.
Preferably, for the P-type mos field-effect transistor, described is that base configuration source electrode and drain electrode comprise with described SiGe condensate:
Based on described SiGe condensate, inject boron or boron fluoride.
From such scheme as can be seen, the present invention forms polysilicon gate on silicon base in the process of making active area; In polysilicon gate both sides structure silicon base depression, the SiGe condensate is inserted the recess of silicon base, be base configuration source electrode and drain electrode with described SiGe condensate again, then, wafer is carried out MSA to be handled, the temperature of carrying out the MSA processing is controlled between 1150 degrees centigrade to 1250 degrees centigrade, and the laser scanning time is controlled between the 650um to 750um.Know according to experimental data, the temperature that MSA is handled is controlled between 1150 degrees centigrade to 1250 degrees centigrade, and the laser scanning time is controlled between the 650um to 750um, in prior art, temperature is controlled at about 1250 degrees centigrade, and laser scanning selection of time 800um, can effectively reduce the stress relaxation that the SiGe polymer layer occurs more, to reduce wafer distortion better; And, can activate effectively and inject the polymeric ion of SiGe, make the ion that places SiGe polymer lattice gap can place the polymeric lattice of SiGe, improve the conductivity of lattice, thereby, improve the performance of active area, and then improve the performance of the last MOSFET that forms.
According to experimental data, take all factors into consideration the MSA parameter combinations to wafer distortion with activation is mixed the effect of the polymeric ion of SiGe two aspects, the present invention has also determined one group of more excellent MSA processing parameter: temperature is chosen as 1214 degrees centigrade, and the laser scanning selection of time is 700us.
Description of drawings
Fig. 1 is the basic structure schematic diagram of active area of the prior art, comprises Fig. 1 a and Fig. 1 b;
Fig. 2 is a method flow diagram of making active area in the prior art;
Fig. 3 makes the method flow diagram of active area for the present invention;
Fig. 4 is the OVL that shows by lithography apparatus.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with embodiment and accompanying drawing, the present invention is described in more detail.
Make the method flow diagram of active area referring to Fig. 3 for the present invention, the active area of manufacturing can be referring to structure shown in Figure 1, and this method may further comprise the steps:
Step 301: on silicon base 101, form polysilicon gate (G) 104.Described polysilicon gate comprises gate oxide and the polysilicon layer that is positioned at successively on the silicon base.
Step 302: carry out etching in polysilicon gate (G) 104 two side areas, structure silicon base 101 depressions.
This step specifically comprises: carry out photoetching earlier, form the photoetching district in polysilicon gate (G) 104 two side areas; Then, the photoetching district is etched into certain depth form depression, shown in Fig. 2 b.
Step 303: in silicon base 101 depressions of structure, insert the SiGe condensate.
In the depression of step 202 structure, carry out epitaxial growth, insert the SiGe condensate.
Step 304: with described SiGe condensate is base configuration source electrode (S) 103 and drain electrode (D) 102.
This step specifically comprises: based on described SiGe condensate, carry out ion and inject.
For N type metal oxide semiconductor field-effect transistor (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor), the alloy that this step is injected is arsenic or phosphorus.Usually, can adopt arsenic ion to carry out alloy and inject, selecting arsenic and not selecting the reason of phosphorus is that the molecular weight of arsenic is bigger, and it is decrystallized to help substrate surface, can access more uniform doping depth in injection.
For P type MOSFET, the alloy that this step is injected is boron or boron fluoride.
Step 305: wafer is carried out MSA handle, the temperature of carrying out the MSA processing is controlled between 1150 degrees centigrade to 1250 degrees centigrade, and the laser scanning time is controlled between the 650um to 750um.
Be formed with after the source region, (CT Contact),, regards the active area that forms as preceding one deck here, and the contact hole that will form on active area is as back one deck need to form contact hole on the source electrode of active area (AA), drain and gate.Can realize being connected of active area and extraneous circuit by contact hole.
Be specifically described forming contact hole below.
The process that forms contact hole comprises: at the crystal column surface resist coating, by exposure imaging the photoresistance glue-line is carried out the contact hole photoetching.
After the photoetching,, can know the position of contact hole after the photoetching by lithography apparatus; Contact hole forms in grid, source electrode and the drain electrode of active area, the position of one deck active area after just can knowing by the position of contact hole after the photoetching of knowing, and the position of active area generally refers to the center of active area.The position of active area can be represented by gate location, also can represent by the center of source electrode and drain electrode.Particularly,, at this moment gate location is considered as the center of active area, has determined the position of grid contact hole after the photoetching, just determined the center of active area for the situation that the position of active area is represented by gate location.Situation is represented by the center of source electrode and drain electrode in position for active area, center between source electrode and the drain electrode is considered as the center of active area, determined contact hole and the center between the contact hole of drain electrode photoetching, just determined the center of active area in the source electrode photoetching.By the center that lithography apparatus just can be obtained back one deck active area, the position that the solid line cross is determined among Fig. 4 just is the center of active area after the photoetching.
Pass through lithography apparatus, the position of the active area that one deck forms before also can knowing, the position of active area can be represented by gate location equally, can represent that also the position of active area generally refers to the center of active area by the center of source electrode and drain electrode.The position that the dotted line cross is determined among Fig. 4 just is the center of preceding one deck active area.
Just, by lithography apparatus, the center of one deck active area before not only can obtaining, the center that can also obtain back one deck active area, as shown in Figure 4.Like this, carry out photoetching after, just can obtain OVL between back one deck and preceding one deck by lithography apparatus, the method for obtaining OVL generally comprises following two kinds: by the acquisition of the skew between back one deck gate location and preceding one deck gate location OVL relatively; Perhaps, the skew acquisition OVL between the center of the center by relatively back one deck source electrode and drain electrode and preceding one deck source electrode and drain electrode.Below the detailed process of obtaining OVL is described.
By lithography apparatus, can obtain the range differences between the position that position that solid line cross among Fig. 4 determines and dotted line cross determine, just, the center of one deck active area and the back OVL between the center of one deck active area before can obtaining.For the situation that the center between source electrode and the drain electrode is considered as the center of active area, OVL is expressed as CT OVL AA, and CT OVL AA represents by numerical value difference on the x axle and the numerical value difference on the y axle; Be considered as the situation of active area position for the position with grid, OVL is expressed as CT OVL poly, and CT OVL poly represents by numerical value difference on the x axle and the numerical value difference on the y axle.Usually adopt the mode of CT OVL poly to represent OVL.
In the step 305, the dwell time that selects when carrying out MSA is different with Temp, correspondingly, CT OVL AA that obtains and CT OVL poly are also inequality, the present invention has carried out repeatedly experiment by selecting different Temp and dwell time combination, obtained reducing the span that stress relaxation appears in the SiGe polymer layer: the temperature that will carry out the MSA processing is controlled between 1150 degrees centigrade to 1250 degrees centigrade, and the laser scanning time is controlled between the 650um to 750um.
Referring to table 1, for selecting CT OVL AA that different dwell time and Temp combination the time obtains and the partial data of CT OVL poly.
CT OVL AA and CT OVL poly numerical value under the combination of table 1 different parameters
Adopt the parameter of selecting when carrying out MSA in the prior art: dwell time is 800us, and Temp is about 1250 degrees centigrade; The CT OVL poly numerical value that obtains is: the deviation on X-axis is 14.4 nanometers (nm), and the deviation on Y-axis is 13.5nm; The CT OVL AA numerical value that obtains is: the deviation on X-axis is 21.2nm, and the deviation on Y-axis is 14.9nm.By with table 1 in be numbered 13 to 19 other respectively organize data and compare, as can be seen, be numbered 12 parameter and have bigger OVL numerical value.
OVL numerical value is more little, shows to have reduced the stress relaxation that the SiGe condensate occurs more effectively, has also just reduced wafer distortion better.
MSA handles except reducing the wafer distortion; Can also repair impaired lattice, the ion that injects in the step 304 can be placed in the polymeric lattice of SiGe.The temperature that MSA selected when handling can not be too high, if too high, then is unfavorable for reducing wafer distortion, but the temperature of selecting can not be low excessively, too low then be unfavorable for activating inject source-drain electrode ion so that it places the polymeric lattice of SiGe.Be elaborated below.
Can enter the polymeric lattice of SiGe if inject the ion of source-drain electrode in the step 304, then be best effect, but in the actual doping process, the ion that has part to inject can not place the SiGe polymer lattice, but place SiGe polymer lattice gap, make lattice not possess conductivity; And the annealing process by later step 304 then can at high temperature activate the ion of injection, makes it to enter in the polymeric lattice of SiGe.Activate the degree of injecting ion, source electrode that can be by testing final formation and the resistance value between the drain electrode are determined, the resistance value that records is more little, show that the electric current between source electrode and the drain electrode is big more, activated the ion that injects source-drain electrode better by annealing process, make the performance of active area of formation better, and then make the performance of MOSFET of last formation better.But annealing temperature is high more, and OVL is big more.Take all factors into consideration temperature to OVL with to activating the effect of injecting ion two aspects, the present invention is controlled at the temperature of MSA between 1150 degrees centigrade to 1250 degrees centigrade,
The present invention takes into account the MSA parameter combinations and mixes the influence of ion two aspects of source-drain electrode to wafer distortion with to activation by repeatedly experiment, and determined one group of preferable MSA parameter value: be chosen as 700us sweep time, temperature is chosen as 1250 degrees centigrade.Be numbered in the table 1 16 data just corresponding this situation, the CT OVL poly numerical value that obtain this moment is: the deviation on X-axis is 9.6nm, and the deviation on Y-axis is 7.5nm; The CT OVL AA numerical value that obtains is: the deviation on X-axis is 13.3nm, and the deviation on Y-axis is 9.8nm.As seen, when selecting this group value, OVL is less; The OVL that records after the photoetching is little, and the distortion of wafer was decreased less after then description of step 304 was annealed.And the resistance value between source electrode by testing final formation and the drain electrode is known also can preferably activate in this case and is injected the polymeric ion of SiGe.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; and be not intended to limit the scope of the invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. the manufacture method of an active area comprises:
On silicon base, form polysilicon gate;
In polysilicon gate both sides structure silicon base depression;
The SiGe condensate is inserted the recess of silicon base;
With described SiGe condensate is base configuration source electrode and drain electrode;
Wafer is carried out laser rapid thermal annealing MSA handle, the temperature that will carry out the MSA processing is controlled between 1150 degrees centigrade to 1250 degrees centigrade, and the laser scanning time is controlled between 650 microsecond to 750 microseconds.
2. the method for claim 1 is characterized in that, the temperature that MSA handles is chosen as 1214 degrees centigrade, and the laser scanning time is 700 microseconds.
3. method as claimed in claim 1 or 2 is characterized in that, for N type metal oxide semiconductor field-effect transistor, described is that base configuration source electrode and drain electrode comprise with described SiGe condensate:
Based on described SiGe condensate, inject arsenic or phosphorus.
4. method as claimed in claim 1 or 2 is characterized in that, for the P-type mos field-effect transistor, described is that base configuration source electrode and drain electrode comprise with described SiGe condensate:
Based on described SiGe condensate, inject boron or boron fluoride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197673A CN102044439B (en) | 2009-10-23 | 2009-10-23 | Manufacture method of active area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197673A CN102044439B (en) | 2009-10-23 | 2009-10-23 | Manufacture method of active area |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102044439A true CN102044439A (en) | 2011-05-04 |
| CN102044439B CN102044439B (en) | 2012-09-26 |
Family
ID=43910460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910197673A Active CN102044439B (en) | 2009-10-23 | 2009-10-23 | Manufacture method of active area |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102044439B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137491A (en) * | 2011-12-01 | 2013-06-05 | 台湾积体电路制造股份有限公司 | Reacted layer for improving thickness uniformity of strained structures |
-
2009
- 2009-10-23 CN CN200910197673A patent/CN102044439B/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137491A (en) * | 2011-12-01 | 2013-06-05 | 台湾积体电路制造股份有限公司 | Reacted layer for improving thickness uniformity of strained structures |
| CN103137491B (en) * | 2011-12-01 | 2016-02-10 | 台湾积体电路制造股份有限公司 | For improving the conversion zone of the thickness evenness of strain structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102044439B (en) | 2012-09-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7211871B2 (en) | Transistors of semiconductor devices and methods of fabricating the same | |
| US8076210B2 (en) | Method for fabricating metal-oxide semiconductor transistors | |
| US20100255666A1 (en) | Thermal processing method | |
| US6200869B1 (en) | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions | |
| CN103367163A (en) | MOSFET with selective dopant deactivation underneath gate | |
| CN104241110A (en) | Method of forming a semiconductor device structure employing fluoring doping and according semiconductor device structure | |
| US6432802B1 (en) | Method for fabricating semiconductor device | |
| US20090152626A1 (en) | Super Halo Formation Using a Reverse Flow for Halo Implants | |
| CN102044439B (en) | Manufacture method of active area | |
| CN102024849A (en) | Metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| US7691714B2 (en) | Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor | |
| Horstmann et al. | Advanced SOI CMOS transistor technologies for high-performance microprocessor applications | |
| JP2006108498A (en) | Method for manufacturing electronic device | |
| US6844228B2 (en) | Manufacturing method of a semiconductor device capable of accurately setting a resistance value of a resistance element | |
| US5913116A (en) | Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer | |
| TW200614387A (en) | Method of fabricating mos transistor by millisecond anneal | |
| US6867080B1 (en) | Polysilicon tilting to prevent geometry effects during laser thermal annealing | |
| US20070114604A1 (en) | Double-extension formation using offset spacer | |
| US9741853B2 (en) | Stress memorization techniques for transistor devices | |
| CN101577229B (en) | Semiconductor element and manufacturing method thereof | |
| CN102315106B (en) | Laser thermal annealing method | |
| US20130230948A1 (en) | Multiple step implant process for forming source/drain regions on semiconductor devices | |
| KR100699462B1 (en) | Schottky Barrier Tunnel Transistor and the Method for Manufacturing the same | |
| Shih et al. | The study of compressive and tensile stress on MOSFET's IV, CV characteristics and it's impacts on hot carrier injection and negative bias temperature instability | |
| CN102087961B (en) | P type doping ultra shallow junction and method for making P-channel metal oxide semiconductor (PMOS) transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121116 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20121116 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |