CN102044421B - Method for manufacturing metal gate - Google Patents
Method for manufacturing metal gate Download PDFInfo
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- CN102044421B CN102044421B CN2009101971030A CN200910197103A CN102044421B CN 102044421 B CN102044421 B CN 102044421B CN 2009101971030 A CN2009101971030 A CN 2009101971030A CN 200910197103 A CN200910197103 A CN 200910197103A CN 102044421 B CN102044421 B CN 102044421B
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- oxide layer
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- metal gate
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Abstract
The invention relates to a method for manufacturing a metal gate, comprising the following steps: firstly providing a wafer with a silicon base, respectively forming a first oxide layer and a second oxide layer on the front surface and the back surface of the silicon base, and respectively forming a first protective layer and a second protective layer on the first oxide layer and the second oxide layer; etching the first protective layer, the first oxide layer and the silicon base; depositing third oxide layers on the first protective layer and an exposed silicon base, and flattening the third oxide layer until the first protective layer is exposed; removing part of the first protective layer by using dry etching; removing the residual first protective layer and part of second protective layer by using wet etching; forming a well region, and removing the first oxide layer by precleaning to form a gate oxide layer; and forming the metal gate. Metal atoms which are exposed out of the side of a grid do not spread to the silicon base, so that the silicon substrate with a certain thickness at the back of the wafer is in no need of removing after the metal gate is etched, thus avoiding the problems that the loss of silicon atoms are resulted from the uneven back surface of the wafer to influence the sequent exposure, and the like.
Description
Technical field
The present invention relates to semiconductor applications, especially a kind of metal gate manufacture method.
Background technology
Make the field at integrated circuit, especially under 32 nanometer technologies, the method for use hafnium and metal gate will be by extensive employing.In the semiconductor manufacturing, there are two kinds of basic etching technics etchings to form metal gate: dry etching and wet etching.Dry etching is to be exposed to the plasma that produces in the gaseous state to crystal column surface, and the window that plasma is left through photoresist with wafer generation physics or chemical reaction, thereby removes the surfacing that exposes to the open air.Dry etching is the main method of etched features under the submicron-scale.And in wet etching, liquid chemical reagent is removed the crystal column surface material with chemical mode.Wet etching can be used on the etching wafer some layer or with the residue that removes behind the dry etching.
Existing metal gate manufacture method probably can comprise; At first with reference to Figure 1A; Positive and negative at silicon substrate 1 forms the first oxide layer 2a and the second oxide layer 2b respectively, is then forming the first protective layer 3a on the first oxide layer 2a and on the second oxide layer 2b, is forming the second protective layer 3b; With reference to Figure 1B, on the first protective layer 3a, form patterned photoresist, be the mask etching first protective layer 3a, the first oxide layer 2a and silicon substrate 1 with the photoresist, form isolated groove; With reference to figure 1C, on the silicon substrate 1 and the first protective layer 3a, adopt chemical vapour deposition (CVD) to form the 3rd oxide layer 2c; With reference to figure 1D, use cmp planarization the 3rd oxide layer 2c then; With reference to figure 1E, following one technology is need first protective layer be removed, and existing protective layer etching is removed the wet etching method that only adopts; Promptly be etched in all directions (laterally, vertical) etching simultaneously because wet etching belongs to isotropism, and wafer is immersed in the chemical liquid; So when the etching first protective layer 3a; The second protective layer 3b and the second oxide layer 2b are etched away equally, and ion injects and forms well region, removes the first oxide layer 2a and forms gate oxide 2d; Continue with reference to figure 1F, on gate oxide, form metal level 4 and polysilicon layer 5; With reference to figure 1G, on polysilicon layer 5, forming the photoresist of patterning again, is mask etching polysilicon layer 5 and metal level 4 with the photoresist, forms metal gate.Before forming metal gate, the protective layer of deposit and oxide layer are all removed in the trench isolations manufacturing process, and wafer rear is the silicon substrate that exposes; After the metal gates etching forms; The side of metal gate exposes metallic atom, and these metallic atoms can diffuse to wafer rear and get into silicon substrate, cause metallic pollution; Cause device creepage to increase problems such as reliability reduction.In order to guarantee that silicon substrate 1 is not impregnated in impurity, must clean the part that is spread in the silicon substrate 1.Silicon substrate 1 attenuation and out-of-flatness cause occurring in the follow-up course of processing problem that mask aligner can't accurately be focused after cleaning.
Summary of the invention
When the technical problem that the present invention solves was to use wet etching to remove protective layer, the protective layer at the silicon substrate back side was removed simultaneously and causes that metallic atom diffuses into surface of silicon when the etching metal gate, influences the performance of metal gate.
A kind of manufacture method of metal gate; A kind of manufacture method of metal gate; The wafer that has formed silicon substrate at first is provided; Positive and negative at said silicon substrate forms first oxide layer and second oxide layer respectively, on said first oxide layer and second oxide layer, forms first protective layer and second protective layer respectively; Etching first protective layer, first oxide layer and silicon substrate; In silicon substrate deposit the 3rd oxide layer of said first protective layer and exposure, planarization the 3rd oxide layer to exposure first protective layer; Dry etching is removed part first protective layer; Wet etching is removed remaining first protective layer and part second protective layer; Ion injects and forms well region, and prerinse is removed first oxide layer and formed gate oxide; Form metal gate.
Preferably, first protective layer and second protective layer all adopt silicon nitride material.
Preferably, first oxide layer, second oxide layer and the 3rd oxide layer all adopt silica.
Preferably, said first protective layer and second protective layer adopt low-pressure chemical vapor phase deposition in boiler tube, to form, and the thickness of formation is 1000～2000 dusts.
Preferably, the mode of the cmp of said planarization the 3rd oxide layer employing.
Preferably, said formation metal gate comprises: on gate oxide, form metal level and polysilicon layer; Etch polysilicon layer and metal level form metal gate.
What preferably, said etch polysilicon layer and metal level adopted is the mode of dry etching.
Preferably, form and also to comprise that cleaning and removing removes the technology of second protective layer and second oxide layer after the metal gate.
Preferably, said prerinse is all adopted hydrofluoric acid clean with cleaning.Compared with prior art; The present invention has the following advantages: through being used of dry etching and wet etching protective layer; Avoided owing to use separately wet etching to cause metallic atom to diffuse into silicon substrate, in the time of can not causing prerinse in the silicon substrate silicon atom run off and the leakage current of the metal gate that causes etc. influences the problem generation of wafer quality.Silicon substrate has the covering of second protective layer when further guaranteeing prerinse, can not cause silicon substrate uneven because of the silicon substrate that cleaning causes, and influences the focusing for wafer of subsequent technique lithographic equipment.
Description of drawings
Figure 1A to 1G is existing metal gate manufacture method structural representation;
Fig. 2 is the flow chart of metal gate manufacture method of the present invention;
Fig. 3 A to 3J is the structural representation of metal gate manufacture method of the present invention.
Embodiment
The embodiment of the invention is used through using dry etching and wet etching dual mode; Protective layer on the etching wafer; The protective layer that prevents wafer silicon substrate below is etched away when only using the wet etching method simultaneously, because therefore metallic atom pollution meeting is directly polluted silicon substrate and is diffused in the silicon substrate, when the etching metal gate; Before getting into next step technology, need contaminated silicon substrate is cleaned; Otherwise can influence wafer quality, but the unevenness that the substrate that cleaned makes back side change makes not only wafer produce the problem that can't accurately focus in post-order process such as photoetching.
For making above-mentioned purpose of the present invention, characteristic and the advantage can be more obviously understandable, do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 2 is a making flow chart of the present invention, and Fig. 3 A to 3F makes sketch map for metal gate of the present invention.
With reference to accompanying drawing 2, step S200 provides the wafer that forms silicon substrate, forms first oxide layer and second oxide layer respectively at the positive and negative of said silicon substrate, on said first oxide layer and second oxide layer, forms first protective layer and second protective layer respectively; Step S201, etching first protective layer, first oxide layer and silicon substrate form isolated groove; Step S202 is in silicon substrate deposit the 3rd oxide layer of said first protective layer and exposure; Step S203, planarization the 3rd oxide layer to exposure first protective layer; Step S204, dry etching first protective layer is removed part first protective layer; Step S205, wet etching remove remaining first protective layer and part second protective layer; Step S206, ion inject and form well region, remove first oxide layer and are forming gate oxide; Step S207 forms metal level and polysilicon layer on gate oxide; Step S208, dry etching polysilicon layer and metal level form metal gate; Step S209, cleaning and removing is removed part second protective layer, guarantees the smooth of silicon substrate.
Step S200 provides the wafer that forms silicon substrate, forms first oxide layer and second oxide layer respectively at the positive and negative of said silicon substrate, on said first oxide layer and second oxide layer, forms first protective layer and second protective layer respectively.
Shown in Fig. 3 A; The wafer that has formed silicon substrate 301, the first oxide layer 302a and the second oxide layer 302b at first is provided; Then said wafer is formed the first protective layer 303a through low-pressure chemical vapor phase deposition (LPCVD) on the first oxide layer 302a, under the second oxide layer 302b, form the second protective layer 303b.The employing of the wherein said first protective layer 303a and the second protective layer 303b be silicon nitride material, thickness can be 1000～2000 dusts, is preferably 1150 dusts.Silicon nitride has higher hardness, can guarantee in the process of cmp, to prevent the wafer overmastication as grinding stop layer, can protect wafer to be polluted in process of production equally.And all oxide layers all adopt silica material among the present invention.
Step S201, etching first protective layer, first oxide layer and silicon substrate form isolated groove.
Shown in Fig. 3 B, on the first protective layer 303a, form one deck photoresist, through exposure, development, then etching is exposed silicon substrate 301 formation isolated grooves.
Step S202 is in silicon substrate deposit the 3rd oxide layer of said first protective layer and exposure.
Shown in Fig. 3 C, form the 3rd oxide layer 302c in wafer frontside through chemical vapor deposition.Because the first protective layer 303a is at the thickness uniformity that part is not etched and chemical vapor deposition deposits in unit are of active area, when forming the 3rd oxide layer 302c, the oxide layer of first protective layer 303a top partly forms convex shape.
Step S203, planarization the 3rd oxide layer to exposure first protective layer.
Like Fig. 3 D, through the three oxide layer 302c flattening surface of cmp with wafer.Because what the 303a of first protective layer adopted is the material that silicon nitride material has higher hardness, so silicon nitride plays the effect that delays grinding rate when cmp is flat to first protective layer 303a surface.After grinding completion, the thickness of the first protective layer 303a is 650 dusts, and the difference in height of the upper surface of the upper surface of the first protective layer 303a and the 3rd oxide layer 302c is at 200～300 dusts.
Step S204, dry etching first protective layer is removed part first protective layer.
Shown in Fig. 3 E, above the first protective layer 303a and the 3rd oxide layer 302c, cover one deck photoresist, remove the photoresist on the 3rd oxide layer 302c with the mode of exposure, development.Through dry etching, remove thickness 500 dusts of the first protective layer 303a, but still the silicon nitride that guarantees 150 dusts are arranged is on the first oxide layer 302a.
Step S205, wet etching remove remaining first protective layer and part second protective layer.
Shown in Fig. 3 F; Mode with wet etching is removed the remaining 150 dust thickness of the first protective layer 303a; Because wet etching belongs to isotropism and refers to that promptly (laterally with vertical direction) carried out etching with identical etch rate on all directions, so the second protective layer 303b is removed the thickness of 150 dusts simultaneously.After wet etching is accomplished, the thickness of said second protective layer 303b residue, 850 to 950 dusts.
Step S206, ion inject and form well region, remove first oxide layer and form gate oxide.
Shown in Fig. 3 G; After adopting well region ion implantation technology step to make that crystal column surface is decrystallized; And wafer is placed among the hydrofluoric acid HF cleaning and removing remove the first oxide layer 302a, and on crystal column surface, forming gate oxide 302d, it is 10～50 dusts that gate oxide 302d forms thickness.
Step S207 forms metal level and polysilicon layer on gate oxide.
Shown in Fig. 3 H, form layer of metal layer 304 and one deck polysilicon layer 305 through physical vapor deposition process (PVD) at gate oxide 302d, the metal gate that is used for post-order process is made.
Step S208, dry etching polysilicon layer and metal level form metal gate.
Shown in Fig. 3 I, cover one deck photoresist at polysilicon layer 305, through exposure, the side of development shows removes the part photoresist, through dry etching, forms metal gate.After etching; Come out in the metal gate side; It is in the said second protective layer 303b surface that metallic atom can be diffused into wafer rear, because the silicon nitride of the second protective layer 303b has the characteristic that hinders metal diffusing, so metallic atom can further not be diffused in the second oxide layer 302b.
Step S209 removes second protective layer and second oxide layer, guarantees the smooth of silicon substrate.
Shown in Fig. 3 J, use phosphoric acid to clean and also remove the second protective layer 303b, again with hydrofluoric acid clean and remove the second oxide layer 302b.Because metallic atom diffuses into the second protective layer 303b in a last step S208, thus need the said part second protective layer 303b be removed, optional, diffuse into whole second protective layer like metallic atom, then can remove all second protective layers.
In the above-mentioned execution mode of metal gate manufacture method of the present invention; Through two kinds of different etching mode etching protective layers; In etching metal gate process, keep second protective layer and cover second oxide layer and silicon substrate with less density with high density silicon nitride material; And in follow-up prewashed step; Removal has the whole and second oxide layer 302b of the said second protective layer 303b of greater density, thereby avoids because the independent wet etching that uses causes metallic atom to diffuse into silicon substrate silicon atom loss in the silicon substrate in the time of can not causing prerinse.
Further, silicon substrate has the covering of second protective layer during owing to prerinse, can not cause silicon substrate uneven because of the silicon substrate that cleaning causes, and influences the focusing for wafer of subsequent technique lithographic equipment.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1. the manufacture method of a metal gate; The wafer that has formed silicon substrate at first is provided; Positive and negative at said silicon substrate forms first oxide layer and second oxide layer respectively, on said first oxide layer and second oxide layer, forms first protective layer and second protective layer respectively;
Etching first protective layer, first oxide layer and silicon substrate;
In silicon substrate deposit the 3rd oxide layer of said first protective layer and exposure, planarization the 3rd oxide layer to exposure first protective layer;
Dry etching is removed part first protective layer;
Wet etching is removed remaining first protective layer and part second protective layer;
Ion injects and forms well region, and prerinse is removed first oxide layer and formed gate oxide;
Form metal gate.
2. metal gate manufacture method as claimed in claim 1 is characterized in that, first protective layer and second protective layer all adopt silicon nitride material.
3. metal gate manufacture method as claimed in claim 1 is characterized in that, first oxide layer, second oxide layer and the 3rd oxide layer all adopt silica.
4. metal gate manufacture method as claimed in claim 1 is characterized in that, said first protective layer and second protective layer adopt low-pressure chemical vapor phase deposition in boiler tube, to form, and the thickness of formation is 1000～2000 dusts.
5. metal gate manufacture method as claimed in claim 1 is characterized in that, the mode of the cmp that said planarization the 3rd oxide layer adopts.
6. metal gate manufacture method as claimed in claim 1 is characterized in that, said formation metal gate comprises: on gate oxide, form metal level and polysilicon layer;
Etch polysilicon layer and metal level form metal gate.
7. metal gate manufacture method as claimed in claim 6 is characterized in that, what said etch polysilicon layer and metal level adopted is the mode of dry etching.
8. metal gate manufacture method as claimed in claim 7 is characterized in that, forms also to comprise that cleaning and removing removes the technology of second protective layer and second oxide layer after the metal gate.
9. metal gate manufacture method as claimed in claim 8 is characterized in that, said prerinse is all adopted hydrofluoric acid clean with cleaning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101971030A CN102044421B (en) | 2009-10-13 | 2009-10-13 | Method for manufacturing metal gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101971030A CN102044421B (en) | 2009-10-13 | 2009-10-13 | Method for manufacturing metal gate |
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| CN102044421A CN102044421A (en) | 2011-05-04 |
| CN102044421B true CN102044421B (en) | 2012-05-23 |
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| CN2009101971030A Expired - Fee Related CN102044421B (en) | 2009-10-13 | 2009-10-13 | Method for manufacturing metal gate |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103137467A (en) * | 2011-11-24 | 2013-06-05 | 联华电子股份有限公司 | Semiconductor manufacturing process for removing oxide layer |
| CN102543713B (en) * | 2012-02-28 | 2014-05-28 | 上海华力微电子有限公司 | Method for etching oxide silicon grid compensating isolation region |
| CN106558486B (en) * | 2015-09-30 | 2019-12-10 | 无锡华润上华科技有限公司 | method for removing mask layer of semiconductor substrate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1181617A (en) * | 1996-10-24 | 1998-05-13 | 佳能株式会社 | Production of electronic device |
| CN1338115A (en) * | 1999-03-03 | 2002-02-27 | 株式会社日立制作所 | Semiconductor integrated circuit device and its production method |
| CN1518090A (en) * | 2003-01-23 | 2004-08-04 | ��ʿͨ��ʽ���� | Manufacturing method of semiconductor device |
| CN1549310A (en) * | 2003-05-16 | 2004-11-24 | 旺宏电子股份有限公司 | Method for removing silicon nitride layer |
| CN1862777A (en) * | 2005-05-09 | 2006-11-15 | 联华电子股份有限公司 | Trend insulation method |
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2009
- 2009-10-13 CN CN2009101971030A patent/CN102044421B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1181617A (en) * | 1996-10-24 | 1998-05-13 | 佳能株式会社 | Production of electronic device |
| CN1338115A (en) * | 1999-03-03 | 2002-02-27 | 株式会社日立制作所 | Semiconductor integrated circuit device and its production method |
| CN1518090A (en) * | 2003-01-23 | 2004-08-04 | ��ʿͨ��ʽ���� | Manufacturing method of semiconductor device |
| CN1549310A (en) * | 2003-05-16 | 2004-11-24 | 旺宏电子股份有限公司 | Method for removing silicon nitride layer |
| CN1862777A (en) * | 2005-05-09 | 2006-11-15 | 联华电子股份有限公司 | Trend insulation method |
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| CN102044421A (en) | 2011-05-04 |
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Granted publication date: 20120523 Termination date: 20191013 |