CN102034827B - Nonvolatile memory and arrangement thereof - Google Patents
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Abstract
The invention discloses a nonvolatile memory arrangement, which includes a semiconductor substrate, a plurality of first type doping wells, a plurality of second conductors, a plurality of first ion doped regions, a plurality of second ion doped regions, a plurality of work lines and a plurality of bit lines. The semiconductor substrate is provided with a plurality of isolation structures for isolating the semiconductor into a plurality of first transistor regions, a plurality of capacitor regions and a plurality of second transistor regions. Each capacitor area is arranged between the corresponding first transistor region and the second transistor region. The plurality of first type doping wells are respectively arranged in one of the corresponding capacitor. Each second ion doped region is arranged in a first type doping well between the adjacent first conductor and the second conductor, and each second ion doped region, together with a corresponding first capacitor component , forms a first capacitor and, together with the corresponding second conductor component, forms a second capacitor.
Description
Technical field
The present invention relates to a kind of semiconductor element layout structure, and particularly relate to a kind of layout of nonvolatile memory.
Background technology
Nonvolatile memory (Non-Volatile Memory, NVM) element has the characteristic that the data that deposit in element can not disappear because of the interruption of power supply supply, thereby becomes and be generally used to one of memory component of storage data at present.
According to the restriction of the read-write number of times of memory, nonvolatile memory can be divided into: repeatedly programmed memory (the multi-time programmable memory with the function of rewritable, MTP memory) and two kinds of the single programmed memories (one-time programmable memory, OTP memory) that the data of single write only can be provided.In addition, if distinguish from component structure, mainly can be divided into again: double level polysilicon (double-poly) nonvolatile memory and single level polysilicon (single-poly) nonvolatile memory.
Due to nonvolatile memory can with general complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process compatible, is therefore often used in in-line memory (embedded memory) field.But, in advanced logic process, use double level polysilicon nonvolatile memory high as complex process and the cost of in-line memory, element yield is not good yet.Therefore,, in advanced logic process, single-layer polysilicon non-volatile memory has some superiority and is regarded as the memory component quite with competitive advantage of future generation.
Fig. 1 is the repeatedly local schematic top plan view of programmed nonvolatile memory layout of known a kind of single level polysilicon.
Please refer to Fig. 1, in semiconductor base 100, be provided with P type well region 112 and N-type well region 114, and between these well regions, be provided with isolation structure 160.Known single level polysilicon repeatedly programmed nonvolatile memory has multiple memory cell 110, and each memory cell 110 is made up of with a capacitor 140 that is positioned at N-type well region 114 transistor 120 that is positioned at P type well region 112.Wherein, transistor 120 is using polysilicon layer g1 as grid, and in the P type well region 112 of polysilicon layer g1 (grid) both sides, is provided with two ion doped regions using respectively as source S and drain D.140, capacitor is in N-type well region 114, to be provided with ion doped region using the control grid as memory cell 110 (Control Gate) CG, and above N-type well region 114, is provided with polysilicon layer g2 using the electrode as capacitor 140.The grid of above-mentioned transistor 120 and the electrode of capacitor 140 form floating grid (Floating Gate) FG for electric connection, and floating grid FG is for being vertically installed in P type well region 112 and N-type well region 114 tops, and extension is arranged at part isolation structure 160 tops.
Multiple memory cell 110 in known nonvolatile memory are configured to arrayed, and take multiple transistors 120 of sequentially arranging on directions X and adjacent multiple capacitors 140 of sequentially arranging on directions X as repetitive.In addition, many word lines (Word Line) WL extends and arranges in parallel to each other in the Y direction along directions X, and each word line WL couples the control grid CG of the each capacitor 140 on directions X.Multiple bit lines (Bit Line) BL along Y-direction extend and above X upwards in parallel to each other arrange, and with word line WL vertical interlaced, each bit lines BL couples the drain D of the each transistor 120 in Y-direction.
As shown in Figure 1, the layout of known nonvolatile memory is that its layout designs is for utilizing a word line WL to control two bit lines BL take a capacitor 140 and two transistors 120 as minimum memory cell size.
But the development trend of memory component is towards high memory density and the sequencing speed (programming speed) of memory also wishes gradually to improve now.Therefore, how to reach above-mentioned target, will be one of problem very important in memory component development.
Summary of the invention
Object of the present invention is exactly that a kind of layout of nonvolatile memory is being provided, except can relatively reducing the leakage current producing by isolation structure corner, and improve outside the coupling effect of capacitor, also can improve the speed of the operation that stylizes of memory component, and promote component density.
The present invention proposes a kind of layout of nonvolatile memory, and this layout comprises semiconductor base, multiple the first type dopant well, multiple the first conductor, multiple the second conductor, multiple the first ion doped region, multiple the second ion doped region, many word lines and multiple bit lines.Wherein, in semiconductor base, there are many isolation structures, semiconductor base is separated into multiple first crystals area under control, multiple capacitor area and multiple transistor secondses district.And each capacitor area, between corresponding first crystal area under control and transistor seconds district, and is arranged with corresponding first crystal area under control and transistor seconds district between two adjacent capacitor areas.Multiple the first type dopant wells are disposed at respectively corresponding a little capacitor areas in one of them.
Hold above-mentionedly, multiple the first conductors are cross-placed on corresponding isolation structure, first crystal area under control and the first type dopant well top.Each first conductor comprises the first capacitance part and the first transistor portion, and the first capacitance part is positioned at the first corresponding type dopant well top, and the first transistor portion is positioned at corresponding top, first crystal area under control.Each first conductor has the first lateral margin respect to one another and the second lateral margin, and the first lateral margin is positioned at the isolation structure top of corresponding first crystal area under control one side, and the second lateral margin is positioned at the first corresponding type dopant well top.Multiple the second conductors are cross-placed on corresponding isolation structure, transistor seconds district and the first type dopant well top.Each second conductor comprises the second capacitance part and transistor seconds portion, and the second capacitance part is positioned at the first corresponding type dopant well top, and transistor seconds portion is positioned at corresponding top, transistor seconds district.Each second conductor has the 3rd lateral margin respect to one another and the 4th lateral margin, and the 3rd lateral margin is positioned at the isolation structure top of corresponding transistor seconds district one side, and the 4th lateral margin is positioned at the first corresponding type dopant well top and one of them is adjacent with the second lateral margin.
In addition, multiple the first ion doped regions are arranged at respectively in the first crystal area under control of the first conductor both sides and in the transistor seconds district of the second conductor both sides, and form multiple the first transistors with the first transistor portion of the first conductor respectively, and form multiple transistor secondses with the transistor seconds portion of the second conductor.Each second ion doped region is arranged in the first type dopant well between the first adjacent conductor and the second conductor, and each the second ion doped region forms one first capacitor and forms one second capacitor with the second corresponding capacitance part with the first corresponding capacitance part simultaneously.Many word line is arranged on semiconductor base, and each word line couples the second ion doped region.Multiple bit lines and word line are vertically arranged on semiconductor base, and the first ion doped region of each bit lines coupling.
In a preferred embodiment of the invention, above-mentioned semiconductor base is the substrate of Second-Type doped semiconductor, it is for example the substrate of P type doped semiconductor, and the first type dopant well is N-type dopant well, the first ion doped region and the second WeiNXing ion doped region, ion doped region.
In a preferred embodiment of the invention, the layout of above-mentioned nonvolatile memory also comprises multiple Second-Type dopant wells, it is sequentially arranged respectively and discontinuous being disposed in first crystal area under control and transistor seconds district, and the first ion doped region is arranged in Second-Type dopant well.Second-Type dopant well is for example P type dopant well, and the first type dopant well is N-type dopant well, the first ion doped region and the second WeiNXing ion doped region, ion doped region.
In a preferred embodiment of the invention, equal in length in the direction of vertical isolation structure of the first above-mentioned capacitance part and the second capacitance part.The width of each the first type dopant well in the direction of vertical isolation structure is greater than the twice of the length of the first capacitance part in the direction of vertical isolation structure.
In a preferred embodiment of the invention, equal in length in the direction of vertical isolation structure of the first transistor portion of above-mentioned each the first conductor and the first capacitance part.
In a preferred embodiment of the invention, the first transistor portion of above-mentioned each the first conductor is different from the length of the first capacitance part in the direction of vertical isolation structure.
In a preferred embodiment of the invention, equal in length in the direction of vertical isolation structure of the transistor seconds portion of above-mentioned each the second conductor and the second capacitance part.
In a preferred embodiment of the invention, the transistor seconds portion of above-mentioned each the second conductor is different from the length of the second capacitance part in the direction of vertical isolation structure.
Because conductor of the present invention (floating grid) does not extend through the first type dopant well, therefore compared with known element design, the negligible amounts of the isolation structure corner having between element (transistor AND gate capacitor) and isolation structure, and then can be reduced in the leakage current that isolation structure corner produces.In addition, between capacitance part of the present invention and the first type dopant well, the edge length (edge length) of lap increases relatively, therefore can make capacitor can there is higher coupling effect (couple efficiency), and it can reduce the required voltage of storage operation, and can lift elements usefulness.In addition, layout of the present invention can be controlled four bit lines BL with a word line WL, to improve the speed of operation that stylizes of memory component, and in unit are, may be configured with more memory cell, and it can promote component density.
For above and other object of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the repeatedly local schematic top plan view of programmed nonvolatile memory layout of known a kind of single level polysilicon.
Fig. 2 is the schematic top plan view of the non-volatile memory cells of embodiments of the invention.
Fig. 3 is the local schematic top plan view of the layout of the nonvolatile memory of embodiments of the invention.
Description of reference numerals
100,200,300: semiconductor base
110: memory cell
112:P type well region
114:N type well region
160: isolation structure
210,320,330,325,335: non-volatile memory cells
120,220: transistor
222,224,360: the first ion doped regions
140,230: capacitor
232: the second ion doped regions
240,340,390: conductor
242,244,342,344,392,394: conductor lateral margin
250,350: Second-Type dopant well
252,352,382: transistor area
260: the first type dopant wells
262,362: capacitor area
270,370: isolation structure
BL: bit line
C1, C2, C3, C ', C ", C " ', C " ": isolation structure corner
CG: control grid
D: drain electrode
FG: floating grid
G1, G ' 1: transistor portion
G2, G ' 2: capacitance part
G1, g2: polysilicon layer
L1, L2, L4: length
L3, L5: width
S: source electrode
WL: word line
Embodiment
Fig. 2 is the schematic top plan view of the non-volatile memory cells of embodiments of the invention.
Please refer to Fig. 2, non-volatile memory cells 210 of the present invention is made up of semiconductor base 200, conductor 240, many isolation structures 270, the first type dopant well 260, two the first ion doped regions 222,224 and the second ion doped region 232.
In semiconductor base 200, dispose many isolation structures 270 that are parallel to each other, it is for example fleet plough groove isolation structure (Shallow Trench Isolation, STI).Semiconductor base 200 is separated the transistor area 252 and capacitor area 262 for being parallel to each other by these isolation structures 270.The first type dopant well 260 is disposed in container area 262, and it is for example N-type dopant well.
In the present embodiment, semiconductor base 200 is for example unadulterated semiconductor base, and non-volatile memory cells 210 also includes Second-Type dopant well 250, and it is for example P type dopant well, is arranged in transistor area 252.Certainly, in another embodiment, also can directly Second-Type admixture be mixed in semiconductor base 200, for example, to become the substrate of Second-Type doped semiconductor, P type doped semiconductor substrate.
The first ion doped region 222,224 of non-volatile memory cells 210 is for example N-type ion doped region, and it is arranged at respectively in the Second-Type dopant well 250 of transistor area 252 of the G1 of the transistor portion both sides of conductor 240.The first ion doped region 222,224 can with the G1 of the transistor portion transistor formed 220 of conductor 240, and respectively as source S and the drain D of transistor 220.
In addition, the second ion doped region 232 is for example N-type ion doped region, and it is arranged in the first type dopant well 260 of conductor 240 1 sides.The second ion doped region 232 forms capacitor 230 with the capacitance part G2 of conductor 240, and the second ion doped region 232 is the control grids (Control Gate, CG) as non-volatile memory cells 210.
Particularly, as shown in Figure 2, the second lateral margin 244 of conductor 240 (floating grid) is positioned at the first type dopant well 260 tops, that is to say that floating grid does not extend through the first type dopant well 260, so in non-volatile memory cells 210, conductor 240 only covers 3 isolation structure corners (corner) C1, C2, C3.As shown in Figure 1, the floating grid FG of known non-volatile memory cells 110 covers 4 isolation structure corner C ', C ", C " ', C " ".Therefore,, with in comparison known, non-volatile memory cells 210 can be reduced in the leakage current that isolation structure corner produces relatively, to improve element efficiency.
In addition, the length of the G1 of transistor portion of conductor 240 in the direction of vertical isolation structure 270 is L1, and the length of the capacitance part G2 of conductor 240 in the direction of vertical isolation structure 270 is L2.In an embodiment of the present invention, the length L 1 of the G1 of transistor portion and the length L 2 of capacitance part G2 equate.In another embodiment, the length L 1 of the G1 of transistor portion is different with the length L 2 of capacitance part G2.
In addition, in an embodiment, the width of the first type dopant well 260 in the direction of vertical isolation structure 270 is L3, and the width L3 of the first type dopant well 260 can be for example the length L 2 that is greater than the capacitance part G2 of two times.
Hold above-mentioned, due to the element design compared to known (as shown in Figure 1), between the capacitance part G2 of the capacitor 230 of non-volatile memory cells 210 and the first type dopant well 260, the edge length (edge length) of lap increases relatively, therefore capacitor 230 can have higher coupling effect (couple efficiency), and it can reduce the required voltage of storage operation, and then can lift elements usefulness.
Next, the layout of nonvolatile memory of the present invention is described with Fig. 3.
Please refer to Fig. 3, the local schematic top plan view of the layout of its nonvolatile memory that is embodiments of the invention.
In semiconductor base 300, have isolation structure 370, semiconductor base 300 is separated the multiple first crystals area under control 352 for being arranged in parallel, multiple capacitor area 362 and multiple transistor secondses district 382 by it.Wherein, each capacitor area 362 is between corresponding first crystal area under control 352 and transistor seconds district 382.And, between two adjacent capacitor areas 362, be arranged with corresponding first crystal area under control 352 and transistor seconds district 382.That is be that layout of the present invention is the design repeated arrangement with transistor area-capacitor area-transistor area.
In the present embodiment, semiconductor base 300 is for example unadulterated semiconductor base, and also can be respectively arranged with Second-Type dopant well 350 in transistor area 352 and transistor area 382, and it is for example P type dopant well.Certainly, in another embodiment, also can directly Second-Type admixture be mixed in semiconductor base 300, for example, to become the substrate of Second-Type doped semiconductor, P type doped semiconductor substrate.
On the other hand, in each capacitor area 362, can be provided with the first type dopant well 360.
Multiple the first conductors 340 are for bridging in parallel with each other above isolation structure 370, first crystal area under control 352 and the first type dopant well 360.The first conductor 340 includes the first capacitance part G2 and the G1 of the first transistor portion, and wherein the first capacitance part G2 position is above the first type dopant well 360 of correspondence, and the G1 of the first transistor portion position is above corresponding first crystal area under control 352.The first conductor 340 also has the first lateral margin 342 respect to one another and the second lateral margin 344, and the first lateral margin 342 is positioned at isolation structure 370 tops of corresponding first crystal area under control 352 1 sides, and the second 344 of lateral margins are to be positioned at the first corresponding type dopant well 360 tops.
Multiple the second conductors 390 are for bridging in parallel with each other above isolation structure 370, transistor seconds district 382 and the first type dopant well 360.The second conductor 390 includes the second capacitance part G ' 2 and the G ' of transistor seconds portion 1, and wherein 2 of the second capacitance part G ' are above the first type dopant well 360 of correspondence, and 1 of the G ' of transistor seconds portion is above corresponding transistor seconds district 382.The second conductor 390 also has the 3rd lateral margin 392 respect to one another and the 4th lateral margin 394, and the 3rd lateral margin 392 is positioned at isolation structure 370 tops of corresponding transistor seconds district 382 1 sides, the 4th 394 of lateral margins are to be positioned at the first corresponding type dopant well 360 tops and adjacent with the second lateral margin 344.
More specifically, the configuration of the first conductor 340 and the second conductor 390 is all to work by isolation structure 370 tops the first type dopant well 360 tops that extend to part.The material of the first conductor 340 and the second conductor 390 is conductor material, and it is for example doped polycrystalline silicon.And the first conductor 340 and the second conductor 390 are the floating grids as nonvolatile memory.
Multiple the first ion doped regions and multiple second ion doped region of layout of the present invention are for example N-type ion doped regions.The first ion doped region is arranged at respectively in the first crystal area under control 352 of the G1 of transistor portion both sides of the first conductor 340 and in the transistor seconds district 382 of the G ' of transistor portion 1 both sides of the second conductor 390.Wherein, the first above-mentioned ion doped region can be respectively as source S and the drain D of element, and it can form the first transistor 320 with the G1 of the first transistor portion of the first conductor 340, and form multiple transistor secondses 325 with the G ' of transistor seconds portion 1 of the second conductor 390.
In addition, the second ion doped region is arranged in the first type dopant well 360 between adjacent the first conductor 340 and the second conductor 390.The second ion doped region forms the first capacitor 330 with the first capacitance part G2 of corresponding the first conductor 340, and form the second capacitor 335 with the second capacitance part G ' 2 of corresponding the second conductor 390, and the second ion doped region is the control grid CG as nonvolatile memory simultaneously.
In addition, the layout of nonvolatile memory of the present invention also comprises many word line WL and multiple bit lines BL.Wherein, word line WL is for being parallel on semiconductor base 300, and each word line WL couples the second ion doped region (namely controlling grid CG).Bit line BL is and the mutual vertical interlaced of word line WL, and each bit lines BL couples each transistorized drain D.
In addition, the length L 1 of the G1 of the first transistor portion can equate with the length L of the first capacitance part G2 2, or unequal.The length L 3 of the G ' of transistor seconds portion 1 equates with the length L 4 of the second capacitance part G ' 2, or unequal.In an embodiment, the length L 2 of the first capacitance part G2 and the length L 4 of the second capacitance part G ' 2 equate.
The width of the first type dopant well 360 in the direction of vertical isolation structure 370 is L5, and in the time that the length L 2 of the first capacitance part G2 and the length L 4 of the second capacitance part G ' 2 equate, the width L5 of the first type dopant well 360 is for example the length L 2 that is greater than the first capacitance part G2 of two times.
Referring again to Fig. 3, the first transistor 320 and the first capacitor 330 can form a non-volatile memory cells, transistor seconds 325 and the second capacitor 335 can form another non-volatile memory cells, and in layout of the present invention, thering are multiple non-volatile memory cells, it is configured to arrayed.And in layout of the present invention, non-volatile memory cells is mirror configuration, therefore may be configured with more memory cell in unit are, and then can relatively promote component density (device density).
As shown in Figure 3, layout of the present invention is the design repeated arrangement with transistor area-capacitor area-transistor area, and adjacent two transistor area 352 dispose two the first conductors 340 and two the second conductors 390 with capacitive region 362 tops therebetween, that is are to dispose 4 non-volatile memory cells.Therefore, layout of the present invention can utilize a word line WL to control four bit lines BL.
Hold above-mentionedly, the memory cell 110 shown in Fig. 1 is to control two bit lines BL with a word line WL, and layout of the present invention can be controlled four bit lines BL by a word line WL.Compared with known element design, layout of the present invention can improve the speed of the operation that stylizes of memory component.
It should be noted, Fig. 3 only shows the schematic diagram of section layout, and it is only provided as an example.Layout of the present invention can have four or memory cell more than four.For instance, some layout will comprise 8,16,32,64 or multiple memory cell more.Discussion is herein not limited to any given number of the memory cell in layout.
In sum, the layout of non-volatile memory cells of the present invention and nonvolatile memory at least has the following advantages:
1. compared to the prior art, the quantity of the isolation structure corner in memory cell of the present invention comparatively reduces, thereby can relatively be reduced in the leakage current that isolation structure corner produces, to improve element efficiency.
2. compared to known element design, capacitor of the present invention can have higher coupling effect, and it can reduce the required voltage of storage operation, and then can lift elements usefulness.
3. layout of the present invention can be controlled four bit lines BL with a word line WL, therefore can improve the speed of the operation that stylizes of memory component.
4. in the unit are of layout of the present invention, may be configured with more memory cell, and then promote component density.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; any persons skilled in the art; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when defining and be as the criterion depending on appended claim.
Claims (11)
1. a layout for nonvolatile memory, comprising:
Semiconductor base, in this semiconductor base, there are many isolation structures, this semiconductor base is separated into multiple first crystals area under control, multiple capacitor area and multiple transistor secondses district, wherein respectively this capacitor area, between this first crystal area under control and this transistor seconds district of correspondence, and is arranged with corresponding this first crystal area under control and this transistor seconds district between two adjacent described multiple capacitor areas;
Multiple the first type dopant wells, are disposed at respectively corresponding described multiple capacitor areas in one of them;
Multiple the first conductors, be cross-placed on corresponding described multiple isolation structures, this first crystal area under control and this first type dopant well top, respectively this first conductor comprises the first capacitance part and the first transistor portion and has the first lateral margin respect to one another and the second lateral margin, wherein respectively this first capacitance part is positioned at this corresponding the first type dopant well top, respectively this first transistor portion is positioned at this corresponding top, first crystal area under control, and respectively this first lateral margin is positioned at this isolation structure top of this corresponding first crystal area under control one side, respectively this second lateral margin is positioned at this corresponding the first type dopant well top,
Multiple the second conductors, be cross-placed on corresponding described multiple isolation structures, this transistor seconds district and this first type dopant well top, respectively this second conductor comprises the second capacitance part and transistor seconds portion and has the 3rd lateral margin respect to one another and the 4th lateral margin, wherein respectively this second capacitance part is positioned at this corresponding the first type dopant well top, respectively this transistor seconds portion is positioned at this corresponding top, transistor seconds district, and respectively the 3rd lateral margin is positioned at this isolation structure top of this corresponding transistor seconds district one side, respectively the 4th lateral margin is positioned at this corresponding the first type dopant well top and one of them is adjacent with described multiple the second lateral margins,
Multiple the first ion doped regions, be arranged at respectively in described multiple first crystals area under control of described multiple the first conductor both sides and in described multiple transistor secondses district of described multiple the second conductor both sides, and form multiple the first transistors with the described multiple the first transistor portion of described multiple the first conductors respectively, and form multiple transistor secondses with the described multiple transistor seconds portion of described multiple the second conductors;
Multiple the second ion doped regions, respectively this second ion doped region is arranged in this first type dopant well between adjacent described multiple the first conductors and described multiple the second conductor, and respectively this second ion doped region forms one first capacitor and forms one second capacitor with the second corresponding capacitance part with the first corresponding capacitance part simultaneously;
Many word lines, are arranged on this semiconductor base, and each word line couples described multiple the second ion doped region; And
Multiple bit lines, is vertically arranged on this semiconductor base with described many word lines, and each bit lines is corresponding and be coupled to the drain electrode of the one of described multiple transistor seconds and described multiple the first transistor.
2. the layout of nonvolatile memory as claimed in claim 1, wherein this semiconductor base is the substrate of Second-Type doped semiconductor.
3. the layout of nonvolatile memory as claimed in claim 2, wherein said multiple the first type dopant well is N-type dopant well, described multiple the first ion doped region and described multiple the second WeiNXing ion doped region, ion doped region, this semiconductor base is the substrate of P type doped semiconductor.
4. the layout of nonvolatile memory as claimed in claim 1, also comprise multiple Second-Type dopant wells, sequentially arrange respectively and discontinuous being disposed in described multiple first crystals area under control and described multiple transistor secondses district, and described multiple the first ion doped region is arranged in described multiple Second-Type dopant well.
5. the layout of nonvolatile memory as claimed in claim 4, wherein said multiple the first type dopant well is N-type dopant well, described multiple the first ion doped region and this WeiNXing ion doped region, the second ion doped region, described multiple Second-Type dopant wells are P type dopant well.
6. the layout of nonvolatile memory as claimed in claim 1, wherein said multiple the first capacitance part are equal in length in the direction of vertical described multiple isolation structures with described multiple the second capacitance part.
7. the layout of nonvolatile memory as claimed in claim 6, wherein respectively the width of this first type dopant well in the direction of vertical described multiple isolation structures is greater than the twice of the length of described multiple the first capacitance part in the direction of vertical described multiple isolation structures.
8. the layout of nonvolatile memory as claimed in claim 1, wherein respectively this first transistor portion of this first conductor with this first capacitance part equal in length in the direction of vertical described multiple isolation structures.
9. the layout of nonvolatile memory as claimed in claim 1, wherein respectively this first transistor portion of this first conductor is different from the length of this first capacitance part in the direction of vertical described multiple isolation structures.
10. the layout of nonvolatile memory as claimed in claim 1, wherein respectively this transistor seconds portion of this second conductor with this second capacitance part equal in length in the direction of vertical described multiple isolation structures.
The layout of 11. nonvolatile memories as claimed in claim 1, wherein respectively this transistor seconds portion of this second conductor is different from the length of this second capacitance part in the direction of vertical described multiple isolation structures.
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