CN102034807B - Method and device for protecting grid electrode - Google Patents
Method and device for protecting grid electrode Download PDFInfo
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- CN102034807B CN102034807B CN 200910196546 CN200910196546A CN102034807B CN 102034807 B CN102034807 B CN 102034807B CN 200910196546 CN200910196546 CN 200910196546 CN 200910196546 A CN200910196546 A CN 200910196546A CN 102034807 B CN102034807 B CN 102034807B
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 149
- 239000002184 metal Substances 0.000 claims abstract description 149
- 230000005669 field effect Effects 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 101100273567 Arabidopsis thaliana CYCL1-1 gene Proteins 0.000 description 51
- 238000005530 etching Methods 0.000 description 19
- 238000005137 deposition process Methods 0.000 description 18
- 230000002159 abnormal effect Effects 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000000227 grinding Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract
The invention discloses a device for protecting a grid electrode, comprising a field effect transistor MOS (Metal Oxide Semiconductor), a first diode, a second diode, first metal wires, a first bonding pad and a second bonding pad, wherein when the device is in an initial state, a grid electrode of the MOS is respectively connected to a first N pole of the first diode and a second P pole of the second diode through the first metal wires; a first P pole of the first diode is grounded; a second N pole of the second diode is grounded; and when the device is in an ending state, the first bonding pad is connected with the grid electrode of the MOS, the second bonding pad is simultaneously connected with the first N pole of the first diode and the second P pole of the second diode, voltage is applied between the first bonding pad and the second bonding pad and the metal wire connected with the MOS and the first diode in the first metal wires is fused. Meanwhile, the invention also discloses a method for protecting the grid electrode. By adopting the method and device, the damage of the antenna effect on the grid electrode can be avoided.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a gate protection method and apparatus.
Background
With the wide application of electronic devices, semiconductor manufacturing processes have been developed rapidly, in the semiconductor manufacturing process, when a metal layer or a dielectric layer is etched, a plasma etching process is involved many times, and under normal conditions, the plasma is electrically neutral, however, in the etching process, abnormal discharge of the plasma may generate free charges, and a large amount of free charges are gathered together to generate current. When a dielectric layer or a metal layer above a field effect transistor (MOS) is etched, current generated by abnormal plasma discharge flows to a grid along a metal interconnection line above the grid to damage the grid, so that the reliability and the service life of the MOS and even the whole chip are seriously reduced, wherein the metal interconnection line is a metal connection passage formed by a metal line formed after the metal layer is etched and metal filled in a through hole of the dielectric layer. The phenomenon that the current generated by the abnormal discharge of the plasma damages the grid is called antenna effect, and is also called plasma-induced grid damage (PID).
In order to clearly illustrate the gate protection device in the related art, the principle of the gate protection device in the related art will be described first.
Fig. 1 is a schematic diagram of a gate protection device in the prior art, and as shown in fig. 1, an N-pole of a first diode 11 is connected to a gate of a MOS12, the N-pole of the first diode 11 is simultaneously connected to a first pad 13, a P-pole of the first diode is grounded, and the gate of the MOS12 is further connected to the first pad 13. The straight line in the figure is a metal interconnection line, when a metal line is formed by etching a metal layer or a via hole is formed by etching a dielectric layer, the free charges generated by the abnormal plasma discharge are guided to the ground along the metal interconnection line and the first diode 11, so that the free charges generated by the abnormal plasma discharge are not accumulated as a current to damage the gate of the MOS12, that is, the first diode 11 corresponds to a protection device of the MOS12, the gate of the MOS12 is connected to the first pad 13, and the first pad 13 is finally formed in the device and is used for supplying an operating voltage to the MOS12 through the first pad 13.
Fig. 2 is a cross-sectional structural view of an embodiment of a gate protection device in the prior art, as shown in fig. 2, the device includes: the MOS transistor comprises a MOS12, a first diode 11, a first metal wire 301 and a first bonding pad 13, wherein a grid electrode 105 of the MOS12 is connected to a first N pole 107 of the first diode 11 through the first metal wire 301, a first P pole 101 of the first diode 11 is grounded (not shown), and the first bonding pad 13 is connected with the grid electrode 105 of the MOS12 and used for providing an operating voltage for the grid electrode 105 of the MOS 12.
Referring to fig. 2, a method for forming a gate protection device in the prior art is described, as shown in fig. 2, the method for forming a gate protection device in the prior art includes the following steps:
step one, providing a substrate 100, and forming a MOS12 by using a deposition process, an etching process, and an ion implantation process, wherein the MOS12 includes: a drain electrode 102, a source electrode 103, a gate oxide layer 104, a gate electrode 105 and a side wall layer 106, wherein the gate oxide layer 104 below the gate electrode 105 and the gate electrode 105 on the surface of the substrate 100 is generally called a gate structure; the first diode 11 is formed by an ion implantation process, wherein the first diode 11 includes a first N-electrode 107 and a first P-electrode 101, and the first P-electrode 101 of the first diode is grounded (not shown).
Step two, depositing a first dielectric layer 201 on the surface of the substrate 100, forming a first via 202 and a second via 203 for metal interconnection subsequently on the gate 105 of the MOS12 and the N-pole 107 of the first diode 11 by using an etching process, filling metal in the first via 202 and the second via 203 by using a deposition process, wherein the filled metal may be copper or tungsten, and finally grinding the metal in the first via 202 and the second via 203 to the surface of the first dielectric layer 201 by using a Chemical Mechanical Polishing (CMP) process.
And thirdly, forming a first metal layer on the first dielectric layer 201 by adopting a deposition process, forming a groove on the first metal layer by adopting an etching process, and forming a first metal line 301 by adopting unetched metal, wherein the MOS12 and the first diode 11 are connected by the first metal line 301, that is, the MOS12 and the first diode 11 are interconnected at the first metal layer.
Step four, forming a second dielectric layer 401 by using a deposition process, forming a third through hole 402 and a fourth through hole 403 in the second dielectric layer 401 above the MOS12 and the first diode 11 by using an etching process, filling metal in the third through hole 402 and the fourth through hole 403 by using the deposition process, wherein the filled metal can be copper or tungsten, and finally grinding the metal in the third through hole 402 and the fourth through hole 403 to the surface of the second dielectric layer 401 by using a CMP process.
And step five, forming a second metal layer on the surface of the second dielectric layer 401 by adopting a deposition process, forming a groove on the second metal layer by adopting an etching process, and forming a second metal line 501 by adopting unetched metal, wherein the MOS12 and the first diode 11 are not interconnected with each other on the second metal layer of the second metal line 501.
Step six, forming a third dielectric layer 601 by using a deposition process, forming a fifth through hole 602 in the third dielectric layer 601 above the MOS12 by using an etching process, filling metal, which may be copper or tungsten, in the fifth through hole 602 by using the deposition process, and finally grinding the metal in the fifth through hole 602 to the surface of the third dielectric layer 601 by using a CMP process.
Step seven, depositing metal aluminum on the surface of the third dielectric layer 601 by using a deposition process, and forming a first bonding pad 13 on the surface of the third dielectric layer 601 above the MOS12 by using an etching process, wherein the first bonding pad 13 is above the fifth via 602 and forms a metal interconnection with the metal in the fifth via 602.
As shown by arrows in fig. 2, when etching a metal layer or a dielectric layer over the MOS12 and the first diode 11, if the plasma abnormal discharge generates charges, the charges may flow to the ground in the direction of the dotted line. Furthermore, the first pad 13 is formed last in the apparatus, when the first pad 13 is formed, an operating voltage can be supplied to the MOS12 through the first pad 13 to drive the MOS12 to operate normally, and since the operating voltage is a positive voltage, when the MOS12 operates, the first diode 11 is in a cut-off state, and the first diode 11 has no influence on the normal operation of the MOS 12.
In addition, the present embodiment is described by taking a semiconductor structure including two metal layers as an example, and in practical applications, the number of metal layers included in the semiconductor structure is determined according to needs, but generally, the number of metal layers is much larger than two.
This flow ends by this point.
It can be seen that, in the prior art, since the N-pole of the first diode 11 is connected to the first pad 13 and the gate 105 of the MOS12, respectively, and the P-pole of the first diode 11 is grounded, when the plasma discharges abnormally, a free positive charge and a free negative charge are generated, the negative charge can be guided to the ground through the first diode 11, however, the positive charge cannot be guided to the ground through the first diode 11, so that a large amount of positive charges are gathered together and a current is generated to damage the gate 105 of the MOS12, and damage to the gate 105 due to the antenna effect cannot be avoided.
Disclosure of Invention
In view of this, the present invention provides a gate protection method and apparatus, which can avoid the damage of the antenna effect to the gate.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a gate protection device, the device comprising: the device comprises a field effect transistor MOS, a first diode, a second diode, a first metal wire, a first bonding pad and a second bonding pad; wherein,
in an initial state, the grid electrode of the MOS is respectively connected to a first N electrode of the first diode and a second P electrode of the second diode through a first metal wire, the first P electrode of the first diode is grounded, and the second N electrode of the second diode is grounded;
in the termination state, the first bonding pad is connected with the grid electrode of the MOS, the second bonding pad is simultaneously connected with the first N electrode of the first diode and the second P electrode of the second diode, voltage is applied between the first bonding pad and the second bonding pad, and the metal wire connecting the MOS and the first diode in the first metal wire is fused.
The current density on the first metal line is greater than 10000000 amps per square centimeter when in the termination state.
The width of a metal wire connecting the MOS and the first diode in the first metal wire is more than or equal to 0.09 and less than or equal to 0.2 microns.
A method of gate protection, the method comprising:
in an initial state, respectively connecting the grid of the MOS to a first N pole of the first diode and a second P pole of the second diode through a first metal wire, grounding the first P pole of the first diode, and grounding the second N pole of the second diode;
in the termination state, a first pad is connected to a gate of the MOS, a second pad is simultaneously connected to a first N-pole of the first diode and a second P-pole of the second diode, and a voltage is applied between the first pad and the second pad, so that a metal line connecting the MOS and the first diode in the first metal line is blown.
The current density on the first metal line is greater than 10000000 amps per square centimeter when in the termination state.
The width of a metal wire connecting the MOS and the first diode in the first metal wire is more than or equal to 0.09 and less than or equal to 0.2 microns.
According to the technical scheme, in an initial state, the grid electrode of the MOS is respectively connected to the first N pole of the first diode and the second P pole of the second diode through the first metal wire, the first P pole of the first diode is grounded, and the second N pole of the second diode is grounded; in a termination state, the first pad is connected with the grid electrode of the MOS, the second pad is simultaneously connected with the first N pole of the first diode and the second P pole of the second diode, and voltage is applied between the first pad and the second pad, so that the metal wire connected with the MOS and the first diode in the first metal wire is fused, positive charges generated by plasma abnormal discharge can be guided to the ground from the second diode, negative charges generated by plasma abnormal discharge can be guided to the ground from the first diode, and current generated by plasma abnormal discharge can be prevented from flowing to the grid electrode along a metal interconnection line above the grid electrode of the MOS, and the grid electrode is prevented from being damaged by an antenna effect.
Drawings
Fig. 1 is a schematic diagram of a gate protection device in the prior art.
Fig. 2 is a cross-sectional structural view of an embodiment of a gate protection device in the prior art.
Fig. 3 is a schematic diagram of a gate protection device provided in the present invention.
Fig. 4 is a cross-sectional structural diagram of an embodiment of a gate protection device provided in the present invention.
Fig. 5 is a flowchart of an embodiment of a gate protection method provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples.
In order to clearly illustrate the gate protection device provided by the present invention, the principle of the gate protection device provided by the present invention will be described first.
Fig. 3 is a schematic diagram of the gate protection device provided by the present invention, as shown in fig. 3, when in an initial state, the P-pole of the first diode 11 is grounded, the N-pole of the second diode 14 is grounded, the N-pole of the first diode 11 is connected to the P-pole of the second diode 14, the N-pole of the first diode 11 and the P-pole of the second diode 14 are simultaneously connected to the second pad 16, the N-pole of the first diode 11 and the P-pole of the second diode 14 are also simultaneously connected to the first pad 13 through the fuse 15, and the N-pole of the first diode 11 and the P-pole of the second diode 14 are also simultaneously connected to the gate of the MOS12 through the fuse 15; when in the terminated state, a voltage is applied between the first pad 13 and the second pad 16, causing the fuse 15 to blow.
The initial state refers to the forming stage of the metal interconnection line, the straight line in the figure is the metal interconnection line, and the metal interconnection line is a metal connecting passage formed by a metal line formed after the metal layer is etched and metal filled in the through hole of the dielectric layer; the termination state refers to a stage of forming the first pad 13 and the second pad 16 after the metal interconnection line is formed.
Fig. 4 is a cross-sectional structural view of an embodiment of a gate protection device provided in the present invention, as shown in fig. 4, the device includes: a MOS12, a first diode 11, a second diode 14, a first metal line 301, a first pad 13, and a second pad 16, wherein, when in an initial state, a gate 105 of the MOS12 is connected to a first N-pole 107 of the first diode 11 and a second P-pole 109 of the second diode 14 through the first metal line 301, respectively, and the first P-pole 101 of the first diode 11 is grounded, and the second N-pole 110 of the second diode 14 is grounded; when in the termination state, the first pad 13 is connected to the gate 105 of the MOS12, the second pad 16 is simultaneously connected to the first N-pole 107 of the first diode 11 and the second P-pole 109 of the second diode 14, and a voltage is applied between the first pad 13 and the second pad 16 to blow out a metal wire connecting the MOS12 and the first diode 11 in the first metal wire 301.
The normal width c of the metal line is greater than 5 micrometers, whereas in the present invention, when in the termination state, in order to cause the first metal line 301 to be blown under the premise of a large voltage, the width of the metal line of length b in the first metal line 301 connecting the MOS12 and the first diode 11 is set to a, where b is 10 micrometers to 20 micrometers, and a ranges from 0.09 to 0.2 micrometers. It should be noted that the metal line with the length b in the first metal line 301 connecting the MOS12 and the first diode 11 corresponds to the fuse 15 shown in fig. 3, and the two are identical in nature, and in practical applications, the fuse 15 is a thin metal line.
In practical applications, if the material of the first metal line 301 is different, the resistance of the first metal line 301 is different, and therefore, the specific value of the voltage applied between the first pad 13 and the second pad 16 is determined according to the specific situation, and as long as the current density J flowing through the first metal line 301 is larger than 10000000 amperes per square centimeter, the metal line connecting the MOS12 and the first diode 11 will be blown.
In order to describe the forming method of the gate protection device provided by the present invention in detail, the forming method of the gate protection device of the present invention is described below with reference to fig. 4.
The forming method of the gate protection device in the prior art comprises the following steps:
step one, providing a substrate 100, and forming a MOS12 by using a deposition process, an etching process, and an ion implantation process, wherein the MOS12 includes: a drain electrode 102, a source electrode 103, a gate oxide layer 104, a gate electrode 105 and a side wall layer 106, wherein the gate oxide layer 104 below the gate electrode 105 and the gate electrode 105 on the surface of the substrate 100 is generally called a gate structure; forming a first diode 11 by using an ion implantation process, wherein the first diode 11 includes a first N-electrode 107 and a first P-electrode 101, and the first P-electrode 101 of the first diode 11 is grounded (not shown); forming a second diode 14 by using an ion implantation process, wherein the second diode 14 includes a second P pole 109 and a second N pole 110, and the second N pole 110 is grounded (not shown); there are several shallow trench isolation regions 108 between the MOS12 and the first diode 11, and there are also shallow trench isolation regions 108 between the first diode 11 and the second diode 14.
Step two, depositing a first dielectric layer 201 on the surface of the substrate 100, forming a first through hole 202, a second through hole 203 and a sixth through hole 204 for subsequent metal interconnection on the gate 105, the first N-pole 107 and the second P-pole 109 respectively by using an etching process, filling metal in the first through hole 202, the second through hole 203 and the sixth through hole 204 by using a deposition process, wherein the filled metal can be copper or tungsten, and finally grinding the metal in the first through hole 202, the second through hole 203 and the sixth through hole 204 to the surface of the first dielectric layer 201 by using a CMP process.
And thirdly, forming a first metal layer on the first dielectric layer 201 by adopting a deposition process, forming a groove on the first metal layer by adopting an etching process, and forming a first metal wire 301 by adopting the unetched metal, wherein the MOS12, the first diode 11 and the second diode 14 are interconnected by the first metal wire 301.
Step four, a deposition process is adopted to form a second dielectric layer 401, an etching process is adopted to form a third through hole 402, a fourth through hole 403 and a seventh through hole 404 on the second dielectric layer 401 above the MOS12, the first diode 11 and the second diode 14 respectively, a deposition process is adopted to fill metal in the third through hole 402, the fourth through hole 403 and the seventh through hole 404, the filled metal can be copper or tungsten, and finally, a CMP process is adopted to grind the metal in the third through hole 402, the fourth through hole 403 and the seventh through hole 404 to the surface of the second dielectric layer 401.
Step five, a second metal layer is formed on the surface of the second dielectric layer 401 by using a deposition process, a trench is formed on the second metal layer by using an etching process, and unetched metal forms the second metal line 501, wherein the second metal line 501 above the MOS12 is not connected with the second metal line 501 above the first diode 11, that is, the MOS12 and the first diode 11 are not interconnected in the second metal layer, and the first diode 11 and the second diode 14 are connected by the second metal line 501, that is, the first diode 11 and the second diode 14 are interconnected in the second metal layer.
Step six, forming a third dielectric layer 601 by using a deposition process, forming a fifth via 602 in the third dielectric layer 601 on the MOS12 by using an etching process, forming an eighth via 603 on the second metal line 501 for interconnecting the first diode 11 and the second diode 14 by using the etching process, filling metal, which may be copper or tungsten, in the fifth via 602 and the eighth via 603 by using the deposition process, and finally grinding the metal in the fifth via 602 and the eighth via 603 to the surface of the third dielectric layer 601 by using a CMP process.
Step seven, depositing metal aluminum on the surface of the third dielectric layer 601 by using a deposition process, and forming a first bonding pad 13 and a second bonding pad 16 by using an etching process, wherein the first bonding pad 13 is above the fifth via 602 and can form a metal interconnection with the metal in the fifth via 602, and the second bonding pad 16 is above the eighth via 603 and can form a metal interconnection with the metal in the eighth via 603. .
When in the initial state, as shown by the arrow in fig. 2, the positive charges generated by the abnormal plasma discharge can be guided to the ground from the second diode 14, and the negative charges generated by the abnormal plasma discharge can be guided to the ground from the first diode 11, so that the current generated by the abnormal plasma discharge can be prevented from flowing to the gate 105 along the metal interconnection line above the gate 105 of the MOS12 to damage the gate 105; when a voltage is applied between the first pad 13 and the second pad 16 in the termination state, since the portion of the first metal line 301 connecting the MOS12 and the first diode 11 is relatively thin, the first metal line 301 connecting the MOS12 and the first diode 11 is blown, which results in no metal connection path between the first pad 13 and the first diode 11 and no metal connection path between the first pad 13 and the second diode 14, and then the forward operating voltage of the MOS12 is applied to the first pad 13 to supply the forward operating voltage to the MOS12 through the first pad 13, so that the driving MOS12 operates normally. It should be noted that, in the present invention, when in the termination state, if the first metal line 301 connecting the MOS12 and the first diode 11 is not blown, in the subsequent process, the forward operating voltage applied to the first pad 13 turns on the second diode 14, and the operating voltage is applied to the second diode 14, so that the MOS12 cannot be driven to normally operate.
In addition, the present embodiment is described by taking a semiconductor structure including two metal layers as an example, and in practical applications, the number of metal layers included in the semiconductor structure is determined according to needs, but generally, the number of metal layers is much larger than two.
This flow ends by this point.
Based on the above-mentioned gate protection method, fig. 5 is a flowchart of an embodiment of the gate protection method provided by the present invention. As shown in fig. 5, the method comprises the steps of:
in step 501, in an initial state, the gate 105 of the MOS12 is connected to the first N-pole 107 of the first diode 11 and the second P-pole 109 of the second diode 14 through the first metal line 301, respectively, the first P-pole 101 of the first diode 11 is grounded, and the second N-pole 110 of the second diode 14 is grounded.
In the termination state, the first pad 13 is connected to the gate 105 of the MOS12, the second pad 16 is simultaneously connected to the first N-pole 107 of the first diode 11 and the second P-pole 109 of the second diode, and a voltage is applied between the first pad 13 and the second pad 16, so that the metal wire connecting the MOS12 and the first diode 11 in the first metal wire 301 is blown out, step 502.
The current density on the first metal line is greater than 10000000 amps per square centimeter when in the termination state.
The width of a metal wire connecting the MOS and the first diode in the first metal wire is more than or equal to 0.09 and less than or equal to 0.2 microns.
For a detailed description of an embodiment of a gate protection method provided by the present invention, reference is made to the corresponding description in the embodiment of the apparatus shown in fig. 4, which is not repeated herein.
This flow ends by this point.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A gate protection device, the device comprising: the device comprises a field effect transistor MOS, a first diode, a second diode, a first metal wire, a first bonding pad and a second bonding pad; wherein,
in the forming stage of the metal interconnection line, the grid electrode of the MOS is respectively connected to a first N pole of the first diode and a second P pole of the second diode through the first metal wire, the first P pole of the first diode is grounded, and the second N pole of the second diode is grounded;
after the metal interconnection line is formed, in the forming stage of a first bonding pad and a second bonding pad, the first bonding pad is connected with a grid electrode of the MOS, the second bonding pad is simultaneously connected with a first N electrode of the first diode and a second P electrode of the second diode, voltage is applied between the first bonding pad and the second bonding pad, and a metal wire connected with the MOS and the first diode in the first metal wire is fused.
2. The apparatus of claim 1, wherein a current density on the first metal line is greater than 10000000 amps per square centimeter during a stage of forming the first pad and the second pad after the metal interconnect line is formed.
3. The apparatus of claim 2, wherein a width of a metal line of the first metal line connecting the MOS and the first diode is greater than or equal to 0.09 and less than or equal to 0.2 μm.
4. A method of gate protection, the method comprising:
in the forming stage of the metal interconnection line, a grid electrode of the MOS is respectively connected to a first N pole of the first diode and a second P pole of the second diode through a first metal wire, the first P pole of the first diode is grounded, and the second N pole of the second diode is grounded;
after the metal interconnection line is formed, in the forming stage of the first bonding pad and the second bonding pad, the first bonding pad is connected with the grid electrode of the MOS, the second bonding pad is simultaneously connected with the first N electrode of the first diode and the second P electrode of the second diode, and voltage is applied between the first bonding pad and the second bonding pad, so that the metal wire connected with the MOS and the first diode in the first metal wire is fused.
5. The method of claim 4, wherein the current density on the first metal line is greater than 10000000 amps per square centimeter during a stage of forming the first pad and the second pad after the metal interconnect line is formed.
6. The method of claim 5, wherein a width of a metal line of the first metal line connecting the MOS and the first diode is greater than or equal to 0.09 and less than or equal to 0.2 μm.
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| US5691234A (en) * | 1995-08-03 | 1997-11-25 | United Microelectronics Corporation | Buried contact method to release plasma-induced charging damage on device |
| CN1845331A (en) * | 2005-04-07 | 2006-10-11 | 冲电气工业株式会社 | Semiconductor device |
| CN101083264A (en) * | 2006-06-02 | 2007-12-05 | 中芯国际集成电路制造(上海)有限公司 | Proctive circuit of metal-oxide-semiconductor transistor and its producing method |
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