CN102033810B - Method for managing a plurality of blocks of flash memory, relevant memory device and controller thereof - Google Patents
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Abstract
The invention provides a method for managing a plurality of blocks of a flash memory, a relevant memory device and a controller thereof. The method comprises the following steps of: dynamically deciding a linkage category on a logical block address according to at least one judging standard, wherein the linkage category is selected from a plurality of preset linkage categories; and recording/updating the linkage category and linkage information corresponding to the linkage category on the logical block address. The invention also provides a relevant memory device and a controller thereof. The controller comprises a read-only memory and a microprocessor, wherein the read-only memory is used for storing a program code; and the microprocessor is used for executing the program code so as to control the access on the flash memory and manage the blocks.
Description
Technical field
The present invention relates to the access (Access) of flash memory (Flash Memory), more particularly, relate to a kind of method of a plurality of blocks for managing a flash memory and relevant memory storage and controller thereof.
Background technology
Because the technology of flash memory constantly develops, various portable memory storages (for example: the memory card that meets SD/MMC, CF, MS, XD standard) be implemented on widely many application in recent years.Therefore, the access control of the flash memory in these portable memory storages also just becomes quite popular subject under discussion.
With NAND type flash memory commonly used, it mainly can divide into single layer cell flash memory (SingleLevel Cell, SLC) and multi-layered unit flash memory (Multiple Level Cell, MLC) two large classes.The transistor that in the single layer cell flash memory each is taken as mnemon only has two kinds of charge values, is respectively applied to presentation logic value 0 and logical value 1.In addition, the transistorized storage capacity that in the multi-layered unit flash memory each is taken as mnemon then is fully utilized, adopt higher voltage to drive, (for example: 00,01,11,10) in a transistor, record two groups of position information with the voltage by different stage; In theory, the recording density of multi-layered unit flash memory can reach more than the twice of recording density of single layer cell flash memory, and this is extraordinary message for once for the related industry of the NAND type flash memory that runs into bottleneck in the evolution.
Compare with the single layer cell flash memory, because the price of multi-layered unit flash memory is more cheap, and can provide larger capacity in limited space, so multi-layered unit flash memory becomes the main flow that the portable memory storage on the market competitively adopts soon.Yet the problem that the instability of multi-layered unit flash memory causes is also appeared in one's mind one by one.For these problems, although some settling modes are provided in the correlation technique, always can't take into account operational effectiveness and system resource and use control.So, no matter take which settling mode, often have corresponding spinoff.Therefore, the method for a kind of novelty of needs is strengthened the data access of keyholed back plate flash memory, uses control to take into account operational effectiveness and system resource.
Summary of the invention
Therefore, one of purpose of the present invention is to provide a kind of method of a plurality of blocks for managing a flash memory and relevant memory storage and controller thereof, to address the above problem.
Another object of the present invention is to provide a kind of method of a plurality of blocks for managing a flash memory and relevant memory storage and controller thereof, to reach optimal operation usefulness and dynamically to reduce the running burden.
Another purpose of the present invention is to provide a kind of method of a plurality of blocks for management one flash memory and relevant memory storage and controller thereof, with the problem of dynamically avoiding pure page or leaf link architecture and the problem of pure block link architecture.In addition, can have long serviceable life by the portable memory storage that utilizes the present invention to realize.
A kind of method of a plurality of blocks for managing a flash memory is provided in the preferred embodiment of the present invention, described method comprises: dynamically determine to link kind for one of a logical block addresses according at least one criterion, wherein said link kind is selected from a plurality of pre-determined link kinds; And for described logical block addresses record/described link kind of renewal and corresponding to the link information of described link kind.
The present invention also provides a kind of memory storage accordingly when said method is provided, comprising: a flash memory, and described flash memory comprises a plurality of blocks; An and controller, be used for the described flash memory of access and manage described a plurality of block, wherein said controller dynamically determines to link kind for one of a logical block addresses according at least one criterion, and described link kind is selected from a plurality of pre-determined link kinds; Wherein said controller is for described logical block addresses record/described link kind of renewal and corresponding to the link information of described link kind.
The present invention also provides a kind of controller of memory storage accordingly when said method is provided, described controller is used for access one flash memory, and described flash memory comprises a plurality of blocks, and described controller comprises: a ROM (read-only memory) is used for storing a program code; And a microprocessor, be used for carrying out described program code with control to the access of described flash memory and manage described a plurality of block; The described controller of wherein carrying out described program code by described microprocessor dynamically determines a link kind for a logical block addresses according at least one criterion, and described link kind is selected from a plurality of pre-determined link kinds; And the described controller of carrying out described program code by described microprocessor is for described logical block addresses record/described link kind of renewal and corresponding to the link information of described link kind.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the synoptic diagram according to a kind of memory storage of the present invention one first embodiment.
Fig. 2 is the process flow diagram according to the method for a kind of a plurality of blocks for managing flash memory of one embodiment of the invention.
Fig. 3 to Fig. 6 is the in one embodiment synoptic diagram of related pre-determined link kind of method shown in Figure 2.
Fig. 7 is in one embodiment related pre-determined link kind and the synoptic diagram that corresponds respectively to the link information of more described pre-determined link kind of method shown in Figure 2.
Fig. 8 is in another embodiment related pre-determined link kind and the synoptic diagram that corresponds respectively to the link information of described pre-determined link kind of method shown in Figure 2.
[primary clustering symbol description]
100 memory storages, 110 Memory Controllers, 112 microprocessors
112C program code 112M ROM (read-only memory) 114 steering logics
116 memory buffer, 118 interface logics, 120 flash memories
730,830 logic entity page or leaf chained lists
910 are used for method 912,914 steps of a plurality of blocks of management one flash memory
Current_PPage current entity page position information
LB (0), LB (1), LB (2), LB (3) ..., LB (n) logical block addresses
LPage (0), LPage (1) ..., LPage (m-1) logical page address
PBA (X_0), PBA (X_2), PBA (X_3) ..., PBA (X_n), PBA (Y) physical blocks address
Type (1), Type (2), Type (3) pre-determined link kind
Embodiment
With reference to figure 1, Fig. 1 is the synoptic diagram according to a kind of memory storage 100 of the present invention one first embodiment, wherein the memory storage 100 of present embodiment especially for portable memory storage (for example: the memory card that meets SD/MMC, CF, MS, XD standard).Memory storage 100 comprises: a flash memory (Flash Memory) 120; And a controller, be used for access (Access) flash memory 120, wherein this controller Memory Controller 110 for example.According to present embodiment, Memory Controller 110 comprise a microprocessor 112, a ROM (read-only memory) (Read Only Memory, ROM) 112M, a steering logic 114, a memory buffer 116, with an interface logic 118.ROM (read-only memory) is used for storing a program code 112C, and microprocessor 112 then is used for executive routine code 112C with the access of control to flash memory 120.Note that program code 112C also need be stored in memory buffer 116 or any type of storer.
Generally speaking, flash memory 120 comprises a plurality of blocks (Block), and this controller (for example: by the Memory Controller 110 of microprocessor 112 executive routine code 112C) to flash memory 120 the erase running of data erase take block as unit.In addition, a block can record the page or leaf (Page) of specific quantity, and wherein this controller writes take page or leaf as unit the running that flash memory 120 carries out data writing.
In the practical operation, Memory Controller 110 by microprocessor 112 executive routine code 112C can utilize the assembly of itself inside to carry out all multi-control runnings, for example: utilize steering logic 114 to control the access running of flash memory 120 (especially at least one block or at least access running of one page), utilize memory buffer 116 to carry out required buffered and utilize interface logic 118 and a main device (HostDevice) mutual.
According to present embodiment, except energy access flash memory 120, this controller can also properly be managed these a plurality of blocks.Clearer and more definite, writing/more during new data, this controller can dynamically determine a link kind for a logical block addresses according at least one criterion (Criterion), wherein this link kind is selected from a plurality of pre-determined link kinds.In addition, this controller can link the link information of kind for this link kind of this logical block addresses record/renewal and corresponding to this.
Fig. 2 is the process flow diagram according to the method 910 of a kind of a plurality of blocks for managing a flash memory of one embodiment of the invention.The method can be applicable to memory storage shown in Figure 1 100, especially above-mentioned controller (for example: by the Memory Controller 110 of microprocessor 112 executive routine code 112C).In addition, the method can be implemented by utilizing memory storage shown in Figure 1 100, especially by utilizing above-mentioned controller to implement.The method is described as follows:
In step 912, above-mentioned controller (for example: by the Memory Controller 110 of microprocessor 112 executive routine code 112C) dynamically determines to link kind for one of a logical block addresses according at least one criterion, and wherein this link kind is selected from a plurality of pre-determined link kinds.For example: these a plurality of pre-determined link kinds comprise one first link kind, one second link kind, with one the 3rd link kind.Especially, when this criterion pointed out that linking between logical page (LPAGE) and the physical page is necessary, then under the control of this controller, this link kind related to link (the linking referred to as page or leaf) between logical page (LPAGE) and the physical page; Otherwise this link kind can only relate to link (the linking referred to as block) between logical blocks and the physical blocks.According to present embodiment, under the control of this controller, this link kind is dynamically switched between the kind that the kind that belongs to the page or leaf link and genus block link.
In step 914, this controller links the link information of kind for this link kind of this logical block addresses record/renewal and corresponding to this.For example: when this link kind was this first link kind, this link information comprised a physical blocks address.Again for example: when this link kind is this second link kind, this link information comprises a physical blocks address and current entity page position information, and this current entity page position information is for the position of pointing out for the up-to-date physical page that writes of this logical block addresses.Again for example: when this link kind was the 3rd link kind, this link information comprised a page link information.
Fig. 3 to Fig. 6 is the in one embodiment synoptic diagram of related pre-determined link kind of method shown in Figure 2, and wherein Fig. 3 and Fig. 4 correspond respectively to above-mentioned first, second and link kind, and Fig. 5 and Fig. 6 then link kind corresponding to the above-mentioned the 3rd.As shown in Figure 3, when this controller determines that in step 912 this link kind is this first link kind, then under the control of this controller, the logical blocks of this logical block addresses representative links to a physical blocks, and control this logical blocks all logical page (LPAGE)s 0,1 ..., with z link to respectively this physical blocks each physical page 0,1 ... with z.At this, this first link kind can be described as " directly link " (Direct Link).
In addition, as shown in Figure 4, when this controller determines that in step 912 this link kind is this second link kind, then under the control of this controller, the logical blocks of this logical block addresses representative links to a physical blocks, but in this logical blocks only some logical page (LPAGE) 1,2 ..., with x link to respectively this physical blocks a part of physical page 1,2 ... with x.At this, this second link kind can be described as " part is link directly " (Partial Direct Link).
In addition, when this controller determines that in step 912 this link kind is the 3rd link kind, then under the control of this controller, the logical blocks of this logical block addresses representative optionally is linked to one or more physical blocks, and the logical page (LPAGE) in this logical blocks links to the physical page of described physical blocks randomly.At this, the 3rd link kind can be described as " Random Links " (Random Link).For example: logical blocks shown in Figure 5 links to a physical blocks, and the logical page (LPAGE) 1,2 in this logical blocks ..., with x link to randomly this physical blocks physical page 1,2 ..., with x (shown in the arrow of Fig. 5).Again for example: logical blocks shown in Figure 6 links to two physical blocks, and the logical page (LPAGE) 0,1,2 in this logical blocks ..., with x link to randomly the physical blocks in Fig. 6 upper right corner physical page 0,1 ... wait and the physical page 0,1 of the physical blocks in Fig. 6 lower right corner ..., with y (shown in the arrow of Fig. 6).In another embodiment, perhaps the logical page (LPAGE) (for example logical page (LPAGE) 7 of the logical page (LPAGE) 3 of LB (p), LB (q)) that belongs to the Different Logic block address links to the Different Logic page or leaf (for example logical page (LPAGE) 8,9 of PBA (Y_0)) that belongs to same physical blocks address randomly.
Note that in the present embodiment Fig. 5 and Fig. 6 all link kind corresponding to the above-mentioned the 3rd.This is not limitation of the present invention just for illustrative purposes.Change example according to one of present embodiment, the 3rd link kind can further be subdivided at least two link kinds, corresponds respectively to the quantity of the physical blocks that this logical blocks links.
Fig. 7 is in one embodiment related pre-determined link kind and the synoptic diagram that corresponds respectively to the link information of described pre-determined link kind of method shown in Figure 2, wherein pre-determined link kind Type (1), Type (2), with Type (3) represent respectively above-mentioned first, second, with the 3rd link kind.In the present embodiment, the link information corresponding to pre-determined link kind Type (1) comprises a physical blocks address and the pointer that points to this physical blocks address.For example: for logical block addresses LB (0), this link kind is pre-determined link kind Type (1), and wherein the link information corresponding to pre-determined link kind Type (1) comprises physical blocks address PBA (X_0) and the index of pointing to physical blocks address PBA (X_0).Similarly, for logical block addresses LB (i), when i=3,4 ... or during n, this link kind is pre-determined link kind Type (1), and wherein the link information corresponding to pre-determined link kind Type (1) comprises physical blocks address PBA (X_i) and the index of pointing to physical blocks address PBA (X_i).
In addition, comprise current entity page position information and a physical blocks address corresponding to the link information of pre-determined link kind Type (2), and comprise the pointer of this current entity page position information of sensing and/or this physical blocks address.For example: for logical block addresses LB (2), this link kind is pre-determined link kind Type (2), wherein the link information corresponding to pre-determined link kind Type (2) comprises current entity page position information Current_PPage and physical blocks address PBA (X_2), and also comprises the index of pointing to current entity page position information Current_PPage and/or physical blocks address PBA (X_2).Especially in the present embodiment, current entity page position information Current_PPage shown in Figure 7 is arranged in physical blocks address PBA (X_2) before, and for this pointed current entity page position information Current_PPage of logical block addresses LB (2).This is not limitation of the present invention just for illustrative purposes.Change example according to one of present embodiment, current entity page position information Current_PPage can be arranged in physical blocks address PBA (X_2) afterwards, and can point to physical blocks address PBA (X_2) for this pointer of logical block addresses LB (2).
In addition, the link information corresponding to pre-determined link kind Type (3) comprises page link information and the pointer that points to this page link information.For example: for logical block addresses LB (1), this link kind is pre-determined link kind Type (3), wherein comprises the pointer of a logic entity page or leaf chained list 730 and sensing logic entity page or leaf chained list 730 corresponding to the link information of pre-determined link kind Type (3).As shown in Figure 7, this controller is for logical block addresses LB (1) record/renewal one physical blocks address PBA (Y).Especially, in logic entity page or leaf chained list 730, this controller is for the corresponding physical page address of logical page address LPage (j) record/renewal that belongs to logical block addresses PBA (Y), in order to can find the data that belong to logical block addresses LB (1) in the future, wherein j=0,1 ... or (m-1).So, logic entity page or leaf chained list 730 comprise physical blocks address PBA (Y) and correspond respectively to the logical page address LPage (0), the LPage (1) that belong to logical block addresses LB (1) ..., with m the physical page address of LPage (m-1).This is not limitation of the present invention just for illustrative purposes.Change example according to one of present embodiment, physical blocks address PBA (Y) can place outside (being stored in) logic entity page or leaf chained list 730.According to another variation example of present embodiment, this logic entity page or leaf chained list can comprise above a physical blocks address.
Fig. 8 is in another embodiment related pre-determined link kind and the synoptic diagram that corresponds respectively to the link information of those pre-determined link kinds of method shown in Figure 2.Present embodiment is variation example embodiment illustrated in fig. 7, and wherein above-mentioned logic entity page or leaf chained list 730 is replaced by logic entity page or leaf chained list 830.In logic entity page or leaf chained list 830, this controller is for a corresponding physical blocks address and the physical page address of logical page address LPage (j) record/renewal that belongs to logical block addresses LB (1), wherein j=0,1 ... or (m-1).Especially, this controller is record/renewal plural groups physical blocks address and physical page address in logic entity page or leaf chained list 830, in order to can find the data that belong to logical block addresses LB (1) in the future, wherein this a plurality of physical blocks address each other can be not identical, can comprise physical blocks address PBA (Y_1), PBA (Y_7), PBA (Y_3) etc. such as this a plurality of physical blocks address.As shown in Figure 8, each row (or project) of logic entity page or leaf chained list 830 comprise a group object block address and physical page address, and each row (or project) from top to bottom correspond respectively to each logical page address LPage (0), the LPage (1) that belong to logical block addresses LB (1) ..., with LPage (m-1).Present embodiment and the routine similar part of above-mentioned each embodiment/variation no longer repeat to give unnecessary details.
One of benefit of the present invention is, for selecting of this link kind, the behavior that writes of method of the present invention and relevant memory storage and the visual main device of controller thereof is dynamically switched between the pattern of the kind that belongs to the page or leaf link and the pattern that belongs to the kind that block link, so method of the present invention and relevant memory storage and controller thereof can reach optimal operation usefulness and dynamically reduce to operate and bear.For example, continuously and intactly a certain logical blocks is write fashionablely when main device, then be applicable to the pattern of " directly link " in the link kind; And continuously and partly a certain logical blocks is write fashionablely when main device, then be applicable to the pattern of " part directly link " in the link kind; And if the main device initial stage writes a certain logical blocks continuously, then but change it and write behavior, for example change into randomly and write, then on the link kind, can dynamically change into from the pattern of " part is link directly " pattern of " Random Links ".In addition, compared with prior art, method of the present invention and relevant memory storage and controller thereof not only possess better performance, and dynamically avoid the problem of pure page or leaf link architecture and the problem of pure block link architecture.In addition, can have long serviceable life by the portable memory storage that utilizes the present invention to realize.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. a method that is used for a plurality of blocks of management flash memory is characterized in that described method is used for the management of multi-layered unit flash memory, comprises the steps:
Dynamically determine to link kind for one of a logical block addresses according at least one criterion, wherein said link kind is selected from a plurality of pre-determined link kinds, described a plurality of pre-determined link kind comprises the first link kind, the second link kind or the 3rd link kind, when main device is write fashionable to a certain logical blocks continuously and intactly, select the first link kind, when main device is write fashionable to a certain logical blocks continuously and partly, select the second link kind, if main device is fashionable for writing randomly, select the 3rd link kind, when the write state of main device switches, switch the link kind; And
For described logical block addresses record or upgrade described link kind and corresponding to the link information of described link kind.
2. the method for a plurality of blocks for managing flash memory according to claim 1 is characterized in that, wherein said a plurality of pre-determined link kinds comprise one first link kind; And when described link kind was described the first link kind, described link information comprised a physical blocks address.
3. the method for a plurality of blocks for managing flash memory according to claim 1 is characterized in that, wherein said a plurality of pre-determined link kinds comprise one second link kind; And when described link kind is described the second link kind, described link information comprises a physical blocks address and current entity page position information, and described current entity page position information is for the position of pointing out for the up-to-date physical page that writes of described logical block addresses.
4. the method for a plurality of blocks for managing flash memory according to claim 1 is characterized in that, wherein said a plurality of pre-determined link kinds comprise one the 3rd link kind; And when described link kind was described the 3rd link kind, described link information comprised a page link information.
5. the method for a plurality of blocks for managing flash memory according to claim 4 is characterized in that, wherein said page or leaf link information comprises a logic entity page or leaf chained list; And for described logical block addresses record or upgrade described link kind and also comprise corresponding to the step of the link information of described link kind:
For described logical block addresses record or upgrade a physical blocks address; And
In described logic entity page or leaf chained list, for the logical page address record that belongs to described logical block addresses or upgrade a corresponding physical page address.
6. the method for a plurality of blocks for managing flash memory according to claim 4 is characterized in that, wherein said page or leaf link information comprises a logic entity page or leaf chained list; And for described logical block addresses record or upgrade described link kind and also comprise corresponding to the step of the link information of described link kind:
In described logic entity page or leaf chained list, for the logical page address record that belongs to described logical block addresses or upgrade a corresponding physical blocks address and a physical page address.
7. the method for a plurality of blocks for the management flash memory according to claim 1 is characterized in that it also comprises:
According to described link kind and corresponding to the link information of described link kind, for described logical block addresses access data.
8. device that is used for a plurality of blocks of management flash memory, described device is used for the management of multi-layered unit flash memory, it is characterized in that, comprising:
Be used for the link kind determination device that at least one criterion of foundation dynamically determines to link for one of a logical block addresses kind, and described link kind is selected from a plurality of pre-determined link kinds, and described a plurality of pre-determined link kinds comprise the first link kind, the second link kind or the 3rd link kind; Continuously and intactly a certain logical blocks is write fashionablely when main device, this link kind determination device is selected first link kind; Continuously and partly a certain logical blocks is write fashionablely when main device, this link kind determination device is selected second link kind; If main device is fashionable for writing randomly, this link kind determination device is selected the 3rd link kind; When the write state of main device switched, this link kind determination device switched the link kind; With
Be used for for described logical block addresses record or upgrade described link kind and corresponding to the record updating device of the link information of described link kind.
9. device according to claim 8 is characterized in that, wherein said a plurality of pre-determined link kinds comprise one first link kind; And when described link kind was described the first link kind, described link information comprised a physical blocks address.
10. device according to claim 8 is characterized in that, wherein said a plurality of pre-determined link kinds comprise one second link kind; And when described link kind is described the second link kind, described link information comprises a physical blocks address and current entity page position information, and described current entity page position information is for the position of pointing out for the up-to-date physical page that writes of described logical block addresses.
11. device according to claim 8 is characterized in that, wherein said a plurality of pre-determined link kinds comprise one the 3rd link kind; And when described link kind was described the 3rd link kind, described link information comprised a page link information.
12. device according to claim 11 is characterized in that, wherein said page or leaf link information comprises a logic entity page or leaf chained list; By described record updating device for described logical block addresses record or upgrade a physical blocks address; And in described logic entity page or leaf chained list, by described record updating device for the logical page address record that belongs to described logical block addresses or upgrade a corresponding physical page address.
13. device according to claim 11 is characterized in that, wherein said page or leaf link information comprises a logic entity page or leaf chained list; And in described logic entity page or leaf chained list, by described record updating device for the logical page address record that belongs to described logical block addresses or upgrade a corresponding physical blocks address and a physical page address.
14. device according to claim 8 is characterized in that, wherein said device also comprises for according to described link kind and corresponding to the link information of described link kind, for the access device of described logical block addresses access data.
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| CN101123116A (en) * | 2006-08-09 | 2008-02-13 | 安国国际科技股份有限公司 | Memory device and its reading and writing method |
| CN101494086A (en) * | 2008-01-24 | 2009-07-29 | 群联电子股份有限公司 | Memory device, controller and switching method for flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101123116A (en) * | 2006-08-09 | 2008-02-13 | 安国国际科技股份有限公司 | Memory device and its reading and writing method |
| CN101494086A (en) * | 2008-01-24 | 2009-07-29 | 群联电子股份有限公司 | Memory device, controller and switching method for flash memory |
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