CN102033812B - Method for managing plurality of blocks of flash memory and relevant memory device and controller thereof - Google Patents
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Abstract
The invention provides a method for managing a plurality of blocks of a flash memory and a relevant memory device and a controller thereof. The method comprises the following steps of: recording/updating link information for a logic block address, wherein the link information comprises a plurality of physical block addresses which are linked to the logic block address and each physical block address represents one of the plurality of blocks; and when a block represented by one of the plurality of physical block addresses does not contain any active page, selectively erasing the block and removing the physical block address from the link information. The invention also provides a relevant memory device and a controller thereof. The controller comprises a read-only memory which is used for storing a program code and a microprocessor which is used for executing the program code so as to access the flash memory and manage the plurality of blocks.
Description
Technical field
The present invention relates to the access (Access) of flash memory (Flash Memory), more particularly, relate to a kind of method of a plurality of blocks for managing a flash memory and relevant memory storage and controller thereof.
Background technology
Because the technology of flash memory constantly develops, various portable memory storages (for example: the memory card that meets SD/MMC, CF, MS, XD standard) be implemented on widely in many application in recent years.Therefore, the access control of the flash memory in these portable memory storages also just becomes quite popular topic.
With NAND type flash memory commonly used, it mainly can divide into single layer cell flash memory (SingleLevel Cell, SLC) and multi-layered unit flash memory (Multiple Level Cell, MLC) two large classes.The transistor that in the single layer cell flash memory each is taken as mnemon only has two kinds of charge values, is respectively applied to presentation logic value 0 and logical value 1.In addition, the transistorized storage capacity that in the multi-layered unit flash memory each is taken as mnemon then is fully utilized, adopt higher voltage to drive, (for example: 00,01,11,10) in a transistor, record two groups of position information with the voltage by different stage; In theory, the recording density of multistage cell flash memory can reach more than the twice of recording density of single-order cell flash memory, and this is extraordinary message for once for the related industry of the NAND type flash memory that runs into bottleneck in the evolution.
Compare with the single layer cell flash memory, because the price of multi-layered unit flash memory is more cheap, and can provide larger capacity in limited space, so multi-layered unit flash memory becomes the main flow that the portable memory storage on the market competitively adopts soon.Yet the problem that the instability of multi-layered unit flash memory causes is also appeared in one's mind one by one.For example: according to correlation technique, in case degradation when flash memory is many because using, user's data just may can be lost at any time.Especially, compare with the single layer cell flash memory, the upper limit of the number of times of erasing of each block in the multi-layered unit flash memory (Erase Count) is relatively low, and this meeting is so that above-mentioned instable problem is more outstanding.
The upper limit of the number of times of erasing that it should be noted that each block of flash memory often reduces along with the employing of new manufacturing technology.Yet the progress of manufacturing technology is the important means of flash memory manufacturer reduction cost often; Under this situation, above-mentioned instable problem will be more serious.Therefore, the method for a kind of novelty of needs is strengthened the data access of keyholed back plate flash memory, to guarantee the integrality of user's data.
Summary of the invention
Therefore, one of purpose of the present invention is to provide a kind of method of a plurality of blocks for managing a flash memory and relevant memory storage and controller thereof, to address the above problem.
Another object of the present invention is to provide a kind of method of a plurality of blocks for managing a flash memory and relevant memory storage and controller thereof, promoting operational effectiveness and to reduce the number of times of the merging running of the block in the described flash memory, even can merge running.
Another purpose of the present invention is to provide a kind of method of a plurality of blocks for management one flash memory and relevant memory storage and controller thereof, with advancing the speed of the number of times of erasing that slows down the block in the flash memory.Therefore, can have long serviceable life by the portable memory storage that utilizes the present invention to realize.
A kind of method of a plurality of blocks for managing a flash memory is provided in the preferred embodiment of the present invention, described method comprises: for logical block addresses record/renewal link information, wherein said link information comprises a plurality of physical blocks address that links to described logical block addresses, and each physical blocks address represents the block in described a plurality of block; And when the block of the physical blocks address representative in described a plurality of physical blocks address during without active page, the described block and from described link information, remove described physical blocks address of optionally erasing.
The present invention also provides a kind of memory storage accordingly when said method is provided, it includes: a flash memory, and described flash memory comprises a plurality of blocks; An and controller, be used for the described flash memory of access and manage described a plurality of block, wherein said controller is for logical block addresses record/renewal link information, and described link information comprises a plurality of physical blocks address that links to described logical block addresses, and each physical blocks address represents the block in described a plurality of block; Wherein when the block of the physical blocks address representative in described a plurality of physical blocks address during without active page, optionally erase described block and from described link information, remove described physical blocks address of described controller.
The present invention also provides a kind of controller of memory storage accordingly when said method is provided, described controller is to be used for access one flash memory, and described flash memory comprises a plurality of blocks, and described controller includes: a ROM (read-only memory) is used for storing a program code; And a microprocessor, be used for carrying out described program code with control to the access of described flash memory and manage described a plurality of block; Wherein carry out the described controller of described program code for logical block addresses record/renewal link information by described microprocessor, and described link information comprises a plurality of physical blocks address that links to described logical block addresses, and each physical blocks address represents the block in described a plurality of block; And when the block of the physical blocks address representative in described a plurality of physical blocks address during without active page, optionally erase described block and from described link information, remove described physical blocks address of the described controller of carrying out described program code by described microprocessor.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the synoptic diagram according to a kind of memory storage of the present invention one first embodiment.
Fig. 2 is the process flow diagram according to the method for a kind of a plurality of blocks for managing a flash memory of one embodiment of the invention.
Fig. 3 is the in one embodiment synoptic diagram of related link information of method shown in Figure 2.
[primary clustering symbol description]
100 memory storages, 110 Memory Controllers, 112 microprocessors
112C program code 112M ROM (read-only memory) 114 steering logics
116 memory buffer, 118 interface logics, 120 flash memories
300-i link information 318-i physical blocks address table 320-i logic entity page or leaf chained list
910 are used for the method for a plurality of blocks of management one flash memory
The current blank page of 912,914 step Current_PPage position
LB (0), LB (1) ..., LB (i) ..., LB (n) logical block addresses
LPage (0), LPage (1) ..., LPage (m-1) logical page address
Page_Link_Table points to the pointer of logic entity page or leaf chained list
The quantity of PBA_Count physical blocks address
PBA (0), PBA (1) ..., PBA (N) physical blocks address
PBAT (0), PBAT (1) ..., PBAT (N) physical blocks address table index
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
With reference to figure 1, Fig. 1 is the synoptic diagram according to a kind of memory storage 100 of the present invention one first embodiment, and wherein the memory storage 100 of present embodiment (for example: the memory card that meets SD/MMC, CF, MS, XD standard) can be portable memory storage.Memory storage 100 comprises: a flash memory (Flash Memory) 120; And a controller, be used for access (Access) flash memory 120, wherein this controller Memory Controller 110 for example.According to present embodiment, Memory Controller 110 comprise a microprocessor 112, a ROM (read-only memory) (Read Only Memory, ROM) 112M, a steering logic 114, a memory buffer 116, with an interface logic 118.ROM (read-only memory) is used for storing a program code 112C, and microprocessor 112 then is used for executive routine code 112C with the access of control to flash memory 120.Note that program code 112C also need be stored in memory buffer 116 or any type of storer.
Generally speaking, flash memory 120 comprises a plurality of blocks (Block), and this controller (for example: by the Memory Controller 110 of microprocessor 112 executive routine code 112C) to flash memory 120 the erase running of data erase take block as unit.In addition, a block can record the page or leaf (Page) of specific quantity, and wherein this controller writes take page or leaf as unit the running that flash memory 120 carries out data writing.
In the practical operation, Memory Controller 110 by microprocessor 112 executive routine code 112C can utilize the assembly of itself inside to carry out all multi-control runnings, for example: utilize steering logic 114 to control the access running of flash memory 120 (especially at least one block or at least access running of one page), utilize memory buffer 116 to carry out required buffered and utilize interface logic 118 and a main device (HostDevice) mutual.
According to present embodiment, except energy access flash memory 120, this controller can also properly be managed these a plurality of blocks.Clearer and more definite, writing/more during new data, this controller can be for logical block addresses record/renewal link information, and wherein this link information comprises a plurality of physical blocks address that links to this logical block addresses, and each physical blocks address represents the block in these a plurality of blocks.In addition, when the block of the physical blocks address representative in this a plurality of physical blocks address during without active page (Valid Page), this block and from this link information, remove this physical blocks address of optionally erasing.
At this, active page representative has the data page of valid data, especially represents actual link to a first instance page or leaf of a certain logical page address.Since this controller to flash memory 120 the erase running of data erase take block as unit, so when this controller for this logical page address more during new data, the data that can upgrade write a second instance page or leaf, and the linking relationship between this logical page address and this first instance page or leaf is substituted by linking relationship between this logical page address and this second instance page or leaf.So, this controller is cancelled the linking relationship between this logical page address and this first instance page or leaf.So this first instance page or leaf is active page no longer just, be to be regarded as invalid page or leaf (Invalid Page).
Fig. 2 is the process flow diagram according to the method 910 of a kind of a plurality of blocks for managing a flash memory of one embodiment of the invention.The method can be applicable to memory storage shown in Figure 1 100, especially above-mentioned controller (for example: by the Memory Controller 110 of microprocessor 112 executive routine code 112C).In addition, the method can be implemented by utilizing memory storage shown in Figure 1 100, especially by utilizing above-mentioned controller to implement.The method is described as follows:
In step 912, above-mentioned controller (for example: by the Memory Controller 110 of microprocessor 112 executive routine code 112C) is for logical block addresses record/renewal link information, wherein this link information comprises a plurality of physical blocks address that links to this logical block addresses, and each physical blocks address represents the block in these a plurality of blocks.Especially, this link information also comprises current entity page position information, for the position of pointing out for the up-to-date physical page that writes of this logical block addresses.In addition, this link information comprises that also out of Memory can be for reference.So, when this controller will carry out access for this logical block addresses in the future, can come access to belong to the data of this logical block addresses according to this link information.
In step 914, when the block of the physical blocks address representative in this a plurality of physical blocks address during without active page, optionally erase this block and from this link information, remove this physical blocks address of this controller.For example: when the block of this physical blocks address representative during without active page, erase immediately this block and from this link information, remove this physical blocks address of this controller.This is not limitation of the present invention just for illustrative purposes.Change example according to one of present embodiment, when the block of this physical blocks address representative during without active page, this controller is based on erase this block and remove the running of this physical blocks address of triggering of a particular event.Like this, this controller is waited until just erase this block and remove this physical blocks address from this link information of the generation of this particular event.Another variation example according to present embodiment, when having reached a predetermined value without the quantity of the block of active page in the middle of the block of those physical blocks address representatives, this controller is erased these in the lump without the block of active page and remove in fact tagma block address from this link information.Another variation example according to present embodiment, when the quantity of the block of those physical blocks address representatives has reached a predetermined value, this controller merges (Merge) at least one new spacing block with the active page of at least a portion block in the block of those physical blocks address representatives, and this at least a portion block and remove in fact tagma block address from this link information of erasing.Especially in this variation example, this at least a portion block is for having one or more blocks of minimum (or less) active page in the middle of the block of those physical blocks address representatives.
According to present embodiment, this link information also comprises a page link information.This controller can judge that whether the block of this physical blocks address representative is without active page according to this page link information.Especially, this page link information comprises a logic entity page or leaf chained list; Like this, in this logic entity page or leaf chained list, this controller just can be for the logical page address record that belongs to this logical block addresses/renewal corresponding a physical blocks address or its representative information, and the corresponding physical page address of record/renewal.About the implementation detail of this link information, please refer to Fig. 3 and further specify.
Fig. 3 is the in one embodiment synoptic diagram of related link information 300-i of method shown in Figure 2.In step 912, above-mentioned controller (for example: by the Memory Controller 110 of microprocessor 112 executive routine code 112C) can be for arbitrary logical block addresses LB (i) record/renewal link information, wherein i=0,1 ... or n.As shown in Figure 3, link information 300-i comprises: current entity page position information for example current blank page position Current_PPage, point to logic entity page or leaf chained list 320-i a pointer Page_Link_Table, link to logical block addresses LB (i) a plurality of physical blocks address (for example: physical blocks address PBA (0) shown in Figure 3, PBA (1) ..., with PBA (N)) quantity PBA_Count and the physical blocks address table 318-i with this a plurality of physical blocks address.Current blank page position Currrent_PPage is used for indicating up-to-date one page data should write for which physical page.In the present embodiment, physical blocks address PBA (0), PBA (1) ..., with PBA (N) represent respectively physical blocks 0,1 ... with N.This controller sequentially used physical blocks 0,1 ..., store the data belong to logical block addresses LB (i) with N, and sequentially physical blocks address table 318-i recorded physical blocks address PBA (0), PBA (1) ..., with PBA (N).This is not limitation of the present invention just for illustrative purposes.In practical operation, can store any by the physical blocks address of this controller for the physical blocks of logical block addresses LB (i) data writing among the physical blocks address table 318-i.Especially, this controller can increase newly in physical blocks address table 318-i at any time or remove any physical blocks address, and can readjust as required the position of the physical blocks address among the physical blocks address table 318-i.
Generally speaking, physical blocks address among the physical blocks address table 318-i can be the physical blocks address of the block of any part in these a plurality of blocks, and the order of those physical blocks addresses does not need identical with the order of block of any part in these a plurality of blocks, and two physical blocks addresses in the wantonly two adjacent fields among the physical blocks address table 318-i need not to be continuous.For example: after repeatedly carrying out data access for logical block addresses LB (i), this controller sequentially physical blocks address table 318-i recorded physical blocks address PBA (1024), PBA (20), PBA (8), PBA (74) ... etc., represent respectively physical blocks 1024,20,8,74 ... etc., be exactly the physical blocks that still be used for to store at that time the data that belonged to logical block addresses LB (i).
In the present embodiment, this controller at first uses the physical blocks 0 of physical blocks address PBA (0) representative to write/upgrade the data that belong to logical block addresses LB (i), and physical blocks address PBA (0) is recorded in physical blocks address table 318-i, wherein only have at first physical blocks address PBA (0) among the physical blocks address table 318-i, and the initial value of quantity PBA_Count equals 1.In this process, this controller is record/many group objects of renewal block address table index and physical page address in logic entity page or leaf chained list 320-i, in order to can find the data that belong to logical block addresses LB (i) in the future, wherein each row (or project) of logic entity page or leaf chained list 320-i comprise a group object block address table index and physical page address, and each row (or project) from top to bottom correspond respectively to each logical page address LPage (0) that belongs to logical block addresses LB (i), LPage (1), ..., with LPage (m-1).
Please note, the physical blocks address table index of present embodiment be selected from the physical blocks address table index PBAT (0) shown in Fig. 3 upper right corner, PBAT (1) ..., with PBAT (N), and this controller can according to physical blocks address table index PBAT (0), PBAT (1) ..., with PBAT (N) in the middle of physical blocks address table 318-i, find out respectively physical blocks address PBA (0), PBA (1) ..., with PBA (N).Like this, each stored physical blocks address table index is the representative information (index information) of a corresponding physical blocks address among the logic entity page or leaf chained list 320-i, wherein the typical data amount of this representative information helps to save the storage area and promotes overall operation usefulness so store this representative information (and directly not storing this ground, corresponding entity district sector address) in logic entity page or leaf chained list 320-i less than the data volume of this corresponding physical blocks address.In addition, the physical blocks address table index PBAT (0) of present embodiment, PBAT (1) ..., be respectively 0,1 with PBAT (N) ... with N, also be the cis-position of each field of physical blocks address table 318-i, during use on the historical facts or anecdotes border physical blocks address table 318-i needn't store physical blocks address table index PBAT (0), PBAT (1) ..., with PBAT (N).This is not limitation of the present invention just for illustrative purposes.Change example according to one of present embodiment, physical blocks address table index PBAT (0), PBAT (1) ..., can be other numerical value with PBAT (N).According to another variation example of present embodiment, this controller directly stores this corresponding physical blocks address (and not storing this representative information) in logic entity page or leaf chained list 320-i; That is to say, this controller is record/many group objects of renewal block address and physical page address in logic entity page or leaf chained list 320-i, in order to can find the data that belong to logical block addresses LB (i) in the future, wherein each row (or project) of logic entity page or leaf chained list 320-i comprise a group object block address and physical page address.
According to present embodiment, at the beginning of the process of setting up physical blocks address table 318-i, when the physical blocks of physical blocks address PBA (0) representative writes (Fully Programmed) fully, this controller then uses the physical blocks of physical blocks address PBA (1) representative to write/upgrade the data that belong to logical block addresses LB (i), and physical blocks address PBA (1) is recorded in physical blocks address table 318-i, wherein only have physical blocks address PBA (0) and PBA (1) among the physical blocks address table 318-i this moment, and the value of quantity PBA_Count to be modified be 2.In the case, in case this controller must be for a certain logical page address of logical block addresses LB (i) new data more, for example for logical page address LPage (m
0) new data more, then this controller upgrades among logic entity page or leaf chained list 320-i corresponding to logical page address LPage (m
0) a group object block address table index and physical page address, wherein this physical blocks address table index is updated to PBAT (1) by PBAT (0), and this physical page address is updated to the address of a new data page or leaf of physical blocks 1 by the address of a legacy data page or leaf of physical blocks 0.Also namely, this controller with cis-position among the physical blocks address table 318-i than cis-position among the peer link information updating physical blocks address table 318-i of a physical blocks (being the larger physical blocks of physical blocks address table index) of back than the peer link information of a physical blocks (being the less physical blocks of physical blocks address table index) of front.This is not limitation of the present invention just for illustrative purposes.Change example according to one of present embodiment, when the physical page of a particular block is write fashionable with the identical order of the logical page (LPAGE) of corresponding logical blocks continuously, this controller can be made as the pointer Page_Link_Table in the link information of this corresponding logical blocks sky (Null) value, to avoid pointing to any logic entity page or leaf chained list.
Similarly, in the present embodiment, when the physical blocks of physical blocks address PBA (j-1) representative is write fashionable fully, this controller uses the physical blocks of physical blocks address PBA (j) representative to write/upgrade the data that belong to logical block addresses LB (i), and physical blocks address PBA (j) is recorded in physical blocks address table 318-i, wherein store physical blocks address PBA (0) among the physical blocks address table 318-i this moment, PBA (1), ..., with PBA (j), and the value of quantity PBA_Count is modified and is (j+1).In the case, in case this controller must be for a certain logical page address of logical block addresses LB (i) new data more, for example for logical page address LPage (m
1) new data more, then this controller upgrades among logic entity page or leaf chained list 320-i corresponding to logical page address LPage (m
1) a group object block address table index and physical page address, wherein this physical blocks address table index upgrade is PBAT (j), and this physical page address is updated to the address of the new data page or leaf of physical blocks j.
So, the above-mentioned running physical blocks address table 318-i that increased, wherein parameter j is changed to N by 1.So, when j=N, store among the physical blocks address table 318-i physical blocks address PBA (0), PBA (1) ..., with PBA (N), and the value of quantity PBA_Count is modified and is (N+1).
Along with the value of quantity PBA_Count constantly increases, each stored among physical blocks address table 318-i physical blocks address can be satisfied the described executive condition of step 914 one by one.So, when the block of the arbitrary physical blocks address representative in those physical blocks addresses during without active page, namely optionally erase this block and from this link information, remove this physical blocks address of this controller.Like this, method of the present invention and relevant memory storage and controller thereof the burden that can reduce significantly (Garbage Collection) running in the refuse collecting that merges running (Merging Operation) and invalid data page or leaf.
According to present embodiment, when link information 300-i has pointed out that K physical blocks address chain is connected to logical block addresses LB (i), burden about the rubbish Centralized Operation of invalid data page or leaf approximately is kept to (1/K) doubly, namely its usefulness be about prior art K doubly.Especially, as K during greater than the number of pages (for example m) of a block, just can remove fully about the burden of the rubbish Centralized Operation of invalid data page or leaf, and not need to merge running.Therefore, method of the present invention and relevant memory storage and controller thereof the number of times of erasing (the Erase Count's) that can slow down the block in the flash memory 120 advances the speed.
Compared with prior art, method of the present invention and relevant memory storage and controller thereof can be promoted operational effectiveness and reduce the number of times of the merging running of the block in the flash memory, even can merge running.In addition, method of the present invention and relevant memory storage and controller thereof the number of times of erasing that can slow down the block in the flash memory advances the speed.Therefore, can have long serviceable life by the portable memory storage that utilizes the present invention to realize.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (24)
1. method that is used for a plurality of blocks of management flash memory is characterized in that the method comprises:
For logical block addresses record/renewal link information, wherein said link information comprises a plurality of physical blocks address that links to described logical block addresses, and each physical blocks address represents the block in described a plurality of block; And
When the block of the physical blocks address representative in described a plurality of physical blocks address during without active page, it is described without the physical blocks of active page and remove described without the physical blocks address of active page from described link information optionally to erase.
2. the method for a plurality of blocks for managing flash memory according to claim 1 is characterized in that wherein said link information also comprises current entity page position information, for the position of pointing out for the up-to-date physical page that writes of described logical block addresses.
3. the method for a plurality of blocks for managing flash memory according to claim 1 is characterized in that wherein said link information also comprises a page link information; And described method also comprises:
Judge that according to described page or leaf link information whether the block of described physical blocks address representative is without active page.
4. the method for a plurality of blocks for managing flash memory according to claim 3 is characterized in that, wherein said page or leaf link information comprises a logic entity page or leaf chained list; And also comprise for the step of described logical block addresses record/described link information of renewal:
In described logic entity page or leaf chained list, for the logical page address record that belongs to described logical block addresses/renewal corresponding a physical blocks address or its representative information, and the corresponding physical page address of record/renewal.
5. the method for a plurality of blocks for the management flash memory according to claim 4, it is characterized in that, wherein for described logical page address record/renewal corresponding described physical blocks address or its representative information, and the step of the corresponding described physical page address of record/renewal also comprises:
With cis-position in the physical blocks address table than cis-position in the described physical blocks address table of a peer link information updating of a physical blocks of back than a peer link information of a physical blocks of front.
6. the method for a plurality of blocks for managing flash memory according to claim 4 is characterized in that, wherein said page or leaf link information also comprises a pointer that points to described logic entity page or leaf chained list.
7. the method for a plurality of blocks for managing flash memory according to claim 1 is characterized in that wherein said link information also comprises the quantity of described a plurality of physical blocks address.
8. the method for a plurality of blocks for the management flash memory according to claim 1, it is characterized in that it is described without the physical blocks of active page and remove and describedly also comprise without the step of the physical blocks address of active page wherein optionally to erase from described link information:
When the block of described physical blocks address representative during without active page, the described block and from described link information, remove described physical blocks address of erasing immediately.
9. the method for a plurality of blocks for the management flash memory according to claim 1, it is characterized in that it is described without the physical blocks of active page and remove and describedly also comprise without the step of the physical blocks address of active page wherein optionally to erase from described link information:
When the block of described physical blocks address representative during without active page, based on erase described block and remove the running of described physical blocks address of triggering of a particular event.
10. the method for a plurality of blocks for the management flash memory according to claim 1, it is characterized in that it is described without the physical blocks of active page and remove and describedly also comprise without the step of the physical blocks address of active page wherein optionally to erase from described link information:
When having reached a predetermined value without the quantity of the block of active page in the middle of the block of described physical blocks address representative, erase in the lump these without the block of active page and from described link information, remove in fact tagma block address.
11. the method for a plurality of blocks for managing flash memory according to claim 1, it is characterized in that it is described without the physical blocks of active page and remove and describedly also comprise without the step of the physical blocks address of active page wherein optionally to erase from described link information:
When the quantity of the block of described a plurality of physical blocks address representative has reached a predetermined value, the active page of at least a portion block in the block of described a plurality of physical blocks address representative is merged at least one new spacing block, and the described at least a portion block and from described link information, remove in fact tagma block address of erasing.
12. the method for a plurality of blocks for managing flash memory according to claim 1 is characterized in that, also comprises:
Write continuously fashionablely with the identical order of the logical page (LPAGE) of corresponding logical blocks when the physical page of a particular block, the pointer in the link information of described corresponding logical blocks is nullified, to avoid pointing to any logic entity page or leaf chained list.
13. a device that is used for a plurality of blocks of management flash memory comprises:
The first module: be used for for logical block addresses record/renewal link information, wherein said link information comprises a plurality of physical blocks address that links to described logical block addresses, and each physical blocks address represents the block in described a plurality of block;
The second module: when being used for block when a physical blocks address representative of described a plurality of physical blocks address without active page, it is described without the physical blocks of active page and remove described without the physical blocks address of active page from described link information optionally to erase.
14. the device of a plurality of blocks for managing flash memory according to claim 13 is characterized in that wherein said link information also comprises current entity page position information, for the position of pointing out for the up-to-date physical page that writes of described logical block addresses.
15. the device of a plurality of blocks for managing flash memory according to claim 13 is characterized in that wherein said link information also comprises a page link information; The device of described a plurality of blocks for managing flash memory also comprises the 3rd module: be used for judging that according to described page or leaf link information whether the block of described physical blocks address representative is without active page.
16. the device of a plurality of blocks for managing flash memory according to claim 15 is characterized in that, wherein said page or leaf link information comprises a logic entity page or leaf chained list; Described the first module also is used at described logic entity page or leaf chained list, for the logical page address record that belongs to described logical block addresses/renewal corresponding a physical blocks address or its representative information, and the corresponding physical page address of record/renewal.
17. the device of a plurality of blocks for managing flash memory according to claim 16, it is characterized in that described the first module also is used for a physical blocks address table cis-position than cis-position in the described physical blocks address table of a peer link information updating of a physical blocks of back than a peer link information of a physical blocks of front.
18. the device of a plurality of blocks for managing flash memory according to claim 16 is characterized in that, wherein said page or leaf link information also comprises a pointer that points to described logic entity page or leaf chained list.
19. the device of a plurality of blocks for managing flash memory according to claim 13 is characterized in that wherein said link information also comprises the quantity of described a plurality of physical blocks address.
20. the device of a plurality of blocks for managing flash memory according to claim 13, it is characterized in that, when described the second module also is used for block when described physical blocks address representative without active page, the described block and from described link information, remove described physical blocks address of erasing immediately.
21. the device of a plurality of blocks for managing flash memory according to claim 13, it is characterized in that, when described the second module also is used for block when described physical blocks address representative without active page, based on erase described block and remove the running of described physical blocks address of triggering of a particular event.
22. the device of a plurality of blocks for managing flash memory according to claim 13, it is characterized in that, described the second module also is used for when having reached a predetermined value without the quantity of the block of active page in the middle of the block of described physical blocks address representative, erases in the lump these without the block of active page and remove in fact tagma block address from described link information.
23. the device of a plurality of blocks for managing flash memory according to claim 13, it is characterized in that, described the second module also is used for when the quantity of the block of more described physical blocks address representative has reached a predetermined value, the active page of at least a portion block in the block of more described physical blocks address representative is merged at least one new spacing block, and the described at least a portion block and from described link information, remove in fact tagma block address of erasing.
24. the device of a plurality of blocks for managing flash memory according to claim 13, it is characterized in that, the described device of a plurality of blocks for the management flash memory also comprises four module: be used for physical page when a particular block and be being write continuously fashionable with the identical order of the logical page (LPAGE) of corresponding logical blocks, pointer in the link information of described corresponding logical blocks is nullified, to avoid pointing to any logic entity page or leaf chained list.
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| TWI659304B (en) * | 2017-10-20 | 2019-05-11 | 慧榮科技股份有限公司 | Method for accessing flash memory module and associated flash memory controller and electronic device |
| CN110780812B (en) * | 2019-09-27 | 2021-08-24 | 苏州浪潮智能科技有限公司 | Method and device for invalidating hard disk data |
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| CN101123116A (en) * | 2006-08-09 | 2008-02-13 | 安国国际科技股份有限公司 | Memory device and its reading and writing method |
| CN101147133A (en) * | 2005-02-16 | 2008-03-19 | 桑迪士克股份有限公司 | Direct file data programming and deletion in flash memories |
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| CN101123116A (en) * | 2006-08-09 | 2008-02-13 | 安国国际科技股份有限公司 | Memory device and its reading and writing method |
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