CN102023839A

CN102023839A - ALPHA computing device

Info

Publication number: CN102023839A
Application number: CN 201010586534
Authority: CN
Inventors: 洪锦坤
Original assignee: Fuzhou Rockchip Electronics Co Ltd
Current assignee: Rockchip Electronics Co Ltd
Priority date: 2010-12-10
Filing date: 2010-12-10
Publication date: 2011-04-20
Anticipated expiration: 2030-12-10
Also published as: CN102023839B

Abstract

The invention discloses an ALPHA computing device, comprising two selectors with one channel selected in three channels, one adder, one subtractor, two multipliers, three latches, one binary to decimal converter and one cyclic shifter. The selectors with one channel selected in three channels are used to realize the function of switching parallel input to serial input. The adder, the subtractor and the multipliers are used to realize the operation function, namely X=(X1*C+X2*(A-C))/A, wherein the value of A is 256 which is two to the power of 8. The latches are used to switch the serial output to parallel output. The binary to decimal converter and the cyclic shifter are used to control input and output. The computing device disclosed by the invention is optimized by using the resource sharing principle, thereby effectively and significantly reducing the area of the chip.

Description

A kind of ALPHA arithmetical unit

[technical field]

The present invention relates to a kind of arithmetical unit, specifically be meant a kind of ALPHA arithmetical unit.

[background technology]

If realize the image overlay processing, just need use the ALPHA arithmetical unit with hardware.Existing ALPHA ALU architecture is comparatively complicated, and chip occupying area is bigger.

The normalized form of ALPHA computing is as follows:

R＝(R1*C+R2*(A-C))/A

G＝(G1*C+G2*(A-C))/A

B＝(B1*C+B2*(A-C))/A

The level of transparency of A for supporting; R1, G1, B1 are background data; R2, G2, B2 are foreground data; C is the foreground to transparent degree.

As realizing this computing, need a large amount of multiplier, totalizer, subtracter and divider, chip occupying area is very big.

[summary of the invention]

Technical matters to be solved by this invention is to provide a kind of resource, less ALPHA arithmetical unit of chip occupying area saved.

The present invention solves the problems of the technologies described above by the following technical solutions:

A kind of ALPHA arithmetical unit comprises that two 3 passages select 1 channel to channel adapter, a totalizer, a subtracter, two multipliers, three latchs, scale-of-two to change decimal system device, a cyclic shifter;

Described 3 passages select 1 channel to channel adapter to be used to realize parallel input commentaries on classics serial function;

Described totalizer, subtracter, multiplier are used to realize calculation function, X=(X1*C+X2* (A-C))/A, and the A value is 256,256 to be 28 powers;

Described latch is used to realize transformation from serial to parallel output;

Described scale-of-two changes decimal system device and cyclic shifter is used for realizing the control input and output.

The invention has the advantages that: utilize the principle of resource sharing that it is optimized, reduced a large amount of chip areas effectively.

[description of drawings]

The invention will be further described in conjunction with the embodiments with reference to the accompanying drawings.

Fig. 1 is computing circuit figure of the present invention.

[embodiment]

The normalized form of ALPHA computing is as follows:

R＝(R1*C+R2*(A-C))/A

G＝(G1*C+G2*(A-C))/A

B＝(B1*C+B2*(A-C))/A

Because three groups of formula operation modes are similar, thus the present invention make into to come computing by one group of formula, X=(X1*C+X2* (A-C))/A, the usable floor area of chip dwindles into original 1/3 like this.It is 28 powers that A is got 256,256, can remove a divider like this, has reduced certain area again.This computing circuit comprises that two 3 passages select 1 channel to channel adapter C1, C2, a totalizer A1, a subtracter D1, two multiplier M1, M2, three latch Q1, Q2, Q3, scale-of-two to change decimal system device F1, a cyclic shifter E1 as shown in Figure 1.

3 passages select 1 channel to channel adapter C1, C2 to be used to realize parallel input commentaries on classics serial function; Totalizer A1, subtracter D1, multiplier M1, M2 are used to realize calculation function, X=(X1*C+X2* (A-C))/A, and the A value is 256,256 to be 28 powers; Latch Q1, Q2, Q3 are used to realize transformation from serial to parallel output; Scale-of-two changes decimal system device F1 and cyclic shifter E1 is used for realizing the control input and output.

Principle of work:

1, judges whether that RESET is invalid and EN is effective? be, jumped to for the 2nd step, not, then continue this step;

2, scale-of-two changes decimal system device F1 and controls 3 passages and select 1 channel to channel adapter C1, C2 to select the R passage, the CLK output low level;

3, the R data are carried out computing through subtracter D1, multiplier M1, M2 and totalizer A1;

4, the result of cyclic shifter E1 control lock storage Q1 storage totalizer A1 computing;

5, scale-of-two changes decimal system device F1 and controls 3 passages and select 1 channel to channel adapter C1, C2 to select the G passage;

6, the G data are carried out computing through subtracter D1, multiplier M1, M2 and totalizer A1;

7, the result of cyclic shifter E1 control lock storage Q2 storage totalizer A1 computing;

8, scale-of-two changes decimal system device F1 and controls 3 passages and select 1 channel to channel adapter C1, C2 to select the B passage;

9, the B data are carried out computing through subtracter D1, multiplier M1, M2 and totalizer A1;

10, the result of cyclic shifter E1 control lock storage Q3 storage totalizer A1 computing;

11, CLK output high level; Jumped to for the 1st step.

The present invention utilizes the principle of resource sharing that it is optimized, and has reduced a large amount of chip areas effectively.

Claims

1. an ALPHA arithmetical unit is characterized in that: comprise that two 3 passages select 1 channel to channel adapter, a totalizer, a subtracter, two multipliers, three latchs, scale-of-two to change decimal system device, a cyclic shifter;