CN102023439B

CN102023439B - TFT (Thin Film Transistor) array structure and manufacturing method thereof

Info

Publication number: CN102023439B
Application number: CN 200910196482
Authority: CN
Inventors: 黄贤军
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2009-09-22
Filing date: 2009-09-22
Publication date: 2013-05-15
Anticipated expiration: 2029-09-22
Also published as: CN102023439A

Abstract

The invention relates to a TFT (Thin Film Transistor) array structure and a manufacturing method thereof. The TFT array structure comprises a substrate, a gate electrode metal layer, a gate electrode insulating layer, a semiconductor layer, an ohmic contact layer, a first insulating layer, a source electrode metal layer, a drain electrode metal layer, a channel between the source electrode metal layer and the drain electrode metal layer and a pixel electrode which covers the gate electrode insulating layer and is connected with the drain electrode metal layer through a through hole, wherein the pixel electrode and the gate electrode metal layer forms two poles of a storage capacitor, and the storage medium of the storage capacitor is a single-layer structure of a double-layer structure. Compared with the prior art, the storage capacitor has larger capacitance storage capacity.

Description

Tft array structure and manufacture method thereof

Technical field

The present invention relates to display technique, particularly tft array structure and manufacture method thereof.

Background technology

Because panel display apparatus has: the advantage such as light, thin, that occupation of land is little, power consumption is little, radiation is little is widely used in various data processing equipments such as TV, notebook computer, mobile phone, personal digital assistant etc.Along with the development of electronic industry, the performance of panel display apparatus is also more and more higher.

Take common thin-film transistor LCD device (Thin Film Transistor Liquid Crystal Display, TFT-LCD) as example, it belongs to a kind of in active matrix liquid crystal display.The principal feature of TFT-LCD is to configure a semiconductor switch device in each pixel, each pixel is an independently transistor of isolation mutually, because each pixel can directly be controlled by a pulse, thereby each node is relatively independent, but and stepless control, so not only improved the reaction time, can accomplish very accurate simultaneously on gray-scale Control.

For price and its yield rate of raising of effectively reducing TFT-LCD, the manufacturing process of active driving TFT array progressively is simplified, from seven times or six photoetching generally five photoetching of employing till now of beginning.Recently, four mask technique based on the slit photoetching technique begins set foot in the manufacturing field of TFT-LCD and progressively be applied, compare with five times traditional photoetching processes, the maximum characteristics of this technique are to form active layer and source leakage metallic pattern by a step slit photoetching process, thereby shortened the production cycle of TFT, reduced its production cost, but because it has used the slit photoetching process, manufacturing accuracy to mask plate has proposed very high requirement, difficulty and the cost of process exploitation are significantly improved, and brought very large difficulty for the raising of yield rate.

In addition, the somebody has proposed other modification method, specifically can consult the application for a patent for invention Publication Specification of Chinese patent application CN200710063236.X, its four road mask plate photoetching processes of having introduced a kind of employing common (non-slit photoetching technique) are made the method for TFT-LCD, only need the four mask step to get final product in the process that forms pixel graphics.

The tft array structure of described manufacturing comprises as shown in Figure 1: substrate 11; The Ohmic contact amorphous silicon layer 15 of the grid 12 that covers on substrate 11, gate insulator 13, semiconductor amorphous silicon layer 14 and doping; Cover on substrate 11, be positioned at the insulation course 16 in the zone outside grid 12, gate insulator 13, semiconductor amorphous silicon layer 14 and Ohmic contact amorphous silicon layer 15; Block the raceway groove (diagram) of Ohmic contact amorphous silicon layer 15; Cover source electrode 17a and the drain electrode 17b of Ohmic contact amorphous silicon layer 15 and insulation course 16; The passivation layer 18 of covering source electrode 17a and drain electrode 17b; Be positioned at the via hole (not shown) on drain electrode 17b; Cover the pixel electrode 19a of passivation layer 18, pixel electrode 19a is connected with drain electrode 17b by described via hole.

But still there are the following problems for above-mentioned tft array structure and manufacture method thereof.For example, the memory capacitance of utilizing the produced pixel cell of described manufacturing process is three layers of dielectric structure (amorphous silicons that comprise grid electrode insulating layer, semiconductor amorphous silicon layer and Ohmic contact doping), capacitances in series makes capacitance smaller, and the capacitance stores ability is relatively poor.

Summary of the invention

The purpose of this invention is to provide a kind of tft array structure and manufacture method thereof, solve the problem that in prior art, in the tft array structure, the memory capacitance capacitance is less, the capacitance stores ability is relatively poor.

For addressing the above problem, the present invention provides a kind of tft array structure on the one hand, comprising: substrate, and described substrate has first area and second area; The first insulation course covers the zone except first area and second area on described substrate; Thin-film transistor structure comprises the gate electrode metal layer, grid electrode insulating layer and the semiconductor layer that are positioned on described first area, and is positioned at source electrode metal layer and drain electrode metal level on described semiconductor layer and the first insulation course; Has the raceway groove that is positioned on the first area between described source electrode metal layer and drain electrode metal level; Described the first insulation course and described semiconductor layer have the surface of planarization; Be positioned at gate electrode metal layer and grid electrode insulating layer on described second area; The second insulation course covers the grid electrode insulating layer of described source electrode metal layer, raceway groove, drain electrode metal level, the first insulation course and described second area; Pixel electrode covers described the second insulation course, and is connected with described drain electrode metal level;

Described pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises grid electrode insulating layer and the second insulation course.

Alternatively, described tft array structure also comprises the via hole that is positioned at described the second insulation course and manifests described drain electrode metal level, and described pixel electrode is connected with described drain electrode metal level by described via hole.

Alternatively, described substrate also has the 3rd zone, and described tft array structure also comprises the gate electrode terminal, and it comprises: the gate electrode metal layer on the 3rd zone of the described substrate of covering; Be positioned at the first insulation course of the gate electrode metal layer periphery on described the 3rd zone; Cover the second insulation course of described the first insulation course; Cover the pixel electrode of described the second insulation course and described gate electrode metal layer.

Alternatively, described substrate also has the 4th zone, and described tft array structure also comprises and the sweep trace district of gate electrode metal floor one, and it comprises: the gate electrode metal layer and the grid electrode insulating layer that cover described substrate; Cover semiconductor layer and the source-drain electrode metal level of the grid electrode insulating layer periphery on described the 4th zone; Cover the second insulation course of the grid electrode insulating layer on described source-drain electrode metal level and described the 4th zone.

Alternatively, also be coated with ohmic contact layer between described semiconductor layer and described source-drain electrode metal level.

Alternatively, described substrate also has the 4th zone, and described tft array structure also comprises and the sweep trace district of gate electrode metal floor one, and it comprises: the gate electrode metal layer and the grid electrode insulating layer that cover described substrate; At least cover the first insulation course on described the 4th zone; Cover the source-drain electrode metal level of the first insulation course periphery on described the 4th zone; Cover the second insulation course of the first insulation course on described source-drain electrode metal level and described the 4th zone.

Alternatively, also be coated with semiconductor layer and ohmic contact layer between described the first insulation course and described grid electrode insulating layer.

Alternatively, described gate electrode metal layer, source electrode metal layer and drain electrode metal level are the monofilm that is selected from Cr, W, Ti, Ta, Mo, Al or Cu, perhaps are selected from least two kinds of composite membranes that metal forms in Cr, W, Ti, Ta, Mo, Al or Cu.

Alternatively, the material of described grid electrode insulating layer, the first insulation course and the second insulation course comprises oxide, nitride or oxides of nitrogen.

Alternatively, the material of described pixel electrode comprises indium tin oxide or indium-zinc oxide.

The present invention provides a kind of tft array structure on the other hand, comprising: substrate, and described substrate has first area and second area; The first insulation course covers the zone except first area and second area on described substrate; Thin-film transistor structure comprises the gate electrode metal layer, grid electrode insulating layer and the semiconductor layer that are positioned on described first area, and is positioned at source electrode metal layer and drain electrode metal level on described semiconductor layer and the first insulation course; Has the raceway groove that is positioned on the first area between described source electrode metal layer and drain electrode metal level; Described the first insulation course and described semiconductor layer have the surface of planarization; Be positioned at gate electrode metal layer and grid electrode insulating layer on described second area; Pixel electrode covers described grid electrode insulating layer, and is connected with described drain electrode metal level; Described pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises the grid electrode insulating layer.

Alternatively, described tft array structure also comprises the second insulation course that covers described source electrode metal layer, raceway groove and drain electrode metal level.

The present invention provides a kind of manufacture method of tft array structure aspect another, and comprising: substrate is provided, and described substrate has first area and second area; Sequentially form gate electrode metal layer, grid electrode insulating layer and semiconductor layer on described substrate; Utilize mask, definition the first photoetching offset plate figure; Take described the first photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and gate electrode metal layer on the zone outside described first area and second area, and manifest described substrate; First area and the zone outside second area at described substrate form the first insulation course; Form the source-drain electrode metal level on described the first insulation course and semiconductor layer; Utilize half tone mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, form the raceway groove that is positioned at the first area on described source-drain electrode metal level, described source-drain electrode metal level is blocked and forms source electrode metal layer and drain electrode metal level on the semiconductor layer on described the first insulation course and first area, to form thin-film transistor structure; Remove source-drain electrode metal level and semiconductor layer on described second area, and manifest described grid electrode insulating layer; Form the second insulation course on described source electrode metal layer, raceway groove, drain electrode metal level and grid electrode insulating layer; Form pixel electrode on described the second insulation course, described pixel electrode is connected with described drain electrode; Described pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises grid electrode insulating layer and the second insulation course.

Alternatively, the manufacture method of described tft array structure also is included in the step that forms ohmic contact layer between source-drain electrode metal level on the first area and semiconductor layer.

Alternatively, the manufacture method of described tft array structure also is included in and forms via hole on described the second insulation course so that the step that described pixel electrode is connected with described drain electrode metal level by described via hole.

Alternatively, take described the first photoetching offset plate figure as mask, the step of removing described semiconductor layer, grid electrode insulating layer and gate electrode metal layer specifically comprises: adopt dry etch process, etch away described semiconductor layer and grid electrode insulating layer; Adopt wet-etching technology, etch away described gate electrode metal layer.

Alternatively, the step of formation the first insulation course is specially: at the periphery of described gate electrode metal layer, grid electrode insulating layer and semiconductor layer coating organic film; The unnecessary organic film that adopts cineration technics will protrude from described semiconductor layer is removed, and forms the first insulation course.

Alternatively, source-drain electrode metal level and semiconductor layer on the described second area of described removal, and the step that manifests described grid electrode insulating layer specifically comprises: adopt wet-etching technology, etch away the source-drain electrode metal level of part; Adopt dry etch process, etch away the semiconductor layer of part.

Alternatively, described substrate also has the 3rd zone, and the manufacture method of described tft array structure also comprises the technique of making the gate electrode terminal, and described technique comprises: sequentially form gate electrode metal layer, grid electrode insulating layer and semiconductor layer on described substrate; Utilize mask plate, definition the first photoetching offset plate figure; Take described the first photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and gate electrode metal layer outside the 3rd zone; The periphery of the gate electrode metal layer on described the 3rd zone, grid electrode insulating layer and semiconductor layer forms the first insulation course; Utilize half tone mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, remove the semiconductor layer on the 3rd zone, and manifest described grid electrode insulating layer; Form the second insulation course on the grid electrode insulating layer on described the first insulation course and described the 3rd zone; Utilize mask plate, definition the 3rd photoetching offset plate figure; Take described the 3rd photoetching offset plate figure as mask, remove the second insulation course and grid electrode insulating layer on described the 3rd zone, and manifest described gate electrode metal layer; Form pixel electrode on the gate electrode metal layer on described the second insulation course and described the 3rd zone.

Alternatively, described substrate also has the 4th zone, the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises: sequentially form gate electrode metal layer, grid electrode insulating layer, semiconductor layer and source-drain electrode metal level on described substrate; Utilize mask plate, definition the first photoetching offset plate figure; Take described the first photoetching offset plate figure as mask, remove the source-drain electrode metal level on described the 4th zone; Remove the semiconductor layer on the 4th zone, and manifest described grid electrode insulating layer; Form the second insulation course on the grid electrode insulating layer on described source-drain electrode metal level and described the 4th zone.

Alternatively, described substrate also has the 4th zone, the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises: sequentially form gate electrode metal layer, grid electrode insulating layer, semiconductor layer and source-drain electrode metal level on described substrate; Utilize mask plate, definition the first photoetching offset plate figure; Take described the first photoetching offset plate figure as mask, remove the source-drain electrode metal level on described the 4th zone; Remove the semiconductor layer of the 4th upper part in zone, and manifest the described grid electrode insulating layer of part; Form the second insulation course on the semiconductor layer on described source-drain electrode metal level and described the 4th zone and grid electrode insulating layer.

Alternatively, the technique in described manufacturing sweep trace district also is included in the step that forms ohmic contact layer between described source-drain electrode metal level and semiconductor layer.

Further aspect of the present invention provides a kind of manufacture method of tft array structure, comprising: substrate is provided, and described substrate has first area and second area; Sequentially form gate electrode metal layer, grid electrode insulating layer and semiconductor layer on described substrate; Utilize half tone mask plate, definition the first photoetching offset plate figure; Take described the first photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part; Retain semiconductor layer, grid electrode insulating layer and gate electrode metal layer on described first area; Retain grid electrode insulating layer and gate electrode metal layer on described second area; Form the first insulation course on the periphery of described first area and described second area; Form the source-drain electrode metal level on described first area and described the first insulation course; Utilize mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, form the raceway groove that is positioned on the first area on described source-drain electrode metal level, described source-drain electrode metal level is blocked and forms source electrode metal layer and drain electrode metal level on the semiconductor layer on described the first insulation course and first area, to form thin-film transistor structure; Remove source-drain electrode metal level and the first insulation course on described second area, manifest described grid electrode insulating layer; Form the second insulation course on described source electrode metal layer, raceway groove, drain electrode metal level and grid electrode insulating layer; Form pixel electrode on described the second insulation course, described pixel electrode is connected with described drain electrode; Described pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises grid electrode insulating layer and the second insulation course.

Alternatively, the described step of removing semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part specifically comprises: adopt dry etch process, etch away described semiconductor layer and grid electrode insulating layer; Adopt wet-etching technology, etch away described gate electrode metal layer.

Alternatively, the step of described formation the first insulation course is specially: at the periphery of described gate electrode metal layer, grid electrode insulating layer and semiconductor layer coating organic film; The unnecessary organic film that adopts cineration technics will protrude from described semiconductor layer is removed, and forms the first insulation course.

Alternatively, the step of described formation raceway groove is specially: adopt wet-etching technology, etch away the source-drain electrode metal level on described first area; Adopt dry etch process, etch away the described semiconductor layer of segment thickness.

Alternatively, described for second area, remove described source-drain electrode metal level and the first insulation course, and the step that manifests the grid electrode insulating layer comprises specifically: adopt wet-etching technology, etch away the source-drain electrode metal level on described second area; Adopt cineration technics, ash melts the first insulation course on described second area.

Alternatively, described substrate also has the 3rd zone, and the manufacture method of described tft array structure also comprises the technique of making the gate electrode terminal, and described technique comprises: sequentially form gate electrode metal layer, grid electrode insulating layer and semiconductor layer on described substrate; Utilize half tone mask plate, definition the first photoetching offset plate figure; Take described photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part; Retain grid electrode insulating layer and gate electrode metal layer on described the 3rd zone; Form the first insulation course on the substrate outside described the 3rd zone and the grid electrode insulating layer on the 3rd zone; Form the second insulation course on described the first insulation course and grid electrode insulating layer; Utilize mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, remove the second insulation course and grid electrode insulating layer on described the 3rd zone, and manifest described gate electrode metal layer; Form pixel electrode on the gate electrode metal layer on described the second insulation course and described the 3rd zone.

Alternatively, described substrate also has the 4th zone, the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises: sequentially form gate electrode metal layer and grid electrode insulating layer on described substrate; Sequentially form the first insulation course and source-drain electrode metal level on described grid electrode insulating layer; Utilize mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, remove the source-drain electrode metal level on described the 4th zone, and manifest described the first insulation course; Form the second insulation course on the first insulation course on described source-drain electrode metal level and the 4th zone.

Alternatively, described substrate also has the 4th zone, the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises: sequentially form gate electrode metal layer, grid electrode insulating layer and semiconductor layer on described substrate; Utilize half tone mask plate, definition the first photoetching offset plate figure; Take described the first photoetching offset plate figure as mask, remove the semiconductor layer on described the 4th zone, and manifest described grid electrode insulating layer; Form the first insulation course on the grid electrode insulating layer on described the 4th zone; Form the source-drain electrode metal level on the first insulation course on described semiconductor layer and described the 4th zone; Utilize mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, remove the source-drain electrode metal level on described the 4th zone, and manifest described the first insulation course; Form the second insulation course on the first insulation course on described source-drain electrode metal level and described the 4th zone.

Alternatively, the technique in described manufacturing sweep trace district also is included in the step that forms ohmic contact layer between described the first insulation course and semiconductor layer.

The present invention also provides a kind of manufacture method of tft array structure on the one hand, comprising: substrate is provided, and described substrate has first area and second area; Sequentially form gate electrode metal layer, grid electrode insulating layer and semiconductor layer on described substrate; Utilize half tone mask plate, definition the first photoetching offset plate figure; Take described the first photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part; Retain semiconductor layer, grid electrode insulating layer and gate electrode metal layer on described first area; Retain grid electrode insulating layer and gate electrode metal layer on described second area; Form the first insulation course on the periphery of described first area and described second area; Form the source-drain electrode metal level on described first area and described the first insulation course; Utilize mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, form the raceway groove that is positioned on the first area on described source-drain electrode metal level, described source-drain electrode metal level is blocked and forms source electrode metal layer and drain electrode metal level on the semiconductor layer on described the first insulation course and first area, to form thin-film transistor structure; Remove source-drain electrode metal level and the first insulation course on described second area, manifest described grid electrode insulating layer; Form pixel electrode on described grid electrode insulating layer, described pixel electrode is connected with described drain electrode; Described pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises the grid electrode insulating layer.

Alternatively, source-drain electrode metal level on the described second area of described removal and the first insulation course, and after manifesting the step of described grid electrode insulating layer, the manufacture method of described tft array structure also is included in the step that forms the second insulation course on described source electrode metal layer, raceway groove and drain electrode metal level.

Alternatively, described substrate also has the 3rd zone, and the manufacture method of described tft array structure also comprises the technique of making the gate electrode terminal, and described technique comprises: sequentially form gate electrode metal layer, grid electrode insulating layer and semiconductor layer on described substrate; Utilize half tone mask plate, definition the first photoetching offset plate figure; Take described the first photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part; Retain grid electrode insulating layer and gate electrode metal layer on described the 3rd zone; Form the first insulation course on the substrate outside described the 3rd zone and the grid electrode insulating layer on the 3rd zone; Form the second insulation course on described the first insulation course and grid electrode insulating layer; Utilize mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, remove the second insulation course and grid electrode insulating layer on described the 3rd zone, and manifest described gate electrode metal layer; Form pixel electrode on the gate electrode metal layer on described the second insulation course and described the 3rd zone.

Compared with prior art, tft array structure provided by the invention, pixel electrode wherein and gate electrode metal layer consist of the two poles of the earth of memory capacitance, the storage medium of described memory capacitance is the single layer structure of grid electrode insulating layer or the two-layer structure that is made up by grid electrode insulating layer and the second insulation course, for the memory capacitance that tft array structure in prior art has three layers or more multi-layered storage medium structure, has larger capacitance stores ability.

In addition, owing to removing or part has been removed ohmic contact layer and the semiconductor layer in the sweep trace district between two data lines, making described two data lines not have electric current after applying varying voltage signal flows through between described two data lines, eliminate the cross-talk between pixel cell, improved image display effect.

Have, the present invention utilizes the etching technics of half tone mask plate again, can etch with less etching technics step the gate electrode terminal for the fixed drive circuit, can simplify technique and reduce costs.

Description of drawings

Fig. 1 is the structural representation of the tft array structure made in prior art;

Fig. 2 is the floor map of tft array structure provided by the invention;

Fig. 3 is the schematic cross-section of A1--A2 line of cut position in the first technical scheme in Fig. 2;

Fig. 4 is the schematic cross-section of B1--B2 line of cut position in Fig. 2;

Fig. 5 a to Fig. 5 d is the schematic cross-section of C1--C2 line of cut position in Fig. 2;

Fig. 6 is the schematic flow sheet of manufacture method in the first embodiment of the first technical scheme of tft array structure of the present invention;

Fig. 7, Fig. 8 a to Figure 20 a are that the manufacture method of tft array structure of the present invention is made the schematic diagram of tft array structure in the first embodiment of the first technical scheme;

Fig. 8 b to Figure 20 b is that the manufacture method of tft array structure of the present invention is made the schematic diagram of gate electrode terminal in the first embodiment of the first technical scheme;

Fig. 8 c, Figure 10 c, Figure 11 c, Figure 12 c, Figure 14 c, Figure 15 c and Figure 15 d, Figure 18 c and Figure 18 d are that the manufacture method of tft array structure of the present invention is made the schematic diagram in sweep trace district in the first embodiment of the first technical scheme;

Figure 21 is the schematic flow sheet of manufacture method in the second embodiment of the first technical scheme of tft array structure of the present invention;

Figure 22, Figure 23 a to Figure 34 a are that the manufacture method of tft array structure of the present invention is made the schematic diagram of tft array structure in the second embodiment of the first technical scheme;

Figure 23 b to Figure 34 b is that the manufacture method of tft array structure of the present invention is made the schematic diagram of gate electrode terminal in the second embodiment of the first technical scheme;

Figure 23 c, Figure 24 c and Figure 24 d, Figure 25 c and Figure 25 d, Figure 27 c and Figure 27 d, Figure 29 c and Figure 29 d, Figure 32 c and Figure 32 d are that the manufacture method of tft array structure of the present invention is made the schematic diagram in sweep trace district in the second embodiment of the first technical scheme;

Figure 35 is the schematic cross-section of A1--A2 line of cut position in the second technical scheme in Fig. 2;

Figure 36 is the schematic flow sheet of manufacture method in the second technical scheme of tft array structure of the present invention;

Figure 37 to Figure 45 is that the manufacture method of tft array structure of the present invention is made the schematic diagram of tft array structure in the second technical scheme.

Embodiment

The inventor finds, formed memory capacitance in the manufacturing process of existing tft array structure includes the storage medium of three layers or more multi-layered structure between upper and lower pole plate, and the capacitance stores ability of memory capacitance is less.

The inventor finds again, and in the manufacturing process of existing tft array structure, the amorphous silicon layer between viewing area data line and gate electrode line can not etch away, and causes to occur the cross-talk phenomenon between neighbor.

The inventor also finds, in the manufacturing process of existing tft array structure, utilizes common mask plate repeatedly to carry out the multiple etching processing step, and is difficult to even can not etch to bind the gate electrode terminal of driving circuit.

In view of this, the present inventor provides a kind of tft array structure and manufacture method thereof.

The first technical scheme:

See also Fig. 2 and Fig. 3, wherein Fig. 2 is the floor map of tft array structure provided by the invention; Fig. 3 be in Fig. 2 along the schematic cross-section of A1--A2 line of cut gained, it has comprised thin film transistor (TFT), and (Thin Film Transistors:TFT is hereinafter to be referred as TFT) structural area and memory capacitance district.In conjunction with Fig. 2 and Fig. 3, described tft array structure comprises: substrate 200, and described substrate 200 has first area 205 and second area 206, wherein will form the TFT structure on first area 205, will form memory capacitance on second area 206; The first insulation course 209, the zone on covered substrate 200 except first area 205 and second area 206; Be positioned at the TFT structure on first area 205, described TFT structure comprises gate electrode metal layer 201, grid electrode insulating layer 202, semiconductor layer 203, the ohmic contact layer 204 that is positioned on first area 205, and is positioned at source electrode metal layer 210a and drain electrode metal level 210b on ohmic contact layer 204 and the first insulation course 209; Has the raceway groove 211 that is positioned on first area 205 between source electrode metal layer 210a and drain electrode metal level 210b; Be positioned at gate electrode metal layer 201 and grid electrode insulating layer 202 on second area 206; The second insulation course 212 covers the grid electrode insulating layer 202 on source electrode metal layer 210a, raceway groove 211, drain electrode metal level 210b and second area 206; Via hole 213 blocks the second insulation course 212 and manifests drain electrode metal level 210b; Pixel electrode 214 covers the second insulation course 212, is connected with drain electrode metal level 210b by via hole 213; Pixel electrode 214 and gate electrode metal layer 201 consist of respectively the two poles of the earth of memory capacitance on second area 206, the grid electrode insulating layer 202 between gate electrode metal layer 201 and pixel electrode 214 and the second insulation course 212 consist of the storage medium of described memory capacitance.

Fig. 4 is the schematic cross-section of B1--B2 line of cut position gate electrode terminal in Fig. 2.As shown in Figure 4, described gate electrode terminal comprises: the gate electrode metal layer 201 on the 3rd zone 207 of covered substrate 200; Be positioned at the first insulation course 209 of gate electrode metal layer 201 periphery on the 3rd zone 207; Cover the second insulation course 212 of the first insulation course 209; Cover the pixel electrode 214 of the second insulation course 212 and gate electrode metal layer 201.

Fig. 5 a is along the schematic cross-section of C1--C2 line of cut gained, namely with the schematic cross-section in the sweep trace district of gate electrode metal floor one in Fig. 2.Described sweep trace district is specially the sweep trace part that is between adjacent two data lines (described data line and source-drain electrode metal level are one) in pixel cell.

As shown in Fig. 5 a, described sweep trace district comprises: the gate electrode metal floor 201 of covered substrate 200 and grid electrode insulating floor 202; Covering is positioned at semiconductor layer 203, ohmic contact layer 204 and the source-drain electrode metal level 210 of grid electrode insulating layer 202 periphery on the 4th zone 208; Cover the second insulation course 212 of grid electrode insulating layer 202 on source-drain electrode metal level 210 and the 4th zone 208.

Fig. 5 b to Fig. 5 d is along C1--C2 line of cut schematic cross-section in other embodiments in Fig. 2.

As shown in Fig. 5 b, similar with Fig. 5 a, described sweep trace district comprises: the gate electrode metal floor 201 of covered substrate 200 and grid electrode insulating floor 202; Cover semiconductor layer 203, ohmic contact layer 204 and the source-drain electrode metal level 210 of grid electrode insulating layer 202 periphery on the 4th zone 208; Cover the second insulation course 212 on the grid electrode insulating layer 202 on source-drain electrode metal level 210 and the 4th zone 208.

As shown in Fig. 5 c, described sweep trace district comprises: the gate electrode metal floor 301 of covered substrate 300 and grid electrode insulating floor 302; The first insulation course 309 of covering grid electrode insulation course 302; Covering is positioned on the 4th zone 308 the source-drain electrode metal level 310 of the first insulation course 309 peripheries; Cover the second insulation course 312 of the first insulation course 309 on source-drain electrode metal level 310 and the 4th zone 308.

As shown in Fig. 5 d, described sweep trace district comprises: the gate electrode metal floor 301 of covered substrate 300 and grid electrode insulating floor 302; Cover semiconductor layer 303 and the ohmic contact layer 304 of grid electrode insulating layer 302 periphery on the 4th zone 308; Cover the first insulation course 309 of grid electrode insulating layer 302 on the 4th zone 308; Cover the source-drain electrode metal level 310 of ohmic contact layer 304; Cover the second insulation course 312 of the first insulation course 309 on source-drain electrode metal level 310 and the 4th zone 308.

The first embodiment:

In one embodiment of the invention, provide a kind of manufacture method of tft array structure, as shown in Figure 6, comprise step:

S101 provides substrate, and described substrate has first area and second area;

S102 sequentially forms gate electrode metal layer, grid electrode insulating layer, semiconductor layer and ohmic contact layer on described substrate;

S103 utilizes mask plate, definition the first photoetching offset plate figure;

S104 take described the first photoetching offset plate figure as mask, removes ohmic contact layer, semiconductor layer, grid electrode insulating layer and gate electrode metal layer on the zone outside described first area and second area, and manifests described substrate;

S105 forms the first insulation course on the first area of described substrate and the zone outside second area;

S106 forms the source-drain electrode metal level on the ohmic contact layer on described the first insulation course and described first area, second area;

S107 utilizes half tone mask plate, definition the second photoetching offset plate figure;

S108, take described the second photoetching offset plate figure as mask, form the raceway groove that is positioned on the first area on described source-drain electrode metal level, described source-drain electrode metal level is blocked and forms source electrode metal layer and drain electrode metal level on the semiconductor layer on described the first insulation course and first area, to form thin-film transistor structure; Remove source-drain electrode metal level, ohmic contact layer and semiconductor layer on described second area, and manifest described grid electrode insulating layer;

S109 forms the second insulation course on described source electrode metal layer, raceway groove, drain electrode metal level and grid electrode insulating layer;

S110 forms via hole on described the second insulation course, described via hole blocks described the second insulation course and manifests described drain electrode metal level;

S111 forms pixel electrode on described the second insulation course, described pixel electrode is connected with described drain electrode metal level by described via hole; Described pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises grid electrode insulating layer and the second insulation course between described gate electrode metal layer and described pixel electrode.

Be elaborated below in conjunction with accompanying drawing.

At first execution in step S101, provide substrate 200 as shown in Figure 7, and substrate 200 has first area 205 and second area 206.In one embodiment of the invention, substrate 200 can adopt transparent glass substrate or quartz.

Then execution in step S102, sequentially form gate electrode metal layer 201, grid electrode insulating layer 202, semiconductor layer 203 and ohmic contact layer 204 on substrate 200.The structure of formation as shown in Fig. 8 a.

In addition, substrate 200 also comprises the gate electrode terminal with the 3rd zone 207.In step S102, for the gate electrode terminal, the gate electrode metal layer 201, grid electrode insulating layer 202, semiconductor layer 203 and the ohmic contact layer 204 that sequentially form on substrate 200 form the structure as shown in Fig. 8 b.

Have, substrate 200 also comprises the sweep trace district with the 4th zone 208 again.In step S102, for the sweep trace district, the gate electrode metal layer 201, grid electrode insulating layer 202, semiconductor layer 203 and the ohmic contact layer 204 that sequentially form on substrate 200 form the structure as shown in Fig. 8 c.

The thickness of gate electrode metal layer 201 is roughly 500 dusts～4000 dusts, and its material can be selected metal or its alloys such as Cr, W, Ti, Ta, Mo, Al or Cu.In one embodiment of the invention, the concrete grammar that forms gate electrode metal layer 201 can adopt physical gas-phase deposite method.

In one embodiment of the invention, the concrete grammar that forms grid electrode insulating layer 202, semiconductor layer 203 and ohmic contact layer 204 can adopt chemical gaseous phase depositing process, particularly, can be plasma reinforced chemical vapour deposition method (PECVD).Wherein, the thickness of grid electrode insulating layer 202 is 1000 dusts～4000 dusts, and its material can be selected oxide, nitride or oxynitrides, and corresponding reacting gas can be SiH ₄, NH ₃, N ₂Or SiH ₂Cl ₂, NH ₃, N ₂The thickness of semiconductor layer 203 and ohmic contact layer 204 is respectively 1000 dusts～2500 dusts and 300 dusts～600 dusts, and the reacting gas of semiconductor layer 203 and ohmic contact layer 204 correspondences can be SiH ₄, N ₂Or SiH ₂Cl ₂, N ₂Described semiconductor layer 203 is amorphous silicon (a-Si) layer.

Then execution in step S103, utilize mask plate, definition the first photoetching offset plate figure.In one embodiment of the invention, described mask plate can be common mask plate.

At ohmic contact layer 204 surface formation the first photoetching offset plate figures (not shown), concrete technology comprises: be coated with photoresist on ohmic contact layer 204, then by exposure, the figure on corresponding first area 205 and second area 206 on mask plate is transferred on photoresist, then utilized developer solution that the photoresist of corresponding site is removed to form and first area 205 and second area 206 graphs of a correspondence.

Follow execution in step S104, take described the first photoetching offset plate figure as mask, remove ohmic contact layer 204, semiconductor layer 203, grid electrode insulating layer 202 and gate electrode metal layer 201 on the zone outside first area 205 and second area 206, and the first area 205 and the ohmic contact layer 204 on second area 206, semiconductor layer 203, grid electrode insulating layer 202 and the gate electrode metal layer 201 that are coated with photoresist are being retained, and form the structure as shown in Fig. 9 a.

In addition, in step S104, utilize mask plate, definition the first photoetching offset plate figure.Take described the first photoetching offset plate figure as mask, remove ohmic contact layer 204, semiconductor layer 203, grid electrode insulating layer 202 and gate electrode metal layer 201 on the zone outside the 3rd zone 207, and manifest substrate 200; And retain in the 3rd zone 207, ohmic contact layer 204, semiconductor layer 203, grid electrode insulating layer 202 and gate electrode metal layer 201 are arranged.The structure of formation as shown in Fig. 9 b.

The removal of described ohmic contact layer 204, semiconductor layer 203, grid electrode insulating layer 202 and gate electrode metal layer 201 realizes by etching technics.Described etching technics can or be dry etching for known wet etching.In one embodiment of the invention, specifically comprise: at first, adopt dry etch process, etch away ohmic contact layer 204, semiconductor layer 203 and grid electrode insulating layer 202; Adopt again wet-etching technology, etch away described gate electrode metal layer 201 until manifest substrate 200.Wherein, the etching gas of ohmic contact layer 204, semiconductor layer 203 can be selected SF ₆/ Cl ₂Or SF ₆/ HCl, the etching gas of grid electrode insulating layer 202 can be selected SF ₆/ O ₂, Cl ₂/ O ₂Or HCl/O ₂, the etching gas of gate electrode metal layer 201 can be selected SF ₆/ O ₂Or Cl ₂/ O ₂Because described dry etch process and wet-etching technology are well known to those skilled in the art, therefore do not give unnecessary details at this.

Then execution in step S105 forms the first insulation course 209 on the first area 205 of substrate 200 and the zone outside second area 206.

In one embodiment of the invention, the first insulation course 209 can be organic film, adopts coating process to form.Specifically comprise: even coating organic film on the first area 205 of substrate 200 and the ohmic contact layer 204 on the zone outside second area 206 and first area 205 and second area 206 at first, this moment, the thickness of the organic film between first area 205 and second area 206 was greater than the summation of gate electrode metal layer 201, grid electrode insulating layer 202, semiconductor layer 203 and 204 4 layers of medium of ohmic contact layer; Described organic film is cured processing, and the structure of formation as shown in Figure 10 a is (in the structure of gate electrode terminal place's formation as shown in Figure 10 b; Form the structure as shown in Figure 10 c at place, sweep trace district); Then adopt cineration technics, remove certain thickness organic film until it is flushed with ohmic contact layer 204, to manifest ohmic contact layer 204, form the plane of planarization, consist of the first insulation course 209, the concrete structure as shown in Figure 11 a (form the structure as shown in Figure 11 b at gate electrode terminal place, form the structure as shown in Figure 11 c at place, sweep trace district).Because cineration technics is well known to those skilled in the art, therefore do not give unnecessary details at this.

In addition, in other embodiments, as long as described organic film can be got rid of segment thickness, described cineration technics also can be replaced by additive method, for example in other embodiments, can remove certain thickness organic film by the oxygen reactive ion etching process.

Then execution in step S106, form source-drain electrode metal level 210 on the first insulation course 209 and the formed planarized surface of ohmic contact layer 204, forms the structure as shown in Figure 12 a.

The source-drain electrode metal level 210 that forms in step S106 is at follow-up further formation source electrode metal layer and drain electrode metal level (specifically can see following description for details).The thickness of source-drain electrode metal level 210 is roughly 500 dusts～2500 dusts, and its material can be selected metal or its alloys such as Cr, W, Ti, Ta, Mo, Al or Cu.In one embodiment of the invention, the concrete grammar of formation source-drain electrode metal level 210 can be to adopt the method for sputter or thermal evaporation to deposit formation on substrate 200.

In addition, in step S106, for the gate electrode terminal, form source-drain electrode metal level 210 on the ohmic contact layer 204 on the first insulation course 209 and the 3rd zone 207, form the structure as shown in Figure 12 b.

Have again, in step S106, for the sweep trace district, form source-drain electrode metal level 210 on ohmic contact layer 204, form the structure as shown in Figure 12 c.

Then execution in step S107, utilize half tone mask plate 40, definition photoresist second graph.Described half tone mask plate 40 is divided into a plurality of sections, and in the present embodiment, described half tone mask plate 40 is divided into three sections, and described three sections have respectively different transmittances.In the present embodiment, half tone mask plate 40 in corresponding first area 205, second area 206 and other zones except first area 205, second area 206 have respectively different transmittances.

At source-drain electrode metal level 210 surface formation the second photoetching offset plate figures (not shown), concrete technology comprises: coating photoresist 41 on source-drain electrode metal level 210, then by exposure, the figure that defines on described half tone mask plate is transferred on photoresist 41, then utilized developer solution that the photoresist 41 of corresponding site is removed to form the second corresponding photoetching offset plate figure.In the present embodiment, in described photoresist image, the photoresist on corresponding first area 205 is partly removed, and the photoresist that reaches periphery on corresponding second area 206 is removed and manifests source-drain electrode metal level 210, forms the structure as shown in Figure 13 a.

Follow execution in step S108, as shown in Figure 17 a, take described the second photoetching offset plate figure as mask, forming the raceway groove 211 that is positioned on first area 205 on source-drain electrode metal level 210, so that source-drain electrode metal level 210 is blocked, thereby form source electrode metal layer 210a and drain electrode metal level 210b on the ohmic contact layer 204 on the first insulation course 209 and first area 205, thereby form thin-film transistor structure; Remove source-drain electrode metal level 210, ohmic contact layer 204 and semiconductor layer 203 on second area 206, and manifest grid electrode insulating layer 202.

Above-mentioned steps S108 can specifically be divided into step by step a plurality of.In one embodiment of the invention, specifically can comprise:

At first, take described the second photoetching offset plate figure as mask, remove on second area 206 and source-drain electrode metal level 210 that periphery manifests, and the source-drain electrode metal level 210 that is coated with photoresist 41 zones is being retained, and forms the structure as shown in Figure 14 a.

For the gate electrode terminal, remove the source-drain electrode metal level 210 on the ohmic contact layer 204 on the first insulation course 209 and the 3rd zone 207, form the structure as shown in Figure 14 b.

For the sweep trace district, utilize half tone mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, remove the source-drain electrode metal level 210 on the 4th zone 208, form the structure as shown in Figure 14 c.

The removal of described source-drain electrode metal level 210 realizes by etching technics.Described etching technics can or be dry etching for known wet etching.In one embodiment of the invention, specifically can adopt wet-etching technology, etch away source-drain electrode metal level 210 until manifest ohmic contact layer 204 under it.Wherein, the etching gas of source-drain electrode metal level 210 can be selected SF ₆/ O ₂Or Cl ₂/ O ₂Because described etching technics is well known to those skilled in the art, therefore do not give unnecessary details at this.

Then, remove ohmic contact layer 204 and semiconductor layer 203 on second area 206, form the structure as shown in Figure 15 a.

For the gate electrode terminal, remove ohmic contact layer 204 and semiconductor layer 203 on the 3rd zone 207, form the structure as shown in Figure 15 b.

For the sweep trace district, take source-drain electrode metal level 210 as mask, remove ohmic contact layer 204 and semiconductor layer 203 on the 4th zone 208, manifest grid electrode insulating layer 202, form the structure as shown in Figure 15 c.

In addition, for the sweep trace district, in another embodiment, take source-drain electrode metal level 210 as mask, remove ohmic contact layer 204 and the semiconductor layer 203 of part on the 4th zone 208, manifest the grid electrode insulating layer 202 of part, form the structure as shown in Figure 15 d.

The removal of described ohmic contact layer 204 and semiconductor layer 203 realizes by etching technics.Described etching technics can or be dry etching for known wet etching.In one embodiment of the invention, specifically can adopt dry etch process, etch away ohmic contact layer 204 and semiconductor layer 203 until manifest grid electrode insulating layer 202 under it, the etching gas of ohmic contact layer 204, semiconductor layer 203 can be selected SF ₆/ Cl ₂Or SF ₆/ HCl.

Then, remove the photoresist 41 on corresponding first area 205, manifest the source-drain electrode metal level 210 of part, form the structure as shown in Figure 16 a.

Then, take photoresist 41 as mask, remove on first area 205 source-drain electrode metal level 210 and under ohmic contact layer 204 and certain thickness semiconductor layer 203, blocked source-drain electrode metal level 210 and formed source electrode metal layer 210a and drain electrode metal level 210b, formed the structure as shown in Figure 17 a.

The removal of described source-drain electrode metal level 210, ohmic contact layer 204 and semiconductor layer 203 realizes by etching technics.Described etching technics can or be dry etching for known wet etching.In one embodiment of the invention, specifically can adopt dry etch process, etch away source-drain electrode metal level 210, ohmic contact layer 204 and certain thickness semiconductor layer 203, the etching gas of source-drain electrode metal level 210 can be selected SF ₆/ O ₂Or Cl ₂/ O ₂, the etching gas of ohmic contact layer 204, semiconductor layer 203 can be selected SF ₆/ Cl ₂Or SF ₆/ HCl.

In addition, in the present embodiment, semiconductor layer 203 is the thickness that has been etched away part, but not as limit, in other embodiments, also semiconductor layer 203 can be etched away fully.

Then execution in step S109, form the second insulation course 212 on source electrode metal layer 210a, raceway groove 211, drain electrode metal level 210b and grid electrode insulating layer 202, forms the structure as shown in Figure 18 a.

For the gate electrode terminal, form the second insulation course 212 on the grid electrode insulating layer 202 on the first insulation course 209 and the 3rd zone 207, form the structure as shown in Figure 18 b.

For the sweep trace district, form the second insulation course 212 on the grid electrode insulating layer 202 on source-drain electrode metal level 210 and the 4th zone 209, form the structure as shown in Figure 18 c.

In addition, for the sweep trace district, in another embodiment, form the second insulation course 212 on the ohmic contact layer 204 on source-drain electrode metal level 210 and the 4th zone 209 and grid electrode insulating layer 202, form the structure as shown in Figure 18 d.

As shown in Figure 18 c and Figure 18 d, owing to removing or part has been removed ohmic contact layer 204 and the semiconductor layer 203 in the sweep trace district between two data lines, making described two data lines not have electric current after applying varying voltage signal flows through between described two data lines, be also that sweep trace between described two data lines and described two data lines can equivalence be not a transistor arrangement, thereby reduced the probability that produces cross-talk between neighbor.

In one embodiment of the invention, the thickness of the second insulation course 212 is 700 dusts～2000 dusts, and its material can be oxide, nitride or oxynitrides, adopts chemical vapor deposition method to form, and corresponding reacting gas can be SiH ₄, NH ₃, N ₂Or SiH ₂Cl ₂, NH ₃, N ₂

Then execution in step S110, form via hole 213 on the second insulation course 212, and via hole 213 blocks the second insulation course 212 and manifests drain electrode metal level 210b it under, the structure of formation as shown in Figure 19 a.

Via hole 213 is to etch away the second insulation course 212 rear formation partly by etching technics.Described etching technics can or be dry etching for known wet etching.

In addition, at gate electrode terminal place, utilize mask plate, definition the 3rd photoetching offset plate figure (not shown); Take described the 3rd photoetching offset plate figure as mask, remove the second insulation course and grid electrode insulating layer on described the 3rd zone, and manifest described gate electrode metal layer.Concrete, by etching technics, etch away the second insulation course 212 and lower grid electrode insulating layer 202 thereof on the 3rd zone 207, and manifest gate electrode metal layer 201, form the gate electrode terminal vias as shown in Figure 19 b, to be used for externally connection.Etching gas can be selected SF ₆/ O ₂, Cl ₂/ O ₂Or HCl/O ₂

It should be noted that, due in step S110, as Figure 19 b, can form in the lump the gate electrode terminal vias when forming via hole 213, just can etch via hole for the gate electrode terminal of fixed drive IC circuit than increasing in the prior art one mask plate, the present invention does not need the processing step of independent etching gate electrode terminal vias of the prior art, thereby can simplify technique, reduction manufacturing cost.

Then execution in step S111, form pixel electrode 214 on the second insulation course 212, forms the structure as shown in Figure 20 a.As shown in Figure 20 a, the pixel electrode 214 of part is filled in via hole 213, is able to be connected with drain electrode metal level 210b by via hole 213.Pixel electrode 214 consists of the two poles of the earth of memory capacitance with gate electrode metal layer 201 on second area 206, described memory capacitance storage medium only comprises grid electrode insulating layer 202 and the second insulation course 212 between gate electrode metal layer 201 and pixel electrode 214.

For the gate electrode terminal, form pixel electrode 214 on the gate electrode metal layer 201 on the second insulation course 212 and the 3rd zone 207, simultaneously in order to the grill-protected electrode terminal, prevent that the gate electrode terminal from corroding because contacting with air, form the structure as shown in Figure 20 b.

In one embodiment of the invention, the concrete grammar that forms pixel electrode 214 comprises: at first, adopt physical gas-phase deposition forming transparency conducting layer on the second insulation course 212, and described transparency conducting layer is filled in via hole 213.The thickness of described transparency conducting layer is 300 dusts～600 dusts, and its material can be selected indium tin oxide or indium-zinc oxide.Then, form pixel electrode 214 by etching technics.In fact, the technique that forms transparency conducting layer also can adopt the method deposition of sputter or thermal evaporation to form, and does not repeat them here.

In above-mentioned steps S111, the pixel electrode 214 that forms is connected with drain electrode metal level 210b by via hole 213, during sweep signal TFT conducting that can be on the gate electrode metal layer, source electrode metal layer 210a is offered pixel electrode 214 through the data-signal that drain electrode metal level 210b conducts.

In addition, formed memory capacitance on corresponding second area 206, wherein, the pixel electrode 214 that is oppositely arranged and gate electrode metal layer 201 be respectively as the upper and lower pole plate of described memory capacitance, and the grid electrode insulating layer 202 between pixel electrode 214 and gate electrode metal layer 201 and the second insulation course 212 are as the storage medium of described memory capacitance.Described storage medium is the memory capacitance of two-layer structure, has larger capacitance stores ability with respect to the memory capacitance of three layers or more multi-layered medium of the prior art.

Each processing step by above-mentioned the first embodiment comes Application in manufacture in the tft array structure of liquid crystal indicator, utilizes the etching technics of half tone mask plate, can make the tft array structure with less etching technics step, can simplify technique and reduce costs.

Semiconductor layer and the ohmic contact layer in the sweep trace district between two data lines are partly or completely etched away, so that described two data lines are not at voltage simultaneously, not having electric current flows through between described two data lines, eliminate the cross-talk between pixel cell, improved image display effect.

The second embodiment:

In one embodiment of the invention, provide a kind of manufacture method of tft array structure, as shown in figure 21, comprise step:

S201 provides substrate, and described substrate has first area and second area;

S202 sequentially forms gate electrode metal layer, grid electrode insulating layer, semiconductor layer and ohmic contact layer on described substrate;

S203 utilizes half tone mask plate, definition the first photoetching offset plate figure;

S204 take described the first photoetching offset plate figure as mask, removes ohmic contact layer, semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part; Retain ohmic contact layer, semiconductor layer, grid electrode insulating layer and gate electrode metal layer on described first area; Retain grid electrode insulating layer and gate electrode metal layer on described second area;

S205 forms the first insulation course on the periphery of described first area and described second area;

S206 forms the source-drain electrode metal level on described first area and described the first insulation course;

S207 utilizes mask plate, definition the second photoetching offset plate figure;

S208, take described the second photoetching offset plate figure as mask, form the raceway groove that is positioned on the first area on described source-drain electrode metal level, described source-drain electrode metal level is blocked and forms source electrode metal layer and drain electrode metal level on the semiconductor layer on described the first insulation course and first area, to form thin-film transistor structure; Remove source-drain electrode metal level and the first insulation course on described second area, manifest described grid electrode insulating layer;

S209 forms the second insulation course on described source electrode metal layer, raceway groove, drain electrode metal level and grid electrode insulating layer;

S210 forms via hole on described the second insulation course, described via hole blocks described the second insulation course and manifests described drain electrode metal level;

S211 forms pixel electrode on described the second insulation course, described pixel electrode is connected with described drain electrode metal level by described via hole; Wherein said pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises described grid electrode insulating layer and described the second insulation course.

Be elaborated below in conjunction with accompanying drawing.

At first execution in step S201, provide substrate 300 as shown in figure 22, and substrate 300 has first area 305 and second area 306.In one embodiment of the invention, substrate 300 can adopt transparent glass substrate or quartz.

Then execution in step S202, sequentially form gate electrode metal layer 301, grid electrode insulating layer 302, semiconductor layer 303 and ohmic contact layer 304 on substrate 300.The structure of formation as shown in Figure 23 a.

In addition, in step S202, for the gate electrode terminal, the gate electrode metal layer 301, grid electrode insulating layer 302, semiconductor layer 303 and the ohmic contact layer 304 that sequentially form on substrate 300 form the structure as shown in Figure 23 b.

Have, in step S202, for the sweep trace district, the gate electrode metal layer 301, grid electrode insulating layer 302, semiconductor layer 303 and the ohmic contact layer 304 that sequentially form on substrate 300 form the structure as shown in Figure 23 c again.

The thickness of gate electrode metal layer 301 is roughly 500 dusts～4000 dusts, and its material can be selected metal or its alloys such as Cr, W, Ti, Ta, Mo, Al or Cu.In one embodiment of the invention, the concrete grammar that forms gate electrode metal layer 301 can adopt physical gas-phase deposite method.

In one embodiment of the invention, the concrete grammar that forms grid electrode insulating layer 302, semiconductor layer 303 and ohmic contact layer 304 can adopt chemical gaseous phase depositing process, particularly, can be that plasma reinforced chemical vapour deposition method (PECVD) deposition forms.Wherein, the thickness of grid electrode insulating layer 302 is 1000 dusts～4000 dusts, and its material can be selected oxide, nitride or oxynitrides, and corresponding reacting gas can be SiH ₄, NH ₃, N ₂Or SiH ₂Cl ₂, NH ₃, N ₂The thickness of semiconductor layer 303 and ohmic contact layer 304 is respectively 1000 dusts～2500 dusts and 300 dusts～600 dusts, and the reacting gas of semiconductor layer 303 and ohmic contact layer 304 correspondences can be SiH ₄, N ₂Or SiH ₂Cl ₂, N ₂Described semiconductor layer 303 is amorphous silicon (a-Si) layer.

Then execution in step S203, utilize half tone mask plate 40, definition the first photoetching offset plate figure.Described half tone mask plate 40 is divided into a plurality of sections, and in the present embodiment, described half tone mask plate 40 is divided into three sections, and described three sections have respectively different transmittances.In the present embodiment, described half tone mask plate 40 in corresponding first area 305, second area 306 and other zones except first area 305, second area 306 have respectively different transmittances.

At ohmic contact layer 304 surface formation photoetching offset plate figures, concrete technology comprises: coating photoresist 41 on ohmic contact layer 304, then by exposure, the figure that defines on described half tone mask plate is transferred on photoresist 41, then utilized developer solution that the photoresist 41 of corresponding site is removed to form corresponding photoetching offset plate figure.

Then execution in step S204, take described the first photoetching offset plate figure as mask, remove ohmic contact layer 304, semiconductor layer 303, grid electrode insulating layer 302 and gate electrode metal layer 301 on the zone outside first area 305 and second area 306; Retain ohmic contact layer 304, semiconductor layer 303, grid electrode insulating layer 302 and gate electrode metal layer 301 on first area 305; Remove ohmic contact layer 304, semiconductor layer 303 on second area 306, retain grid electrode insulating layer 302 and gate electrode metal layer 301 on second area 306.By step S204, form the structure as shown in Figure 24 a.

In addition, in step S203, for the gate electrode terminal, utilize half tone mask plate, definition the first photoetching offset plate figure; In step S204, take described the first photoetching offset plate figure as mask, remove ohmic contact layer 304, semiconductor layer 303, grid electrode insulating layer 302 and the gate electrode metal layer 301 of part, manifest substrate 300, and retain grid electrode insulating layer 301 and gate electrode metal layer 302 on the 3rd zone 307.The structure of formation as shown in Figure 24 b.

Have again, in step S204, utilize half tone mask plate, definition the first photoetching offset plate figure; Take described the first photoetching offset plate figure as mask, remove ohmic contact layer 304 and semiconductor layer 303.The structure of formation as shown in Figure 24 c.

In fact, for the sweep trace district, in another embodiment, in step S203, utilize half tone mask plate, definition the first photoetching offset plate figure; In step S204, take described the first photoetching offset plate figure as mask, remove ohmic contact layer 304 and semiconductor layer 303 on the 4th zone 308, and manifest grid electrode insulating layer 302.The structure of formation as shown in Figure 24 d.

The removal of described ohmic contact layer 304, semiconductor layer 303, grid electrode insulating layer 302 and gate electrode metal layer 301 realizes by etching technics.Described etching technics can or be dry etching for known wet etching.In one embodiment of the invention, specifically comprise: at first, adopt dry etch process, etch away ohmic contact layer 304, semiconductor layer 303 and grid electrode insulating layer 302; Adopt again wet-etching technology, etch away described gate electrode metal layer 301 until manifest substrate 300.Wherein, the etching gas of ohmic contact layer 304, semiconductor layer 303 can be selected SF6/Cl2 or SF ₆/ HCl, the etching gas of grid electrode insulating layer 302 can be selected SF ₆/ O ₂, Cl ₂/ O ₂Or HCl/O ₂, the etching gas of gate electrode metal layer 301 can be selected SF ₆/ O ₂Or Cl ₂/ O ₂Because described dry etch process and wet-etching technology are well known to those skilled in the art, therefore do not give unnecessary details at this.

Then execution in step S205 forms the first insulation course 309 on the periphery of the first area 305 of substrate 300 and second area 306, form the structure as shown in Figure 26 a.

In addition, in step S205, for the gate electrode terminal, form the first insulation course 309 on the grid electrode insulating layer 302 on the substrate 300 outside the 3rd zone 307 and the 3rd zone 307, form the structure as shown in Figure 26 b.

Have again, in step S205, for the sweep trace district, form the first insulation course 309 on grid electrode insulating layer 302, form the structure as shown in Figure 25 c.

For the sweep trace district, in another embodiment, in step S205, form the first insulation course 309 on the grid electrode insulating layer 302 on the 4th zone 308, form the structure as shown in Figure 25 d.

In one embodiment of the invention, the first insulation course 309 can be organic film, adopts coating process to form.Specifically comprise: at first at even coating organic film on the first area 305 of substrate 300 and the zone outside second area 306, ohmic contact layer 304 on first area 305 and on the ohmic contact layer 304 on second area 306, this moment, the thickness of the first insulation course 309 between first area 305 and second area 306 was greater than the summation of gate electrode metal layer 301, grid electrode insulating layer 302,

semiconductor layer

303 and 304 4 layers of medium of ohmic contact layer; Described organic film is cured processing, forms the structure (in the structure of gate electrode terminal place's formation as shown in Figure 25 b) as shown in Figure 25 a; Then adopt cineration technics, remove certain thickness organic film until make it flush to manifest ohmic contact layer 304 with ohmic contact layer 304 on first area 305, form the plane of planarization, specifically the structure as shown in Figure 26 a (in the structure of gate electrode terminal place's formation as shown in Figure 26 b).Because cineration technics is well known to those skilled in the art, therefore do not give unnecessary details at this.

In addition, in other embodiments, as long as organic film can be got rid of segment thickness, described cineration technics also can be replaced by additive method, for example in other embodiments, can remove certain thickness organic film by the oxygen reactive ion etching process.

Then execution in step S206, form source-drain electrode metal level 310 on the formed planarized surface of ohmic contact layer 304 on the first insulation course 309 and first area 305, forms the structure as shown in Figure 27 a.

In step S206, for the gate electrode terminal, form source-drain electrode metal level 310 on the first insulation course 309, form the structure as shown in Figure 27 b.

In step S206, for the sweep trace district, form source-drain electrode metal level 310 on the first insulation course 309, form the structure as shown in Figure 27 c.

For the sweep trace district, in another embodiment, in step S206, form source-drain electrode metal level 310 on the first insulation course 309 on ohmic contact layer 304 and the 4th zone 308, form the structure as shown in Figure 27 d.

The source-drain electrode metal level 310 that forms in step S206 is at follow-up further formation source electrode metal layer and drain electrode metal level.The thickness of source-drain electrode metal level 310 is roughly 500 dusts～2500 dusts, and its material can be selected metal or its alloys such as Cr, W, Ti, Ta, Mo, Al or Cu.In one embodiment of the invention, the concrete grammar of formation source-drain electrode metal level 310 can be to adopt the method for sputter or thermal evaporation to deposit formation on substrate 300.

Then execution in step S207, utilize mask plate, definition the second photoetching offset plate figure.In one embodiment of the invention, described mask plate is common mask plate.

At source-drain electrode metal level 310 surface formation photoetching offset plate figures (not shown), concrete technology comprises: coating photoresist 41 on source-drain electrode metal level 310, then by exposure, the figure that defines on mask plate is transferred on photoresist 41, then utilized developer solution that the photoresist 41 of corresponding site is removed to form graph of a correspondence.In the present embodiment, in described photoresist image, the photoresist 41 on corresponding first area 305 and second area 306 is removed and manifests source-drain electrode metal level 310, forms the structure as shown in Figure 28 a.And in the structure of gate electrode terminal place's formation as shown in Figure 28 b.

Follow execution in step S208, as shown in Figure 31 a, take described photoetching offset plate figure as mask, forming the raceway groove 311 that is positioned on first area 305 on source-drain electrode metal level 310, so that source-drain electrode metal level 310 is blocked, thereby form source electrode metal layer 310a and drain electrode metal level 310b on the ohmic contact layer 304 on the first insulation course 309 and first area 305, to form thin-film transistor structure; Remove source-drain electrode metal level 310 and the first insulation course 309 on second area 306, manifest grid electrode insulating layer 302.

Above-mentioned steps S208 can specifically be divided into step by step a plurality of.In one embodiment of the invention, specifically can comprise:

At first, take described the second photoetching offset plate figure as mask, remove the source-drain electrode metal level 310 that corresponding first area 305 manifests, be able to source-drain electrode metal level 310 is blocked and form source electrode metal layer 310a and drain electrode metal level 310b; And remove the source-drain electrode metal level 310 that corresponding second area 306 manifests and manifest the first insulation course 309 under it, form the structure as shown in Figure 29 a.

For the gate electrode terminal, remove source-drain electrode metal level 310, form the structure as shown in Figure 29 b.

For the sweep trace district, utilize mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, remove the source-drain electrode metal level 310 on the 4th zone 308, and manifest the first insulation course 309.The structure of formation as shown in Figure 29 c.

For the sweep trace district, in another embodiment, utilize mask plate, definition the second photoetching offset plate figure; Take described the second photoetching offset plate figure as mask, remove the source-drain electrode metal level 310 on the 4th zone 308, and manifest the first insulation course 309.The structure of formation as shown in Figure 29 d.

The removal of described source-drain electrode metal level 310 realizes by etching technics.Described etching technics can or be dry etching for known wet etching.In one embodiment of the invention, specifically can adopt wet-etching technology, etch away source-drain electrode metal level 310 until manifest ohmic contact layer 304 under it.Wherein, the etching gas of source-drain electrode metal level 310 can be selected SF ₆/ O ₂Or Cl ₂/ O ₂Because described etching technics is well known to those skilled in the art, therefore do not give unnecessary details at this.

Then, remove the first insulation course 309 that second area 306 places appear until manifest grid electrode insulating layer 302 it under, the structure of formation as shown in Figure 30 a.

For the gate electrode terminal, remove the first insulation course 309 of part, make the first insulation course 309 flush with grid electrode insulating layer 302 on the 3rd zone 307, the structure of formation as shown in Figure 30 b.

The removal of described the first insulation course 309 can be adopted cineration technics, but be not limited successively, in other embodiments, described cineration technics also can be replaced by additive method, for example in other embodiments, can remove certain thickness organic film by the oxygen reactive ion etching process.

Then, remove ohmic contact layer 304 and certain thickness semiconductor layer 303 that 305 places, corresponding first area appear, blocked source-drain electrode metal level 310 and formed source electrode metal layer 310a and drain electrode metal level 310b, formed the structure as shown in Figure 31 a.

The removal of described ohmic contact layer 304 and semiconductor layer 303 realizes by etching technics.Described etching technics can or be dry etching for known wet etching.In one embodiment of the invention, specifically can adopt dry etch process to etch away ohmic contact layer 304 and certain thickness semiconductor layer 303, the etching gas of ohmic contact layer 304 and semiconductor layer 303 can be selected SF ₆/ Cl ₂Or SF ₆/ HCl.

In the present embodiment, semiconductor layer 303 is the thickness that has been etched away part, but not as limit, in other embodiments, also semiconductor layer 303 can be etched away fully.

Then execution in step S209, remove photoresist 41, forms the second insulation course 312 on source electrode metal layer 310a, raceway groove 311, drain electrode metal level 310b and grid electrode insulating layer 302, forms the structure as shown in Figure 32 a.

For the gate electrode terminal, form the second insulation course 312 on the first insulation course 309 and grid electrode insulating layer 302, form the structure as shown in Figure 32 b.

For the sweep trace district, form the second insulation course 312 on the first insulation course 309 on source-drain electrode metal level 310 and the 4th zone 308, form the structure as shown in Figure 32 c.

For the sweep trace district, in another embodiment, form the second insulation course 312 on the first insulation course 309 on source-drain electrode metal level 310 and the 4th zone 308, form the structure as shown in Figure 32 d.

As shown in Figure 30 c and Figure 30 d, owing to removing or part has been removed ohmic contact layer 204 and the semiconductor layer 203 in the sweep trace district between two data lines, so that not having electric current after applying varying voltage signal, described two data lines do not flow through between described two data lines, be also that sweep trace between described two data lines and described two data lines can equivalence be not a transistor arrangement, thereby reduced the probability that produces cross-talk between neighbor, correspondingly improved image display effect.

In one embodiment of the invention, the thickness of the second insulation course 312 is 700 dusts～3000 dusts, and its material can be oxide, nitride or oxynitrides, adopts chemical vapor deposition method to form, and corresponding reacting gas can be SiH ₄, NH ₃, N ₂Or SiH ₂Cl ₂, NH ₃, N ₂

Then execution in step S210, form via hole 313 on the second insulation course 312, and via hole 313 blocks the second insulation course 312 and manifests drain electrode metal level 310b it under, the structure of formation as shown in Figure 33 a.

Via hole 313 is to etch away the second insulation course 312 rear formation partly by etching technics.Etching gas can be selected SF ₆/ O ₂, Cl ₂/ O ₂Or HCl/O ₂

For the gate electrode terminal, remove the second insulation course 312 and grid electrode insulating layer 302 on the 3rd zone 307, and manifest gate electrode metal layer 301, form the structure as shown in Figure 33 b.

It should be noted that, due in step S210, can form in the lump the gate electrode terminal vias when forming via hole 313, just can etch via hole for the gate electrode terminal of fixed drive IC circuit than increasing in the prior art one mask plate, the present invention does not need the processing step of independent etching gate electrode terminal vias of the prior art, thereby can simplify technique, reduction manufacturing cost.

Then execution in step S211, form pixel electrode 314 on the second insulation course 312, forms the structure as shown in Figure 34 a.As shown in Figure 34 a, the pixel electrode 214 of part is filled in via hole 213, is able to be connected with drain electrode metal level 210b by via hole 213.Pixel electrode 314 consists of the two poles of the earth of memory capacitance with gate electrode metal layer 301 on second area 306, the storage medium of described memory capacitance only comprises grid electrode insulating layer 302 and the second insulation course 312 between gate electrode metal layer 301 and pixel electrode 314.

For the gate electrode terminal, form pixel electrode 314 on the gate electrode metal layer 301 on the second insulation course 312 and the 3rd zone 307, form the structure as shown in Figure 34 b.

In one embodiment of the invention, the concrete grammar that forms pixel electrode 314 comprises: at first, adopt physical gas-phase deposition forming transparency conducting layer on the second insulation course 312 and via hole 313, the thickness of described transparency conducting layer is 300 dusts～600 dusts, and its material can be selected indium tin oxide or indium-zinc oxide; Then, form pixel electrode 314 by etching technics.In fact, the technique that forms transparency conducting layer also can adopt the method deposition of sputter or thermal evaporation to form, and does not repeat them here.

In above-mentioned steps S211, the pixel electrode 314 that forms is connected with drain electrode metal level 310b by via hole 313, source electrode metal layer 310a can be offered pixel electrode 314 through the data-signal that drain electrode metal level 310b conducts during sweep signal TFT conducting that can be on the gate electrode metal layer.

In addition, formed memory capacitance on corresponding second area 306, wherein, the pixel electrode 314 that is oppositely arranged and gate electrode metal layer 301 be respectively as the upper and lower pole plate of described memory capacitance, and the grid electrode insulating layer between pixel electrode 314 and gate electrode metal layer 301 and the second insulation course are as the storage medium of described memory capacitance.Described memory capacitance has larger capacitance stores ability with respect to the memory capacitance of three layers or more multi-layered medium of the prior art.

The second technical scheme:

See also Fig. 2 and Figure 35, Figure 35 wherein be in Fig. 2 along the schematic cross-section of A1--A2 line of cut gained, it has comprised thin film transistor (TFT), and (Thin Film Transistors:TFT is hereinafter to be referred as TFT) structural area and memory capacitance district.In conjunction with Fig. 2 and Figure 35, described tft array structure comprises: substrate 400, and described substrate 400 has first area 405 and second area 406, wherein will form the TFT structure on first area 405, will form memory capacitance on second area 406; The first insulation course 409, the zone on covered substrate 400 except first area 405 and second area 406; Be positioned at the TFT structure on first area 405, described TFT structure comprises gate electrode metal layer 401, grid electrode insulating layer 402, semiconductor layer 403, the ohmic contact layer 404 that is positioned on first area 405, and is positioned at source electrode metal layer 410a and drain electrode metal level 410b on ohmic contact layer 404 and the first insulation course 409; Has the raceway groove 411 that is positioned on first area 405 between source electrode metal layer 410a and drain electrode metal level 410b; Be positioned at gate electrode metal layer 401 and grid electrode insulating layer 402 on second area 406; The second insulation course 412 covers source electrode metal layer 410a, raceway groove 411, drain electrode metal level 410b and the first insulation course 409; Via hole 413 blocks the second insulation course 412 and manifests drain electrode metal level 410b; Pixel electrode 414 covers the second insulation course 412 and grid electrode insulating layer 402, and is connected with drain electrode metal level 410b by via hole 413; Pixel electrode 414 consists of respectively the two poles of the earth of memory capacitance with gate electrode metal layer 401 on second area 406, only comprise grid electrode insulating layer 402 between gate electrode metal layer 401 and pixel electrode 414, therefore, described memory capacitance just has the single storage medium for grid electrode insulating layer 402.

In actual applications, can be substantially similar with the manufacture method of Fig. 6 and tft array structure shown in Figure 21, Figure 36 has shown the manufacture method for the manufacture of the described tft array structure of Figure 35.What need to specify is, similar because of manufacturing process and the aforementioned techniques scheme in gate electrode terminal and sweep trace district, associated process steps can be with reference to the related content in the aforementioned techniques scheme, therefore do not repeat them here.

The manufacture method of described tft array structure comprises the following steps:

S301 provides substrate, and described substrate has first area and second area;

S302 sequentially forms gate electrode metal layer, grid electrode insulating layer, semiconductor layer and ohmic contact layer on described substrate;

S303 utilizes half tone mask plate, definition the first photoetching offset plate figure;

S304 take described the first photoetching offset plate figure as mask, removes ohmic contact layer, semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part; Retain ohmic contact layer, semiconductor layer, grid electrode insulating layer and gate electrode metal layer on described first area; Retain grid electrode insulating layer and gate electrode metal layer on described second area;

S305 forms the first insulation course on the periphery of described first area and described second area;

S306 forms the source-drain electrode metal level on described first area and described the first insulation course;

S307 utilizes mask plate, definition the second photoetching offset plate figure;

S308, take described the second photoetching offset plate figure as mask, form the raceway groove that is positioned on the first area on described source-drain electrode metal level, described source-drain electrode metal level is blocked and forms source electrode metal layer and drain electrode metal level on the semiconductor layer on described the first insulation course and first area, to form thin-film transistor structure; Remove source-drain electrode metal level and the first insulation course on described second area, manifest described grid electrode insulating layer;

S309 forms the second insulation course on described source electrode metal layer, raceway groove, drain electrode metal level and grid electrode insulating layer;

S310 forms via hole on described the second insulation course, described via hole blocks described the second insulation course and manifests described drain electrode metal level; Remove the second insulation course on the grid electrode insulating layer on described second area;

S311 forms pixel electrode on the grid electrode insulating layer on described the second insulation course and described second area, described pixel electrode is connected with described drain electrode metal level by described via hole; Wherein said pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises the grid electrode insulating layer between described gate electrode metal layer and described pixel electrode.

Be elaborated below in conjunction with accompanying drawing.

At first execution in step S301 and step S302, the substrate 400 that has on first area 405 and second area 406 is provided, sequentially form gate electrode metal layer 401, grid electrode insulating layer 402, semiconductor layer 403 and ohmic contact layer 404 on substrate 400, form structure as shown in figure 37.

Then execution in step S303, utilize half tone mask plate 40, definition the first photoetching offset plate figure.Described half tone mask plate 40 is divided into a plurality of sections, and in the present embodiment, described half tone mask plate 40 is divided into three sections, and described three sections have respectively different transmittances.In the present embodiment, described half tone mask plate 40 in corresponding first area 405, second area 406 and other zones except first area 405, second area 406 have respectively different transmittances.

At ohmic contact layer 404 surface formation the first photoetching offset plate figures, concrete technology comprises: coating photoresist 41 on ohmic contact layer 404, then by exposure, the figure that defines on described half tone mask plate is transferred on photoresist 41, then utilized developer solution that the photoresist 41 of corresponding site is removed to form corresponding photoetching offset plate figure.

Then execution in step S304, take described the first photoetching offset plate figure as mask, remove ohmic contact layer 404, semiconductor layer 403, grid electrode insulating layer 402 and gate electrode metal layer 401 on the zone outside first area 405 and second area 406; Retain ohmic contact layer 404, semiconductor layer 403, grid electrode insulating layer 402 and gate electrode metal layer 401 on first area 305; Remove ohmic contact layer 404, semiconductor layer 403 on second area 406, retain grid electrode insulating layer 402 and gate electrode metal layer 401 on second area 406.By step S304, form structure as shown in figure 38.

Follow execution in step S305, form the first insulation course 409 on the periphery of the first area 405 of substrate 400 and second area 406, make the ohmic contact layer on the first insulation course 409 and first area 405 form planarized surface, form structure as shown in figure 39.

Then execution in step S306, form source-drain electrode metal level 410 on formed planarized surface on the ohmic contact layer 404 on the first insulation course 409 and first area 405, forms structure as shown in figure 40.

Then execution in step S307, utilize mask plate, definition the second photoetching offset plate figure.In one embodiment of the invention, described mask plate is common mask plate.

At source-drain electrode metal level 410 surface formation the second photoetching offset plate figures, concrete technology comprises: coating photoresist 41 on source-drain electrode metal level 410, then by exposure, the figure that defines on mask plate is transferred on photoresist 41, then utilized developer solution that the photoresist 41 of corresponding site is removed to form graph of a correspondence.In the present embodiment, in described photoresist image, the photoresist 41 on corresponding first area 405 and second area 406 is removed and manifests source-drain electrode metal level 410, forms structure as shown in figure 41.

Follow execution in step S308, as shown in figure 42, take described the second photoetching offset plate figure as mask, forming the raceway groove 411 that is positioned on first area 405 on source-drain electrode metal level 410, so that source-drain electrode metal level 410 is blocked, thereby form source electrode metal layer 410a and drain electrode metal level 410b on the ohmic contact layer 404 on the first insulation course 409 and first area 405, to form thin-film transistor structure; Remove source-drain electrode metal level 410 and the first insulation course 409 on second area 406, manifest grid electrode insulating layer 402.

Then execution in step S309, remove photoresist 41, forms the second insulation course 412 on source electrode metal layer 410a, raceway groove 411, drain electrode metal level 410b and grid electrode insulating layer 402, forms structure as shown in figure 43.

Then execution in step S310, as shown in figure 44, form via hole 413 on the second insulation course 412, and via hole 413 blocks the second insulation course 412 and manifests drain electrode metal level 410b under it.In the present embodiment, via hole 313 is to etch away the second insulation course 312 rear formation partly by etching technics.

In addition, in step S310, also comprise and remove the second insulation course 412 on grid electrode insulating layer 402 on second area 406.In the present embodiment, removing the second insulation course 412 etches away by etching technics.

Then execution in step S311, form pixel electrode 414 on the grid electrode insulating layer 402 on the second insulation course 412 and second area 406, forms structure as shown in figure 45.As shown in figure 45, the pixel electrode 414 of part is filled in via hole 413, is able to be connected with drain electrode metal level 410b by via hole 413.Pixel electrode 414 consists of the two poles of the earth of memory capacitance with gate electrode metal layer 401 on second area 406, and only comprise grid electrode insulating layer 402 between pixel electrode 414 and gate electrode metal layer 401, therefore, the storage medium of described memory capacitance only comprises grid electrode insulating layer 402.Described memory capacitance has larger capacitance stores ability with respect to the memory capacitance of three layers or more multi-layered medium of the prior art.

Although oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.

Claims

1. a tft array structure, is characterized in that, comprising:

Substrate, described substrate has first area and second area;

The first insulation course covers the zone except first area and second area on described substrate;

Thin-film transistor structure comprises the gate electrode metal layer, grid electrode insulating layer and the semiconductor layer that are positioned on described first area, and is positioned at source electrode metal layer and drain electrode metal level on described semiconductor layer and the first insulation course; Has the raceway groove that is positioned on the first area between described source electrode metal layer and drain electrode metal level; Described the first insulation course does not cover described semiconductor layer, gate electrode metal layer, grid electrode insulating layer;

Be positioned at gate electrode metal layer and grid electrode insulating layer on described second area;

Also comprise:

The second insulation course covers the grid electrode insulating layer of described source electrode metal layer, raceway groove, drain electrode metal level, the first insulation course and described second area;

Pixel electrode covers described the second insulation course, and is connected with described drain electrode metal level;

2. tft array structure according to claim 1, is characterized in that, also comprises the via hole that is positioned at described the second insulation course and manifests described drain electrode metal level, and described pixel electrode is connected with described drain electrode metal level by described via hole.

3. tft array structure according to claim 1, is characterized in that, described substrate also has the 3rd zone, and described tft array structure also comprises the gate electrode terminal, and it comprises:

Cover the gate electrode metal layer on the 3rd zone of described substrate;

Be positioned at the first insulation course of the gate electrode metal layer periphery on described the 3rd zone;

Cover the second insulation course of described the first insulation course;

Cover the pixel electrode of described the second insulation course and described gate electrode metal layer.

4. tft array structure according to claim 1, is characterized in that, described substrate also has the 4th zone, and described tft array structure also comprises and the sweep trace district of gate electrode metal floor one, and it comprises:

Cover gate electrode metal layer and the grid electrode insulating layer of described substrate;

Cover semiconductor layer and the source-drain electrode metal level of the grid electrode insulating layer periphery on described the 4th zone;

Cover the second insulation course of the grid electrode insulating layer on described source-drain electrode metal level and described the 4th zone.

5. tft array structure according to claim 1, is characterized in that, also is coated with ohmic contact layer between described semiconductor layer and described source electrode metal layer, drain electrode metal level.

6. tft array structure according to claim 1, is characterized in that, described substrate also has the 4th zone, and described tft array structure also comprises and the sweep trace district of gate electrode metal floor one, and it comprises:

At least cover the first insulation course on described the 4th zone;

Cover the source-drain electrode metal level of the first insulation course periphery on described the 4th zone;

Cover the second insulation course of the first insulation course on described source-drain electrode metal level and described the 4th zone.

7. tft array structure according to claim 6, is characterized in that, also is coated with semiconductor layer and ohmic contact layer between described the first insulation course and described grid electrode insulating layer.

8. tft array structure according to claim 1, it is characterized in that, described gate electrode metal layer, source electrode metal layer and drain electrode metal level are the monofilm that is selected from Cr, W, Ti, Ta, Mo, Al or Cu, perhaps are selected from least two kinds of composite membranes that metal forms in Cr, W, Ti, Ta, Mo, Al or Cu.

9. tft array structure according to claim 1, is characterized in that, the material of described grid electrode insulating layer, the first insulation course and the second insulation course comprises oxide, nitride or oxides of nitrogen.

10. tft array structure according to claim 1, is characterized in that, the material of described pixel electrode comprises indium tin oxide or indium-zinc oxide.

11. a tft array structure is characterized in that, comprising:

Substrate, described substrate has first area and second area;

Thin-film transistor structure comprises the gate electrode metal layer, grid electrode insulating layer and the semiconductor layer that are positioned on described first area, and is positioned at source electrode metal layer and drain electrode metal level on described semiconductor layer and the first insulation course; Has the raceway groove that is positioned on the first area between described source electrode metal layer and drain electrode metal level; Described the first insulation course does not cover described semiconductor layer, gate metal layer, grid electrode insulating layer;

Also comprise:

Pixel electrode covers described grid electrode insulating layer, and is connected with described drain electrode metal level;

Described pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises the grid electrode insulating layer.

12. tft array structure according to claim 11 is characterized in that, also comprises the second insulation course that covers described source electrode metal layer, raceway groove and drain electrode metal level.

13. tft array structure according to claim 12 is characterized in that, also comprises the via hole that is positioned at described the second insulation course and manifests described drain electrode metal level, described pixel electrode is connected with described drain electrode metal level by described via hole.

14. tft array structure according to claim 11 is characterized in that described substrate also has the 3rd zone, described tft array structure also comprises the gate electrode terminal, and it comprises:

Cover the gate electrode metal layer on the 3rd zone of described substrate;

Cover the second insulation course of described the first insulation course;

15. tft array structure according to claim 11 is characterized in that described substrate also has the 4th zone, described tft array structure also comprises and the sweep trace district of gate electrode metal floor one, and it comprises:

16. tft array structure according to claim 11 is characterized in that, also is coated with ohmic contact layer between described semiconductor layer and described source electrode metal layer, drain electrode metal level.

17. tft array structure according to claim 11 is characterized in that described substrate also has the 4th zone, described tft array structure also comprises and the sweep trace district of gate electrode metal floor one, and it comprises:

At least cover the first insulation course on described the 4th zone;

18. tft array structure according to claim 17 is characterized in that, also is coated with semiconductor layer and ohmic contact layer between described the first insulation course and described grid electrode insulating layer.

19. tft array structure according to claim 11, it is characterized in that, described gate electrode metal layer, source electrode metal layer and drain electrode metal level are the monofilm that is selected from Cr, W, Ti, Ta, Mo, Al or Cu, perhaps are selected from least two kinds of composite membranes that metal forms in Cr, W, Ti, Ta, Mo, Al or Cu.

20. tft array structure according to claim 11 is characterized in that, the material of described grid electrode insulating layer, the first insulation course and the second insulation course comprises oxide, nitride or oxides of nitrogen.

21. tft array structure according to claim 11 is characterized in that the material of described pixel electrode comprises indium tin oxide or indium-zinc oxide.

22. the manufacture method of a tft array structure is characterized in that, comprising:

Substrate is provided, and described substrate has first area and second area;

Sequentially form gate electrode metal layer, grid electrode insulating layer and semiconductor layer on described substrate;

Utilize mask, definition the first photoetching offset plate figure;

Take described the first photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and gate electrode metal layer on the zone outside described first area and second area, and manifest described substrate;

First area and the zone outside second area at described substrate form the first insulation course;

Form the source-drain electrode metal level on described the first insulation course and semiconductor layer;

Utilize half tone mask plate, definition the second photoetching offset plate figure;

Take described the second photoetching offset plate figure as mask, form the raceway groove that is positioned at the first area on described source-drain electrode metal level, described source-drain electrode metal level is blocked and forms source electrode metal layer and drain electrode metal level on the semiconductor layer on described the first insulation course and first area, to form thin-film transistor structure;

Remove source-drain electrode metal level and semiconductor layer on described second area, and manifest described grid electrode insulating layer;

Form the second insulation course on described source electrode metal layer, raceway groove, drain electrode metal level and grid electrode insulating layer;

Form pixel electrode on described the second insulation course, described pixel electrode is connected with drain electrode; Described pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises grid electrode insulating layer and the second insulation course.

23. the manufacture method of tft array structure according to claim 22 is characterized in that, also is included in the step that forms ohmic contact layer between source-drain electrode metal level on the first area and semiconductor layer.

24. the manufacture method of tft array structure according to claim 22 is characterized in that, also is included in to form via hole on described the second insulation course so that the step that described pixel electrode is connected with described drain electrode metal level by described via hole.

25. the manufacture method of tft array structure according to claim 22 is characterized in that, take described the first photoetching offset plate figure as mask, the step of removing described semiconductor layer, grid electrode insulating layer and gate electrode metal layer specifically comprises:

Adopt dry etch process, etch away described semiconductor layer and grid electrode insulating layer;

Adopt wet-etching technology, etch away described gate electrode metal layer.

26. the manufacture method of tft array structure according to claim 22 is characterized in that, the step that forms the first insulation course is specially: at the periphery of described gate electrode metal layer, grid electrode insulating layer and semiconductor layer coating organic film; The unnecessary organic film that adopts cineration technics will protrude from described semiconductor layer is removed, and forms the first insulation course.

27. the manufacture method of tft array structure according to claim 22 is characterized in that, source-drain electrode metal level and semiconductor layer on the described second area of described removal, and the step that manifests described grid electrode insulating layer specifically comprises:

Adopt wet-etching technology, etch away the source-drain electrode metal level of part;

Adopt dry etch process, etch away the semiconductor layer of part.

28. the manufacture method of tft array structure according to claim 22 is characterized in that, described substrate also has the 3rd zone, and the manufacture method of described tft array structure also comprises the technique of making the gate electrode terminal, and described technique comprises:

Utilize mask plate, definition the first photoetching offset plate figure;

Take described the first photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and gate electrode metal layer outside the 3rd zone;

The periphery of the gate electrode metal layer on described the 3rd zone, grid electrode insulating layer and semiconductor layer forms the first insulation course;

Take described the second photoetching offset plate figure as mask, remove the semiconductor layer on the 3rd zone, and manifest described grid electrode insulating layer;

Form the second insulation course on the grid electrode insulating layer on described the first insulation course and described the 3rd zone;

Utilize mask plate, definition the 3rd photoetching offset plate figure;

Take described the 3rd photoetching offset plate figure as mask, remove the second insulation course and grid electrode insulating layer on described the 3rd zone, and manifest described gate electrode metal layer;

Form pixel electrode on the gate electrode metal layer on described the second insulation course and described the 3rd zone.

29. the manufacture method of tft array structure according to claim 22, it is characterized in that, described substrate also has the 4th zone, and the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises:

Sequentially form gate electrode metal layer, grid electrode insulating layer, semiconductor layer and source-drain electrode metal level on described substrate;

Utilize mask plate, definition the first photoetching offset plate figure;

Take described the first photoetching offset plate figure as mask, remove the source-drain electrode metal level on described the 4th zone;

Remove the semiconductor layer on the 4th zone, and manifest described grid electrode insulating layer;

Form the second insulation course on the grid electrode insulating layer on described source-drain electrode metal level and described the 4th zone.

30. the manufacture method of tft array structure according to claim 22, it is characterized in that, described substrate also has the 4th zone, and the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises:

Utilize mask plate, definition the first photoetching offset plate figure;

Remove the semiconductor layer of the 4th upper part in zone, and manifest the described grid electrode insulating layer of part;

Form the second insulation course on the semiconductor layer on described source-drain electrode metal level and described the 4th zone and grid electrode insulating layer.

31. the manufacture method of according to claim 29 or 30 described tft array structures is characterized in that, also is included in the step that forms ohmic contact layer between described source-drain electrode metal level and semiconductor layer.

32. the manufacture method of a tft array structure is characterized in that, comprising:

Substrate is provided, and described substrate has first area and second area;

Utilize half tone mask plate, definition the first photoetching offset plate figure;

Take described the first photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part; Retain semiconductor layer, grid electrode insulating layer and gate electrode metal layer on described first area; Retain grid electrode insulating layer and gate electrode metal layer on described second area;

Form the first insulation course on the periphery of described first area and described second area;

Form the source-drain electrode metal level on described first area and described the first insulation course;

Utilize mask plate, definition the second photoetching offset plate figure;

Take described the second photoetching offset plate figure as mask, form the raceway groove that is positioned on the first area on described source-drain electrode metal level, described source-drain electrode metal level is blocked and forms source electrode metal layer and drain electrode metal level on the semiconductor layer on described the first insulation course and first area, to form thin-film transistor structure;

Remove source-drain electrode metal level and the first insulation course on described second area, manifest described grid electrode insulating layer;

33. the manufacture method of tft array structure according to claim 32 is characterized in that, also is included in the step that forms ohmic contact layer between source-drain electrode metal level on the first area and semiconductor layer.

34. the manufacture method of tft array structure according to claim 32 is characterized in that, also is included in to form via hole on described the second insulation course so that the step that described pixel electrode is connected with described drain electrode metal level by described via hole.

35. the manufacture method of tft array structure according to claim 32 is characterized in that, the described step of removing semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part specifically comprises:

Adopt wet-etching technology, etch away described gate electrode metal layer.

36. the manufacture method of tft array structure according to claim 32 is characterized in that, the step of described formation the first insulation course is specially: at the periphery of described gate electrode metal layer, grid electrode insulating layer and semiconductor layer coating organic film; The unnecessary organic film that adopts cineration technics will protrude from described semiconductor layer is removed, and forms the first insulation course.

37. the manufacture method of tft array structure according to claim 32 is characterized in that, the step of described formation raceway groove is specially:

Adopt wet-etching technology, etch away the source-drain electrode metal level on described first area;

Adopt dry etch process, etch away the described semiconductor layer of segment thickness.

38. the manufacture method of tft array structure according to claim 32 is characterized in that, for second area, removes described source-drain electrode metal level and the first insulation course, and the step that manifests the grid electrode insulating layer specifically comprises:

Adopt wet-etching technology, etch away the source-drain electrode metal level on described second area;

Adopt cineration technics, ash melts the first insulation course on described second area.

39. the manufacture method of tft array structure according to claim 32 is characterized in that, described substrate also has the 3rd zone, and the manufacture method of described tft array structure also comprises the technique of making the gate electrode terminal, and described technique comprises:

Take described the first photoetching offset plate figure as mask, remove semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part; Retain grid electrode insulating layer and gate electrode metal layer on described the 3rd zone;

Form the first insulation course on the substrate outside described the 3rd zone and the grid electrode insulating layer on the 3rd zone;

Form the second insulation course on described the first insulation course and grid electrode insulating layer;

Utilize mask plate, definition the second photoetching offset plate figure;

Take described the second photoetching offset plate figure as mask, remove the second insulation course and grid electrode insulating layer on described the 3rd zone, and manifest described gate electrode metal layer;

40. the manufacture method of tft array structure according to claim 32, it is characterized in that, described substrate also has the 4th zone, and the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises:

Sequentially form gate electrode metal layer and grid electrode insulating layer on described substrate;

Sequentially form the first insulation course and source-drain electrode metal level on described grid electrode insulating layer;

Utilize mask plate, definition the second photoetching offset plate figure;

Take described the second photoetching offset plate figure as mask, remove the source-drain electrode metal level on described the 4th zone, and manifest described the first insulation course;

Form the second insulation course on the first insulation course on described source-drain electrode metal level and the 4th zone.

41. the manufacture method of tft array structure according to claim 32, it is characterized in that, described substrate also has the 4th zone, and the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises:

Take described the first photoetching offset plate figure as mask, remove the semiconductor layer on described the 4th zone, and manifest described grid electrode insulating layer;

Form the first insulation course on the grid electrode insulating layer on described the 4th zone;

Form the source-drain electrode metal level on the first insulation course on described semiconductor layer and described the 4th zone;

Utilize mask plate, definition the second photoetching offset plate figure;

Form the second insulation course on the first insulation course on described source-drain electrode metal level and described the 4th zone.

42. the manufacture method of described tft array structure, is characterized in that according to claim 41, also is included in the step that forms ohmic contact layer between described the first insulation course and semiconductor layer.

43. the manufacture method of a tft array structure is characterized in that, comprising:

Substrate is provided, and described substrate has first area and second area;

Utilize mask plate, definition the second photoetching offset plate figure;

Form pixel electrode on described grid electrode insulating layer, described pixel electrode is connected with drain electrode; Described pixel electrode and described gate electrode metal layer consist of the two poles of the earth of memory capacitance on second area, the storage medium of described memory capacitance only comprises the grid electrode insulating layer.

44. the manufacture method of described tft array structure, is characterized in that according to claim 43, also is included in the step that forms ohmic contact layer between source-drain electrode metal level on the first area and semiconductor layer.

45. the manufacture method of described tft array structure according to claim 43, it is characterized in that, source-drain electrode metal level on the described second area of described removal and the first insulation course, and after manifesting the step of described grid electrode insulating layer, also be included in the step that forms the second insulation course on described source electrode metal layer, raceway groove and drain electrode metal level.

46. the manufacture method of described tft array structure, is characterized in that according to claim 45, also is included in to form via hole on described the second insulation course so that the step that described pixel electrode is connected with described drain electrode metal level by described via hole.

47. the manufacture method of described tft array structure, is characterized in that according to claim 43, the described step of removing semiconductor layer, grid electrode insulating layer and the gate electrode metal layer of part specifically comprises:

Adopt wet-etching technology, etch away described gate electrode metal layer.

48. the manufacture method of described tft array structure, is characterized in that according to claim 43, the step of described formation the first insulation course is specially: at the periphery of described gate electrode metal layer, grid electrode insulating layer and semiconductor layer coating organic film; The unnecessary organic film that adopts cineration technics will protrude from described semiconductor layer is removed, and forms the first insulation course.

49. the manufacture method of described tft array structure, is characterized in that according to claim 43, the step of described formation raceway groove is specially:

50. the manufacture method of described tft array structure, is characterized in that according to claim 43, for second area, removes described source-drain electrode metal level and the first insulation course, and the step that manifests the grid electrode insulating layer specifically comprises:

51. the manufacture method of described tft array structure, is characterized in that according to claim 43, described substrate also has the 3rd zone, and the manufacture method of described tft array structure also comprises the technique of making the gate electrode terminal, and described technique comprises:

Utilize mask plate, definition the second photoetching offset plate figure;

52. the manufacture method of described tft array structure according to claim 43, it is characterized in that, described substrate also has the 4th zone, and the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises:

Utilize mask plate, definition the second photoetching offset plate figure;

53. the manufacture method of described tft array structure according to claim 43, it is characterized in that, described substrate also has the 4th zone, and the manufacture method of described tft array structure also comprises the technique made from the sweep trace district of gate electrode metal floor one, and described technique comprises:

Utilize mask plate, definition the second photoetching offset plate figure;

54. the manufacture method of 3 described tft array structures, is characterized in that according to claim 5, also is included in the step that forms ohmic contact layer between described the first insulation course and semiconductor layer.