CN102013796B - Detection circuit and detection method for anti-oscillation asynchronous boosting type voltage converter - Google Patents
Detection circuit and detection method for anti-oscillation asynchronous boosting type voltage converter Download PDFInfo
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- CN102013796B CN102013796B CN 201010284789 CN201010284789A CN102013796B CN 102013796 B CN102013796 B CN 102013796B CN 201010284789 CN201010284789 CN 201010284789 CN 201010284789 A CN201010284789 A CN 201010284789A CN 102013796 B CN102013796 B CN 102013796B
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Abstract
The invention relates to a detection circuit and detection method for an anti-oscillation asynchronous boosting type voltage converter. The voltage converter comprises at least one switch which is connected with a node and controlled by a first signal and switched to convert input voltage into output voltage. The detection circuit comprises a comparator and a logic circuit, wherein a second signal is produced by the comparator when voltage on the node reaches a critical value, and a detection signal is produced by the logic circuit according to the first signal and the second signal. The detection method comprises the following steps of: (1) detecting voltage on the node; (2) producing a second signal when voltage on the node reaches a critical value; and (3) producing a detection signal according to the first signal and the second signal.
Description
Technical field
The present invention relates to a kind of asynchronous pressure boosting type electric voltage converter, relate in particular to a kind of circuit for detecting and method for detecting thereof that is applied in the asynchronous pressure boosting type electric voltage converter of resistant and oscillation resistant.
Background technology
Fig. 1 is shown as traditional asynchronous pressure boosting type electric voltage converter 100, wherein inductance L 1 is connected between input voltage VIN and node LX, switch 104 is connected between node LX and ground connection GND, diode D1 is connected between node LX and output VOUT, capacitor C OUT connects output VOUT, and controller 102 output one pulse-width modulation signal PWM diverter switches 104 are to be converted to input voltage VIN output voltage VO UT.In controller 102, resistance R 1 and R2 pressure-dividing output voltage VOUT produce feedback voltage VFB, error amplifier 114 produces error signal EA according to reference voltage VREF and feedback voltage VFB, comparator 110 produces signal COMP according to error signal EA and sawtooth signal RAMP, trigger 108 according to signal COMP and from the frequency CLK of oscillator 106 produce pulse-width modulation signal PWM through driver 112 diverter switches 104 to produce inductive current IL1.
Fig. 2 is the oscillogram of signal in Fig. 1, and wherein waveform 150 is pulse-width modulation signal PWM, and waveform 152 is the voltage on node LX, and waveform 154 is inductive current IL1.With reference to Fig. 2, during the work period of pulse-width modulation signal PWM, switch 104 is opened (turn on), and inductive current IL1 rises, when pulse-width modulation signal PWM transfers low level to, switch 104 cuts out (turn off), inductive current IL1 begins to descend, and the voltage on node LX is drawn high, then, form oscillating circuit and produce vibration when inductive current IL1 is discharged to the parasitic capacitance that makes on inductance and diode D1 and node LX, enclose the part of coming as dotted line in waveform 152 and 154.
Fig. 3 is waveform 152 and 154 partial enlarged drawing in Fig. 2.Fig. 4 to Fig. 6 is in order to the schematic diagram that discharges and recharges of duration of oscillation inductance L 1 to be described.with reference to Fig. 3 to Fig. 6, when pulse-width modulation signal PWM transfers low level to, switch 104 cuts out, inductive current IL1 begins to descend, and the voltage on node LX raises, when inductive current IL1 is down to 0, as shown in time t1, voltage on node LX begins to descend, and the parasitic capacitance CD on diode D1 and node LX and CP are to inductance L 1 charging, as shown in Figure 4, when time t2, voltage on node LX equals input voltage VIN, and inductive current IL1 also reaches valley, then, voltage on node LX is continuous decrease again, until during the low critical value of the voltage ratio ground connection GND on node LX, the substrate diode of switch 104 (body diode) 116 conductings, as shown in time t3, this moment, inductive current IL1 flowed to inductance L 1 by ground connection GND, as shown in Figure 5, and the voltage on node LX will be limited in certain value by substrate diode 116, when inductive current IL1 rises to greater than 0 the time, as shown in time t4, the substrate diode 116 of switch 104 is closed, and inductance L 1 begins parasitic capacitance CD and CP discharge, as shown in Figure 6, at this moment, voltage on node LX begins to rise until inductive current IL1 repeats Fig. 4 to the step that discharges and recharges shown in Figure 6 more again after 0, as shown in time t5.As previously mentioned, the vibration of inductive current IL1 will cause the also and then vibration of voltage on node LX, thereby produce input noise, output noise and electromagnetic interference (Electro Magnetic Interference; The generation of problem such as EMI).
Summary of the invention
Purpose of the present invention is to propose a kind of asynchronous pressure boosting type electric voltage converter and resistant and oscillation resistant method thereof of resistant and oscillation resistant, can prevent the generation of input noise, output noise and electromagnetic interference by above-mentioned asynchronous pressure boosting type electric voltage converter and resistant and oscillation resistant method thereof.
For achieving the above object, the invention provides a kind of asynchronous pressure boosting type electric voltage converter of resistant and oscillation resistant, it comprises that an inductance is connected between one first voltage and a node, one switch is connected between this node and a second voltage and is controlled by a first signal, one diode is connected between the output of this node and this transducer, and a bypass resistance is connected between this first voltage and node.A kind of resistant and oscillation resistant method comprises voltage or this first signal on this node of detecting comes the voltage on decision node whether to vibrate, when vibration occurs in the voltage on this node, producing a secondary signal makes this bypass resistance form a bypass path, to suppress the vibration of voltage on this node, make the voltage on this node maintain certain value.
Another program of the present invention is to provide a kind of resistant and oscillation resistant method of asynchronous pressure boosting type electric voltage converter, described transducer comprises an inductance and is connected between one first voltage and a node, one switch is connected between this node and a second voltage, switch in response to a control signal, and one diode be connected between the output of this node and this transducer, the method comprises the following steps: that (1) judges whether the voltage on this node vibrates; And (2) voltage on this node forms a bypass path to stablize the voltage on this node when vibration occurring between this first voltage and node.
Another scheme of the present invention is to provide a kind of circuit for detecting that is applied in electric pressure converter, described electric pressure converter comprises that at least one switch sees through a node and connects an inductance, this switch is controlled by a first signal and switches to control the inductive current that flows through this inductance and transfer an input voltage to an output voltage, this circuit for detecting comprises: a comparator produces a secondary signal when voltage on this node reaches a critical value; One logical circuit produces a detection signal according to this first signal and secondary signal; And a bypass resistance, this detection signal drives this bypass resistance to form a bypass path between this input voltage and this node.
Another scheme of the present invention is to provide a kind of method for detecting that is applied in electric pressure converter, described electric pressure converter comprises that at least one switch sees through a node and connects an inductance, this switch is controlled by a first signal and switches to control the inductive current that flows through this inductance and transfer an input voltage to an output voltage, and the method comprises the following steps: that (1) detect the voltage on this node; Produce a secondary signal when (2) voltage on this node reaches a critical value; (3) produce a detection signal according to this first signal and secondary signal; And (4) utilize this detection signal, makes the bypass resistance conducting between this input voltage and this node form a bypass path.
The present invention makes it compared with prior art owing to having adopted above-mentioned technical scheme, has following advantage and good effect: the present invention can prevent the generation of input noise, output noise and electromagnetic interference.
Description of drawings
Fig. 1 is traditional asynchronous pressure boosting type electric voltage converter schematic diagram;
Fig. 2 is the oscillogram of signal in Fig. 1;
Fig. 3 is waveform 152 and 154 partial enlarged drawing in Fig. 2;
Fig. 4 shows the situation schematic diagram that parasitic capacitance CD and CP charge to inductance L 1;
Situation schematic diagram when Fig. 5 shows 116 conducting of substrate diode;
Fig. 6 shows the situation schematic diagram that parasitic capacitance CD and CP discharge to inductance L 1;
Fig. 7 is the embodiments of the invention schematic diagram;
Fig. 8 is the first embodiment of electric charge bypass resistance 202 in Fig. 7;
Fig. 9 is the second embodiment of electric charge bypass resistance 202 in Fig. 7;
Figure 10 is the 3rd embodiment of electric charge bypass resistance 202 in Fig. 7;
Figure 11 is the 4th embodiment of electric charge bypass resistance 202 in Fig. 7;
Figure 12 is the 5th embodiment of electric charge bypass resistance 202 in Fig. 7;
Figure 13 is the first embodiment of circuit for detecting 203 in Fig. 7;
Figure 14 is the oscillogram of signal in Figure 13;
Figure 15 is the second embodiment of circuit for detecting 203 in Fig. 7;
Figure 16 is the oscillogram of signal in Figure 15;
Figure 17 is the 3rd embodiment of circuit for detecting 203 in Fig. 7;
Figure 18 is the oscillogram of signal in Figure 17; And
Figure 19 is the another kind of embodiment that produces detection signal Sc.
Embodiment
Be described in further detail below with reference to asynchronous pressure boosting type electric voltage converter and the resistant and oscillation resistant method thereof of accompanying drawing to resistant and oscillation resistant of the present invention.
Fig. 7 is embodiments of the invention, in asynchronous pressure boosting type electric voltage converter 200, inductance L 1 is connected between input voltage VIN and node LX, nmos pass transistor N1 is connected to and is controlled by pulse-width modulation signal PWM between node LX and ground connection GND, diode D1 is connected between node LX and output VOUT, capacitor C D is the parasitic capacitance of diode D1, capacitor C P is the parasitic capacitance on node LX, electric charge bypass resistance 202 and inductance L 1 are connected in parallel between input voltage VIN and node LX, and the voltage on circuit for detecting 203 detecting node LX is to produce detection signal Sc.When vibration appears in the voltage on node LX, circuit for detecting 203 will produce detection signal Sc and make electric charge bypass resistance 202 formation one bypass path, and then make voltage on node LX maintain the level of input voltage VIN.
Fig. 8 is the first embodiment of electric charge bypass resistance 202 in Fig. 7, and it comprises that a switch 204 is controlled by detection signal Sc, when switch 204 is opened (turn on), will form a two-way bypass path.Fig. 9 is the second embodiment of electric charge bypass resistance 202 in Fig. 7, it comprises that PMOS transistor 206 and 208 is connected between input voltage VIN and node LX, and have separately substrate diode 210 and 212, a plurality of diode D2, D3 and D4 are connected between the gate of node LX and transistor 208, resistance R 1 and a plurality of diode D2, D3 and D4 are in parallel, switch 214 is connected between the gate and current source 216 of transistor 208, wherein resistance R 1 is used for voltage on pull-up transistor 208 gates to close transistor 208, diode D2, D3 and D4 are used for the limiting voltage on transistor 208 gates in the voltage range that gate can bear, 216 of current sources are to open transistor 208.In this embodiment, because the voltage on node LX may be higher than input voltage VIN, as shown in the waveform 152 of Fig. 2, therefore the transistor 208 of connected node LX is high potential assembly, in addition, form bypass path because of substrate diode 210 and 212 conductings in order to prevent from all closing (turn off) at transistor 206 and 208, therefore substrate diode 210 and 212 is arranged with back-to-back form.when signal Sc is high levle, transistor 208 is opened, Simultaneous Switching 214 is also opened the gate that makes transistor 208 and is connected to current source 216, thereby make transistor 208 also open to form bypass path, at this moment, transistor 208 and current source 216 can equivalence be considered as a current mirror, transistor 206 can be considered a resistance, transistor 208 can be considered a current source, when the voltage on node LX during greater than input voltage VIN, electric current on bypass path flows to input voltage VIN by node LX through transistor 208, when the voltage on node LX during less than input voltage VIN, electric current flows to node LX by input voltage VIN through the substrate diode 212 of transistor 208.
Figure 10 is the 3rd embodiment of electric charge bypass resistance 202 in Fig. 7, the PMOS transistor 218 and the nmos pass transistor 220 that wherein are connected between input voltage VIN and node LX have respectively substrate diode 222 and 224, and charge pump 226 produces voltage V1 switching transistor 220 according to detection signal Sc.when vibration appears in the voltage on node LX, detection signal Sc transfers high levle to open transistor 218, after transistor 218 is opened, voltage on transistor 220 source electrodes equals input voltage VIN, therefore need charge pump 226 to provide higher than the voltage V1 of input voltage VIN to the gate of transistor 220 slightly to open transistor 220, this moment, transistor 218 can be considered a resistance, transistor 220 can be considered a current source, when the voltage on node LX during greater than input voltage VIN, electric current on bypass path flows to input voltage VIN by node LX through transistor 220, when the voltage on node LX during less than input voltage VIN, electric current flows to node LX by input voltage VIN through the substrate diode 224 of transistor 220.In this embodiment, transistor 220 is also high potential assembly, and substrate diode 222 and 224 is also arranged in back-to-back mode.
Figure 11 is the 4th embodiment of electric charge bypass resistance 202 in Fig. 7, it comprises that PMOS transistor 228 and vague and general type nmos pass transistor 230 are connected between input voltage VIN and node LX, be controlled by detection signal Sc, transistor 228 and 230 respectively has a substrate diode 232 and 234.When vibration occured the voltage on node LX, detection signal Sc transferred high levle to and forms a two-way bypass path to open transistor 228 and 230, and then makes the voltage on node LX maintain input voltage VIN.Furthermore, when signal Sc is high levle, transistor 228 and 230 is opened, this moment, transistor 228 can be considered a resistance, and transistor 230 can be considered a current source, and during greater than input voltage VIN, the electric current on bypass path flows to input voltage VIN by node LX through transistor 230 when the voltage on node LX, during less than input voltage VIN, electric current flows to node LX by input voltage VIN through the substrate diode 234 of transistor 230 when the voltage on node LX.In this embodiment, transistor 230 is high potential assembly, and substrate diode 232 and 234 is arranged in back-to-back mode.
Figure 12 is the 5th embodiment of electric charge bypass resistance 202 in Fig. 7, and it comprises that PMOS transistor 236 and diode 240 are connected between input voltage VIN and node LX.When the voltage oscillation on node LX, detection signal Sc transfers high levle to open transistor 236 to form a unidirectional bypass path, and this moment, transistor 236 can be considered a resistance.During greater than the voltage on node LX, electric current flows to node LX from input voltage VIN through diode 240 when input voltage VIN.Transistor 236 has a substrate diode 238 to be arranged in back-to-back mode with diode 240, to prevent forming bypass path because of substrate diode 238 when transistor 236 is closed.In other embodiments, diode 240 can replace with transistorized substrate diode.
Figure 13 is the first embodiment of circuit for detecting 203 in Fig. 7, the isolated circuit 300 of its mesohigh is connected between node LX and comparator 304, in order to isolated high pressure, comparator 304 produces signal ck according to the voltage on node LX, or door 308 is according to pulse-width modulation signal PWM and in order to the signal EN output signal S1 of activation circuit for detecting 203, PMOS transistor 310 is connected between input voltage VIN and transistor 306, be controlled by detection signal Sc, nmos pass transistor 312 is connected between the output and ground connection GND of comparator 304, be controlled by detection signal Sc, trigger 314 produces detection signal Sc according to signal ck and S1.the isolated circuit 300 of high pressure comprises that nmos pass transistor 302 is connected between the gate of PMOS transistor 306 in node LX and comparator 304, and diode Dclamp is connected between the gate and source electrode of transistor 302, wherein transistor 302 is high potential assembly, when transistor 310 is opened, voltage on transistor 306 source electrodes equals input voltage VIN, according to transistorized characteristic as can be known, when the gate of transistor 306 and the pressure reduction between source electrode during less than the critical voltage VTP of transistor 306, transistor 306 opens to produce signal ck, therefore when the voltage on node LX during less than voltage Vr=(VIN-VTP), transistor 306 will be opened.
Figure 14 is the oscillogram of signal in Figure 13, and wherein waveform 400 is pulse-width modulation signal PWM, and waveform 402 is the voltage on node LX, and waveform 404 is signal ck, and waveform 406 is detection signal Sc.with reference to Fig. 7, Figure 13 and Figure 14, when time t1, pulse-width modulation signal PWM transfers high levle to open transistor N1, voltage on node LX is lower than voltage Vr at this moment, therefore signal ck transfers high levle to, pulse-width modulation signal PWM is high levle again, therefore trigger 314 produces the detection signal Sc of low level, after transistor N1 closes, voltage on node LX is drawn high and is surpassed voltage Vr, as time t2, therefore signal ck also transfers low level to, when if the voltage on node LX is again lower than voltage Vr afterwards, as time t3, transistor 306 is opened so that signal ck transfers high levle to, because pulse-width modulation signal PWM at this moment is low level, therefore trigger 314 produces the detection signal Sc of high levle so that electric charge bypass resistance 202 forms a bypass path, and then make voltage on node LX maintain the level of input voltage VIN, as shown in waveform 402.
Figure 15 is the second embodiment of circuit for detecting 203 in Fig. 7, the isolated circuit 500 of its mesohigh is connected between node LX and comparator 504, in order to isolated high pressure, it comprises high potential assembly nmos pass transistor 502 and diode Dclamp, diode Dclamp is connected between the gate and source electrode of transistor 502, comparator 504 comprises PMOS transistor 506, the gate of transistor 506 is connected to node LX through transistor 502, source electrode is connected to input voltage VIN through PMOS transistor 510, when transistor 502 and 510 is opened, the gate of transistor 506 and source electrode be connected node LX and input voltage VIN respectively, according to transistor characteristic, when the voltage on node LX during lower than voltage Vr=(VIN-VTP), PMOS transistor 506 opens to produce the signal ck of high levle, the nmos pass transistor 512 that is connected between comparator 504 outputs and ground connection GND is controlled by detection signal Sc, when transistor 512 is opened, signal ck will be pulled to low level, or door 508 produces signal S1 according to pulse-width modulation signal PWM and signal EN, two digit counter 514 count signal ck produce detection signal Sc.
Figure 16 is the oscillogram of signal in Figure 15, and wherein waveform 600 is pulse-width modulation signal PWM, and waveform 602 is the voltage on node LX, and waveform 604 is signal ck, and waveform 606 is detection signal Sc.with reference to Fig. 7, Figure 15 and Figure 16, when time t1, pulse-width modulation signal PWM transfers low level to, make counter 514 beginning count signal ck, for fear of misoperation, therefore counter 514 is detecting signal ck when occurring for the first time, do not produce detection signal Sc, as shown in time t1, then, when the voltage on node LX produces signal ck lower than voltage Vr again, as time t2, counter 514 produces detection signal Sc so that electric charge bypass resistance 202 forms a bypass path, and then make voltage on node LX maintain the level of input voltage VIN, as shown in waveform 602.In this embodiment, produce detection signal Sc when secondary occurring for setting signal ck, but in other embodiments, can change as required the number of times of counting.
Figure 13 and circuit for detecting 203 shown in Figure 15 can use with electric charge bypass resistance 202 collocation of Fig. 8, Fig. 9, Figure 10, Figure 11 and Figure 12.
Figure 17 is the 3rd embodiment of circuit for detecting 203 in Fig. 7, the isolated circuit 700 of its mesohigh is connected between node LX and comparator 704, in order to isolated high pressure, the isolated circuit 700 of high pressure comprises high potential assembly NOMOS transistor 702 and diode Dclamp, transistor 702 is connected between node LX and comparator 704, diode Dclamp is connected between the gate and source electrode of transistor 702, comparator 704 judges according to the voltage on node LX whether transistor N1 closes generation signal Sc, or door 706 produces signal S1 according to pulse-width modulation signal PWM and signal EN, produce a signal to trigger 710 with door 708 according to signal Sc and S1, trigger 710 produces detection signal Sc according to output and the signal S1 with door 708.Figure 18 is the oscillogram of signal in Figure 17, and wherein waveform 800 is pulse-width modulation signal PWM, and waveform 802 is the voltage on node LX, and waveform 804 is detection signal Sc.With reference to Figure 12, Figure 17 and Figure 18, after pulse-width modulation signal PWM transferred low level to, transistor N1 closed the voltage that makes on node LX and draws high, and trigger 710 also transfers because of signal S1 the detection signal Sc that low level produces high levle to
To open transistor 236, as time t1, at this moment, diode 240 prevents that electric current from flowing to input voltage VIN from node LX through transistor 236, then, when the voltage on node LX is down to than the low voltage VD of input voltage VIN, as time t2, electric charge bypass resistance 202 will form a bypass path envoy and put the level that voltage on LX maintains input voltage VIN.
In the above-described embodiments, all to produce signal Sc to determine whether electric charge bypass resistance 202 forms a bypass path by the voltage on detecting node LX, but can also produce signal Sc by alternate manner in other embodiments, as shown in figure 19, circuit for detecting 203 produces signal Sc for detecting pulse-width modulation signal PWM, and circuit for detecting 203 can be by postponing or anti-phase pulse-width modulation signal PWM generation signal Sc.
Above introduction only be based on preferred embodiment of the present invention, can not limit scope of the present invention with this.Any replacement, combination, discrete of the present invention being made step well know in the art, and to the invention process step do well know in the art be equal to change or replace all do not exceed exposure of the present invention and protection range.
Claims (10)
1. circuit for detecting that is applied in the asynchronous pressure boosting type electric voltage converter of resistant and oscillation resistant, described electric pressure converter comprises that at least one switch sees through a node and connects an inductance, this switch is controlled by a first signal and switches to control the inductive current that flows through this inductance and transfer an input voltage to an output voltage, and this circuit for detecting comprises:
One comparator produces a secondary signal when voltage on this node reaches a critical value;
One logical circuit produces a detection signal according to this first signal and secondary signal; And
One bypass resistance, this detection signal drive this bypass resistance to form a bypass path between this input voltage and this node.
2. circuit for detecting as claimed in claim 1, is characterized in that, described circuit for detecting comprises that the more isolated circuit of a high pressure is connected between this node and comparator, in order to isolated high pressure.
3. circuit for detecting as claimed in claim 2, is characterized in that, the isolated circuit of described high pressure comprises that a transistor is connected between this node and comparator, and this transistor is a high potential assembly.
4. circuit for detecting as claimed in claim 1, is characterized in that, described logical circuit comprises that a trigger produces this detection signal in response to this first signal and secondary signal.
5. circuit for detecting as claimed in claim 4, is characterized in that, described trigger produces described detection signal until described first signal transfers one second level to according to this secondary signal when described first signal is first level.
6. circuit for detecting as claimed in claim 1, is characterized in that, described logical circuit comprises that a counter produces this detection signal in response to this first signal and secondary signal.
7. circuit for detecting as claimed in claim 6, it is characterized in that, described counter is counted the number of times that this secondary signal occurs when this first signal is first level, and produces this detection signal until this first signal transfers one second level to when the number of times that this secondary signal occurs reaches a default value.
8. method for detecting that is applied in the asynchronous pressure boosting type electric voltage converter of resistant and oscillation resistant, described electric pressure converter comprises that at least one switch sees through a node and connects an inductance, this switch is controlled by a first signal and switches to control the inductive current that flows through this inductance and transfer an input voltage to an output voltage, and the method comprises the following steps:
(1) detect voltage on this node;
Produce a secondary signal when (2) voltage on this node reaches a critical value;
(3) produce a detection signal according to this first signal and secondary signal; And
(4) utilize this detection signal, make the bypass resistance conducting between this input voltage and this node form a bypass path.
9. method for detecting as claimed in claim 8, is characterized in that, the step of this generation one detection signal comprises:
When this first signal is first level, cover this secondary signal; And
When this first signal is second level, produce this detection signal until this first signal transfers this first level to according to secondary signal.
10. method for detecting as claimed in claim 8, is characterized in that, the step of described generation one detection signal comprises:
When this first signal is first level, count the number of times of this secondary signal appearance to produce a count value;
When this count value reaches a default value, produce this detection signal until this first signal transfers one second level to; And
When this first signal transfers this second level to, this count value of resetting.
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| CN 201010284789 CN102013796B (en) | 2007-08-13 | 2007-08-13 | Detection circuit and detection method for anti-oscillation asynchronous boosting type voltage converter |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1296331A (en) * | 1999-11-16 | 2001-05-23 | 常盘电业株式会社 | Power source circuit |
| JP2007143368A (en) * | 2005-11-22 | 2007-06-07 | Ricoh Co Ltd | Synchronous rectification type switching regulator, control circuit of the synchronous rectification type switching regulator, and operation control method of the synchronous rectification type switching regulator |
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| US6396250B1 (en) * | 2000-08-31 | 2002-05-28 | Texas Instruments Incorporated | Control method to reduce body diode conduction and reverse recovery losses |
| DE102004031395A1 (en) * | 2004-06-29 | 2006-02-02 | Infineon Technologies Ag | DC converter |
| US7235955B2 (en) * | 2004-07-26 | 2007-06-26 | Intersil Americas Inc. | Method and apparatus for preventing boosting system bus when charging a battery |
| US20060103365A1 (en) * | 2004-11-17 | 2006-05-18 | Compulite Systems (2000) Ltd. | Method and converter circuitry for improved-performance AC chopper |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1296331A (en) * | 1999-11-16 | 2001-05-23 | 常盘电业株式会社 | Power source circuit |
| JP2007143368A (en) * | 2005-11-22 | 2007-06-07 | Ricoh Co Ltd | Synchronous rectification type switching regulator, control circuit of the synchronous rectification type switching regulator, and operation control method of the synchronous rectification type switching regulator |
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