CN102013266A - Source line biasing circuit and voltage compensation unit thereof - Google Patents
Source line biasing circuit and voltage compensation unit thereof Download PDFInfo
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- CN102013266A CN102013266A CN2009101956204A CN200910195620A CN102013266A CN 102013266 A CN102013266 A CN 102013266A CN 2009101956204 A CN2009101956204 A CN 2009101956204A CN 200910195620 A CN200910195620 A CN 200910195620A CN 102013266 A CN102013266 A CN 102013266A
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Abstract
The invention relates to a source line biasing circuit and a voltage compensation unit thereof, wherein the voltage compensation unit of the source line biasing circuit comprises a current-to-voltage conversion unit and a conversion unit, wherein the current-to-voltage conversion unit comprises a tracking transistor which has the same type, number and channel length with the transistor in a source line biasing path and converts an input source line compensation current into a source line compensation voltage; and the conversion unit compensates a biasing voltage input by voltage compensation by utilizing a source line to obtain a compensation voltage. The source line biasing circuit and the voltage compensation unit thereof can compensate the voltage drop deviation of the whole source line biasing path caused by the process variation.
Description
Technical field
The present invention relates to memory circuitry, particularly a provenance line biasing circuit and voltage compensation unit thereof.
Background technology
Storer (for example, flash memory Flash memory) storage unit generally includes four lead-in wires: bit line (BL, bit-line), word line (WL, word-line), source line (SL, source-line) and baseline (SBL, sub-line), corresponding respectively drain electrode, grid, source electrode and the base stage that couples MOS transistor.
Generally, when the storage unit of storer was carried out write operation, for example programming (program) and wipe (erase) pattern need be with the voltage bias of source line to high voltage (high voltage).Fig. 1 has shown the elementary path of source line biasing: charge pump unit 11 and adjustment unit 12 provide stable bias voltage HV; (for example under programming mode, write control signal WR_ENB is a low level) was biased to bias voltage HV with source line voltage VSL when source line voltage generation unit 13 need be setovered at the source line; Source line driver element 14 when corresponding source line is selected (line options signal SL_ENB is a low level as the source) with the voltage bias of source line SL to source line voltage VSL, i.e. bias voltage HV.
When write operation, have electric current on the line of source, because it is at random (write data " 0 " or " 1 ") that the user carries out write operation to storage unit, it is corresponding that the load (loading) of source line can be different when write operation, therefore, the magnitude of voltage on the line of source can produce deviation because of the pressure drop of source line bias path (bias voltage HV is to the transmission path of the voltage of source line SL).Source line bias path as shown in Figure 2, voltage compensation unit 15 is used to compensate the voltage deviation on the line of source, the current value of source line when Iwr is write operation, it is relevant with technology; X*Iwr represents the current value according to the load needs compensation of current source line, control transformation unit 152 converts bias voltage HV to bucking voltage HV_CPS it is converted to the magnitude of voltage that will compensate by current conversion voltage cell 151 after, and the voltage of source line SL is biased to bucking voltage HV_CPS.
Fig. 3 is an example circuit diagram of existing source line biasing circuit, in conjunction with Fig. 2, the current conversion voltage cell 151 of voltage compensation unit 15 comprises resistance R c, converting unit 152 comprises conversioning transistor mn1, source line voltage generation unit 13 comprises the first switching transistor mp1, and source line driver element 14 comprises second switch transistor mp2 and pull-down transistor mn2.
Yet, the pressure drop of whole source line bias path (bias voltage HV is to the voltage of source line SL) also has deviation because of the MOS transistor technique change, as under slow process corner (slow process corner) situation, the threshold voltage of the first switching transistor mp1 and second switch transistor mp2 is big, and the pressure drop meeting of source line bias path more greatly; Under fast process corner (fast process corner) situation, the threshold voltage of the first switching transistor mp1 and second switch transistor mp2 is little, and the pressure drop meeting of source line bias path is littler.And in circuit shown in Figure 3, owing to resistance R c can not change with technology, so voltage compensation unit 15 can't compensate the pressure drop deviation of whole source line bias path.
Summary of the invention
The problem that the present invention solves provides a provenance line biasing circuit and voltage compensation unit thereof, to compensate the pressure drop deviation of the source line bias path that causes because of technique change.
For addressing the above problem, embodiment of the present invention provides the voltage compensation unit of a provenance line biasing circuit, comprise: the current conversion voltage cell, comprise with source line bias path in the identical tracking transistor of transistor types, quantity and channel length, described tracking transistor with the input source line offset current be converted to source line bucking voltage; Converting unit, the bias voltage with described source line bucking voltage compensation input obtains bucking voltage.
For addressing the above problem, embodiment of the present invention also provides a provenance line biasing circuit, comprising:
The current conversion voltage cell, comprise with source line bias path in the identical tracking transistor of transistor types, quantity and channel length, described tracking transistor with the input source line offset current be converted to source line bucking voltage;
Converting unit, the bias voltage with described source line bucking voltage compensation input obtains bucking voltage;
The source line voltage generation unit when write operation, is biased to described bucking voltage with source line voltage;
Source line driver element, when the source line is selected, with the voltage bias of source line to described source line voltage.
Compared with prior art, technique scheme adopts the transistor identical with transistor types, quantity and channel length in the line bias path of source to come the change in voltage of tracing source line bias path, that is to say, follow the tracks of the change in voltage that causes because of technique change with the transistor identical, so technique scheme can compensate the pressure drop deviation of the whole source line bias path that causes because of technique change with transistorized technique change situation in the line bias path of source.
Description of drawings
Fig. 1 is the elementary path synoptic diagram of provenance line biasing;
Fig. 2 is a kind of path synoptic diagram with source line biasing of voltage compensation;
Fig. 3 is the example circuit diagram of existing source line biasing circuit;
Fig. 4 is the embodiment circuit diagram of source of the present invention line biasing circuit.
Embodiment
Embodiment of the present invention adopts the transistor identical with transistor types, quantity and channel length in the line bias path of source to come the change in voltage of tracing source line bias path.
The voltage compensation unit of the source line biasing circuit of embodiment of the present invention comprises:
The current conversion voltage cell, comprise with source line bias path in the identical tracking transistor of transistor types, quantity and channel length, described tracking transistor with the input source line offset current be converted to source line bucking voltage;
Converting unit, the bias voltage with described source line bucking voltage compensation input obtains bucking voltage.
The source line biasing circuit of embodiment of the present invention comprises above-mentioned voltage compensation unit.
Below in conjunction with drawings and Examples embodiment of the present invention is described in detail.Please refer to Fig. 4, the source line biasing circuit of present embodiment comprises: voltage compensation unit 25, source line voltage generation unit 13 and source line driver element 14.
Current conversion voltage cell 251, comprise with source line bias path in the identical tracking transistor of transistor types, quantity and channel length, described tracking transistor with the input source line offset current X*Iwr be converted to source line bucking voltage SL_CPS;
Converting unit with described source line bucking voltage SL_CPS compensation bias voltage HV, obtains bucking voltage HV_CPS.
Source line bias path shown in Figure 4 comprises 2 PMOS transistor mp1, mp2, and therefore, current conversion voltage cell 251 comprises 2 PMOS transistor mp1_dm, the mp2_dm that channel length is identical with transistor mp1, mp2.
Specifically, current conversion voltage cell 251 comprises that first follows the tracks of the transistor mp1_dm and the second tracking transistor mp2.It is the PMOS transistor that grid connects low-voltage that the first tracking transistor mp1_dm and second follows the tracks of transistor mp2, therefore is in normally open; First follows the tracks of the source electrode input offset voltage HV of transistor mp1_dm, first drain electrode of following the tracks of transistor mp1_dm connects the source electrode of the second tracking transistor mp2_dm, second follows the tracks of the drain electrode input source line offset current X*Iwr of transistor mp2_dm, current value when Iwr is write operation, X*Iwr is the current value of the required compensation of load of corresponding current source line, and second drain voltage of following the tracks of transistor mp2_dm is source line bucking voltage SL_CPS.The X value should be as much as possible little, and to reduce the output current load of charge pump, the X value is chosen as the value less than 1 usually.
Converting unit 252 comprises conversioning transistor mn1.Conversioning transistor mn1 is a nmos pass transistor, and grid connects the drain electrode (being input source line bucking voltage SL_CPS) of the second tracking transistor mp2_dm, source electrode input offset voltage HV, drain electrode output bucking voltage HV_CPS.
Source line voltage generation unit 13 when write operation, is biased to bucking voltage HV_CPS with source line voltage VSL.Source line voltage generation unit 13 comprises the first switching transistor mp1, the first switching transistor mp1 is the PMOS transistor, grid input write control signal WR_ENB, source electrode input offset voltage HV_CPS (i.e. drain electrode with conversioning transistor mn1 is connected), drain electrode output source line voltage VSL.When write operation (for example programming mode), source line SL needs biasing, and write control signal WR_ENB is a low level.
Source line driver element 14, when source line SL is selected, with the voltage bias of source line SL to source line voltage VSL.Source line driver element 14 comprises second switch transistor mp2, second switch transistor mp2 is the PMOS transistor, grid input source line options signal SL_ENB, source electrode input source line voltage VSL (i.e. drain electrode with the first switching transistor mp1 is connected), drain electrode connection source line SL.When choosing source line SL, source line options signal SL_ENB is a low level.
Source line driver element 14 also comprises pull-down transistor mn2, and pull-down transistor mn2 is a nmos pass transistor, grid input source line options signal SL_ENB, and source electrode connects low-voltage, drain electrode connection source line SL (i.e. drain electrode with second switch transistor mp2 is connected).When not choosing source line SL, source line options signal SL_ENB is a high level, and pull-down transistor mn2 is pulled down to low level with source line SL.
In other embodiments, first switching transistor and second switch transistor also can be nmos pass transistors, and grid is effective write control signal of input high level and source line options signal respectively; Correspondingly, first of the current conversion voltage cell 251 tracking transistor and the second tracking transistor also should be nmos pass transistors.
Therefore the circuit of comparison diagram 3 and Fig. 4 when load (for example to storage unit write data " 0 ") is arranged, provides big voltage to the source line on the line SL of source, X=0 is set, the voltage V of Fig. 3 and source line SL shown in Figure 4
SLBe expressed as:
V
SL＝HV-Vt-V
ds(mp1)-V
ds(mp2) (1)
Wherein, Vt is the threshold voltage of conversioning transistor mn1, V
Ds (mp1), V
Ds (mp2)Pressure drop is leaked in the source that is respectively the first switching transistor mp1 and second switch transistor mp2.
When not having load (for example to storage unit write data " 1 ") on the line SL of source, line provides small voltage to the source, X=maximal value (the X value is less than 1 usually) therefore is set, the voltage V of source line SL shown in Figure 3
SLBe expressed as:
V
SL＝HV-Vt-Rc*X*Iwr (2)
And the voltage V of source line SL shown in Figure 4
SLBe expressed as:
V
SL＝HV-Vt-V
ds(mpl_dm)-V
ds(mp2_dm) (3)
Wherein, V
Ds (mp1_dm), V
Ds (mp2_dm)Be respectively first and follow the tracks of the source leakage pressure drop that transistor mp1_dm and second follows the tracks of transistor mp2_dm.
For circuit shown in Figure 3, convolution (2) is provided with the voltage deviation that X value and/or Rc value just can compensate the source line as can be known.But, because therefore the Rc value can, can't not compensate the pressure drop deviation of the whole source line bias path that causes because of technique change with technique change.
For circuit shown in Figure 4, convolution (3) is provided with X value and/or first and follows the tracks of the voltage deviation that transistor mp1_dm, second channel width of following the tracks of transistor mp2_dm just can compensate the source line as can be known.And,, therefore, also can compensate the pressure drop deviation of the whole source line bias path that causes because of technique change because the first tracking transistor mp1_dm, second follows the tracks of transistor mp2_dm with technique change.Specifically, first to follow the tracks of type and the channel length of the first switching transistor mp1 in type that transistor mp1_dm and second follows the tracks of transistor mp2_dm and channel length and the source line bias path and second switch transistor mp2 identical, therefore, the technique change of the first switching transistor mp1 and second switch transistor mp2 can be reflected in first and follow the tracks of the transistor mp1_dm and second technique change of following the tracks of transistor mp2_dm, correspondingly from formula (3) and (1) can see more also that first follows the tracks of pressure drop that transistor mp1_dm and the second tracking transistor mp2_dm cause because of technique change can follow the tracks of the pressure drop that the first switching transistor mp1 and second switch transistor mp2 cause because of technique change.
In addition, as previously mentioned, in order to reduce the output current load of charge pump, the X value should be as much as possible little.For circuit shown in Figure 3, the X value can not be too little, because the X value is more little, correspondingly resistance R c is big more, and big resistance not only can increase chip area, also can increase stray capacitance.And for circuit shown in Figure 4, it is as much as possible little that the X value then can be accomplished, because follow the tracks of the influence that transistor mp1_dm, mp2_dm can not be subjected to the X value.
In sum, technique scheme adopts the transistor identical with transistor types, quantity and channel length in the line bias path of source to come the change in voltage of tracing source line bias path, so can compensate the pressure drop deviation of the whole source line bias path that causes because of technique change.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (11)
1. the voltage compensation unit of a provenance line biasing circuit is characterized in that, comprising:
The current conversion voltage cell, comprise with source line bias path in the identical tracking transistor of transistor types, quantity and channel length, described tracking transistor with the input source line offset current be converted to source line bucking voltage;
Converting unit, the bias voltage with described source line bucking voltage compensation input obtains bucking voltage.
2. the voltage compensation unit of source according to claim 1 line biasing circuit is characterized in that, the source line offset current of described input is X a times of write-operation current, and wherein, X is less than 1.
3. the voltage compensation unit of source according to claim 1 line biasing circuit is characterized in that, described current conversion voltage cell comprises that being in first of normally open follows the tracks of the transistor and the second tracking transistor, wherein,
The transistorized source electrode input offset voltage of first tracking, drain electrode connect second and follow the tracks of transistorized source electrode, and second follows the tracks of transistor drain input source line offset current, and the second tracking transistor drain voltage is source line bucking voltage.
4. the voltage compensation unit of source according to claim 1 line biasing circuit is characterized in that described converting unit comprises conversioning transistor, grid input source line bucking voltage, source electrode input offset voltage, drain electrode output bucking voltage.
5. a provenance line biasing circuit is characterized in that, comprising:
The current conversion voltage cell, comprise with source line bias path in the identical tracking transistor of transistor types, quantity and channel length, described tracking transistor with the input source line offset current be converted to source line bucking voltage;
Converting unit, the bias voltage with described source line bucking voltage compensation input obtains bucking voltage;
The source line voltage generation unit when write operation, is biased to described bucking voltage with source line voltage;
Source line driver element, when the source line is selected, with the voltage bias of source line to described source line voltage.
6. source according to claim 5 line biasing circuit is characterized in that, the source line offset current of described input is X a times of write-operation current, and wherein, X is less than 1.
7. source according to claim 5 line biasing circuit is characterized in that, described current conversion voltage cell comprises that being in first of normally open follows the tracks of the transistor and the second tracking transistor, wherein,
The transistorized source electrode input offset voltage of first tracking, drain electrode connect second and follow the tracks of transistorized source electrode, and second follows the tracks of transistor drain input source line offset current, and the second tracking transistor drain voltage is source line bucking voltage.
8. source according to claim 5 line biasing circuit is characterized in that described converting unit comprises conversioning transistor, grid input source line bucking voltage, source electrode input offset voltage, drain electrode output bucking voltage.
9. source according to claim 5 line biasing circuit is characterized in that described source line voltage generation unit comprises first switching transistor, grid input write control signal, source electrode input offset voltage, drain electrode output source line voltage.
10. source according to claim 5 line biasing circuit is characterized in that, described source line driver element comprises the second switch transistor, grid input source line options signal, source electrode input source line voltage, drain electrode connection source line.
11. source according to claim 10 line biasing circuit is characterized in that, also comprises pull-down transistor, grid input source line options signal, and source electrode connects low-voltage, drain electrode connection source line.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910195620 CN102013266B (en) | 2009-09-07 | 2009-09-07 | Source line biasing circuit and voltage compensation unit thereof |
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| CN 200910195620 CN102013266B (en) | 2009-09-07 | 2009-09-07 | Source line biasing circuit and voltage compensation unit thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290101A (en) * | 2011-07-04 | 2011-12-21 | 上海宏力半导体制造有限公司 | Source line biasing circuit and memory |
| CN103730160B (en) * | 2014-01-07 | 2016-08-24 | 上海华虹宏力半导体制造有限公司 | A kind of memory and read method, reading circuit |
| CN109300493A (en) * | 2017-07-25 | 2019-02-01 | 三星电子株式会社 | Ripple compensation device, data drive circuit and semiconductor devices |
-
2009
- 2009-09-07 CN CN 200910195620 patent/CN102013266B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290101A (en) * | 2011-07-04 | 2011-12-21 | 上海宏力半导体制造有限公司 | Source line biasing circuit and memory |
| CN102290101B (en) * | 2011-07-04 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | Source line biasing circuit and storer |
| CN103730160B (en) * | 2014-01-07 | 2016-08-24 | 上海华虹宏力半导体制造有限公司 | A kind of memory and read method, reading circuit |
| CN109300493A (en) * | 2017-07-25 | 2019-02-01 | 三星电子株式会社 | Ripple compensation device, data drive circuit and semiconductor devices |
| CN109300493B (en) * | 2017-07-25 | 2023-11-28 | 三星电子株式会社 | Ripple compensator, data driving circuit and semiconductor device |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140416 |
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Effective date of registration: 20140416 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |