CN102006443B - Port switching and signal processing method and circuit - Google Patents
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Abstract
The invention relates to a port switching and signal processing method and circuit. The invention provides a port switching and signal processing method which comprises the following steps of: firstly inputting video signals; when the input video signals are the digital signals, directly transmitting digital signals to a video processing unit after electrostatic discharge protection and impedance matching are carried out on the digital signals by a digital signal receiving and processing unit; and when the input video signals are the video graphics array and green synchronous video signals, dividing the video graphics array and green synchronous video signals into two paths to be transmitted and processed after the electrostatic discharge protection and the impedance matching are carried out on video images by a video graphics array\green synchronous signal receiving processing unit. The invention also provides a port switching and signal processing circuit. The invention has the advantages that the input of different signals by the single port is realized, the problem of various interfaces is avoided and the ESD (Electronic Static Discharge) and EFT (Electrical Fast Transient) resistance performance of composite video signals is improved.
Description
Technical Field
The present invention relates to digital information transmission, and more particularly, to a method and circuit for port switching and signal processing in digital information transmission.
Background
The current medical display device mainly uses a Digital Video Interface (DVI) or an analog Video Interface (Video Graphics Array, VGA for short), Video + HS (horizontal synchronization signal, HSYNC or HS for short)/VS (vertical synchronization signal, VSYNC or VS for short), Video + XS, Sync On Green (Green synchronization), SOG for short, composite Video signal (composite signal or composite Video signal), CVS for short, however, the current display Interface technology generally has a plurality of ports and each port can only support one or two of the signals, i.e. each port has a single function. Particularly, the current display device only supports composite video, and its anti-ESD (Electro-Static discharge, abbreviated as ESD) and anti-EFT (Electrical Fast Transient/burst, abbreviated as EFT) effects cannot meet the requirements of the medical field at all.
Since the level of the sync header of the Composite Video Signal (CVS) is only about 0.3V, if it is directly sent to the subsequent video processing chip (LSI) without any isolation, the subsequent video processing chip is very susceptible to interference on the CVS, which results in failure of normal operation, especially when ESD of 8KV is applied and EFT test of 2KV is performed, it cannot pass at all. Moreover, the signal interfaces of the display device are very numerous at present, however, in practical application, each set of medical diagnosis system usually only outputs one signal and only needs one signal interface; the redundant ports not only cause cost waste and inconvenience for structural design, but also are not favorable for the EMI (Electromagnetic Interference) effect of the medical equipment.
Disclosure of Invention
The invention provides a port switching and signal processing method and a circuit thereof, aiming at solving the problems that in the prior art, the interfaces are various and composite video signals cannot pass anti-ESD and EFT tests.
The invention provides a port switching and signal processing method, firstly inputting a video signal;
when the input video signal is a digital signal, the digital signal is directly transmitted to a video processing unit after electrostatic discharge protection and impedance matching are finished by a digital signal receiving and processing unit;
when the input video signals are display drawing array and green synchronous video signals, the display drawing array and the green synchronous video signals are divided into two paths for transmission and processing after electrostatic discharge protection and impedance matching of the video images are completed through a display drawing array/green synchronous signal receiving and processing unit,
one path of the synchronous switching unit is used for transmitting the separated synchronous signals and the composite synchronous signals contained in the display drawing array video signals to the synchronous switching unit for synchronous switching and shaping, the synchronous switching unit is used for operating and selecting the composite signals or synchronous input of the display drawing array video signals according to a screen menu type adjusting mode of a user, the correct display drawing array synchronous video signals are transmitted to the sampling clock recovery unit so as to generate a sampling clock meeting analog-to-digital conversion sampling by frequency doubling, and then the sampling clock is input to the analog-to-digital conversion unit so as to provide a stable and reliable sampling clock for analog-to-digital conversion of the analog-to-digital conversion unit;
the other path inputs the display drawing array and the green synchronous video signal to a video signal amplifying unit for voltage amplification, then transmits the signals to an analog-to-digital conversion unit for analog-to-digital conversion, and transmits the digital signals output by the analog-to-digital conversion unit to the video processing unit;
when a composite signal is input, the composite signal is divided into two paths for transmission and processing, wherein,
one path inputs the composite signal to a composite signal receiving and processing unit for high-impedance isolation, then carries out low-pass filtering, then inputs the composite signal to a synchronous extraction unit for synchronous extraction, strips out the composite synchronous signal with only 0.3V, outputs the composite synchronous signal to the synchronous switching unit for synchronous switching and shaping in the level amplitude of 5VPP, selects the composite signal or displays the synchronous input of the video signal of the drawing array through the synchronous switching unit according to the operation of a screen menu type adjusting mode of a user, outputs the correct composite synchronous signal to a sampling clock recovery unit to generate a sampling clock meeting the sampling of analog-to-digital conversion, and then inputs the sampling clock to an analog-to-digital conversion unit to provide a stable and reliable sampling clock for the analog-to-digital conversion of the analog-to-digital conversion unit,
and the other path of the composite signal is transmitted to the video signal amplifying unit for voltage amplification, then transmitted to the analog-to-digital conversion unit for analog-to-digital conversion, and then transmitted to the video processing unit.
As a further improvement of the present invention, first, a video signal is input through the DVI-I interface.
As a further improvement of the invention, when the composite signal of 1VPP is input from the blue channel of the DVI-I interface, the composite signal is subjected to high-impedance isolation through a MOS tube Q12, then is subjected to low-pass filtering, and then is input into a synchronous extraction unit for synchronous extraction.
As a further improvement of the present invention, the composite signal after high impedance isolation by the MOS transistor Q12 and low pass filtering is input to an LM1881 video synchronization separation chip for synchronization extraction, and the LM1881 video synchronization separation chip strips out the composite synchronization signal of only 0.3V and outputs the composite synchronization signal to the synchronization switching unit at a level of 5VPP for synchronization switching and shaping.
As a further improvement of the invention, the LM1881 video synchronization separation chip strips out the composite synchronization signal with only 0.3V, and outputs the composite synchronization signal to the 74HC4052 chip with the level amplitude of 5VPP for synchronous switching and shaping.
The invention also provides a port switching and signal processing circuit, which comprises a digital signal receiving and processing unit for performing electrostatic discharge protection and impedance matching, a display drawing array \ green synchronous signal receiving and processing unit for performing electrostatic discharge protection and impedance matching, and a composite signal receiving and processing unit for performing high-impedance isolation and low-pass filtering, wherein,
the output end of the digital signal receiving and processing unit is connected with a video processing unit,
the output end of the display drawing array/green synchronous signal receiving and processing unit is respectively connected with a video signal amplifying unit and a synchronous switching unit, the video signal amplifying unit amplifies the voltage of the signals, the display drawing array/green synchronous signal receiving and processing unit transmits the separated synchronous signals and the composite synchronous signals contained in the display drawing array video signals to the synchronous switching unit for synchronous switching and shaping,
the output end of the video signal amplifying unit is connected with an analog-to-digital conversion unit, the output end of the analog-to-digital conversion unit is connected with the input end of the video processing unit, the output end of the synchronous switching unit is connected with a sampling clock recovery unit, the output end of the sampling clock recovery unit is connected with the input end of the analog-to-digital conversion unit, the output end of the composite signal receiving and processing unit is connected with a synchronous extraction unit, the output end of the synchronous extraction unit is connected with the input end of the synchronous switching unit, wherein,
the synchronous extraction unit strips a composite synchronous signal with only 0.3V, then outputs the composite synchronous signal to the synchronous switching unit for synchronous switching and shaping in a level amplitude of 5VPP, the synchronous switching unit selects the composite signal or displays synchronous input of a drawing array according to the operation of a screen menu type adjustment mode of a user, outputs a correct synchronous signal to the sampling clock recovery unit, multiplies the frequency to generate a sampling clock meeting analog-to-digital conversion sampling, and then inputs the sampling clock to the analog-to-digital conversion unit to provide a stable and reliable sampling clock for analog-to-digital conversion of the analog-to-digital conversion unit.
As a further improvement of the invention, the port switching and signal processing circuit comprises a DVI-I interface, and the digital signal receiving and processing unit, the display drawing array \ green synchronous signal receiving and processing unit, the composite signal receiving and processing unit and the video signal amplifying unit are respectively connected with the DVI-I interface.
As a further improvement of the present invention, the composite signal receiving and processing unit includes a MOS transistor Q12, a gate of the MOS transistor Q12 is connected to the blue channel of the DVI-I interface, a drain of the MOS transistor Q12 is connected between the output end of the display drawing array \ green synchronization signal receiving and processing unit and the input end of the video signal amplifying unit, and a source of the MOS transistor Q12 is connected to the input end of the synchronization extracting unit.
As a further improvement of the present invention, the synchronous extraction unit includes an LM1881 video synchronization separation chip, the source of the MOS transistor Q12 is connected to the input end of the LM1881 video synchronization separation chip, and the CSOUT end of the LM1881 video synchronization separation chip is connected to the input end of the synchronous switching unit.
As a further improvement of the present invention, the synchronous switching unit includes a 74HC4052 chip, the CSOUT terminal of the LM1881 video synchronization separation chip is connected to the 2Y1 terminal of the 74HC4052 chip, the separation synchronization signal output by the display drawing array \ green synchronization signal receiving processing unit includes a vertical synchronization signal and a horizontal synchronization signal, the vertical synchronization signal is connected to the 1Y0 terminal of the 74HC4052 chip, and the horizontal synchronization signal is connected to the 2Y0 terminal of the 74HC4052 chip.
The invention has the beneficial effects that: by the scheme, the input of different signals of a single port is realized, the problem of multiple interfaces is avoided, and the ESD (electro-static discharge) and EFT (extended edge test) resistance of the composite video signal is improved.
Drawings
FIG. 1 is a schematic block diagram of a port switching and signal processing circuit according to the present invention;
fig. 2 is a circuit diagram of the port switching and signal processing circuit according to the present invention.
Detailed Description
The invention is further described with reference to the following description and embodiments in conjunction with the accompanying drawings.
The reference numerals in fig. 1 to 2 are: a digital signal reception processing unit 1; a VGA \ SCG signal receiving and processing unit 2; a video signal amplifying unit 3; an analog-to-digital conversion unit 4; a synchronous switching unit 5; a sampling clock recovery unit 6; a CVS signal reception processing unit 7; a synchronous extraction unit 8; an MCU (Micro Control Unit, abbreviated as MCU) 9; a signal input module power management unit 10; a video processing unit 100.
As shown in fig. 1 to fig. 2, in a method for port switching and signal processing, a video signal is input first, and the input video signal may be a digital signal or an analog signal; wherein,
when the input video signal is a digital signal, the digital signal is directly transmitted to the video processing unit 100 after electrostatic discharge (ESD) protection and impedance matching are completed by the digital signal receiving and processing unit 1, and the next operation processing is performed;
when the input video signals are display drawing array (VGA) and green Synchronous (SOG) video signals, the display drawing array (VGA) and green Synchronous (SOG) video signals are input by Blue channel (Blue), after the display drawing array (VGA) and green Synchronous (SOG) video signals pass through the display drawing array \ green synchronous signal receiving and processing unit to complete electrostatic discharge protection and impedance matching of video images, the display drawing array \ green synchronous signal receiving and processing unit can be abbreviated as VGA \ SCG signal receiving and processing unit 2, the signals are divided into two paths for transmission and processing, wherein,
one path of the synchronous switching unit transmits the separation synchronous signal (H + V, namely HS + VS) and the composite synchronous signal (XS) contained in the video signal of the display drawing array (VGA) to the synchronous switching unit 5 for synchronous switching and shaping, the synchronous switching unit 8 selects the synchronous input of the composite signal (CVS) or the video signal of the display drawing array (VGA) according to the on-screen display (OSD) operation of a user, and outputs the correct synchronous video signal of the display drawing array (VGA) to the (ADC) sampling clock recovery unit 6 to generate a sampling clock meeting the analog-to-digital conversion sampling by frequency doubling, and then the sampling clock is input to the analog-to-digital conversion unit 4 to provide a stable and reliable sampling clock for the analog-to-digital conversion of the analog-to-digital conversion unit 4,
the other path outputs the display drawing array (VAG) and green Synchronization (SOG) video signals to the video signal amplifying unit 3 to perform 1: 1, and then the amplified voltage is transmitted to an analog-to-digital conversion unit 4 for analog-to-digital conversion, the analog-to-digital conversion unit 4 performs analog-to-digital conversion according to the provided sampling clock and outputs a digital signal to the video processing unit 100 for further operation, and the analog-to-digital conversion unit 4 may be referred to as an ADC unit (analog-to-digital conversion, ADC for short);
when a composite signal (CVS) of 1VPP is input from a Blue channel (Blue), the composite signal is divided into two paths for transmission and processing, wherein,
the composite signal (CVS) is input into a composite signal receiving and processing unit for high-impedance isolation, low-pass filtering is carried out, then the composite signal is input into a synchronous extraction unit 7 for synchronous extraction, a composite synchronous signal with only 0.3V is stripped from a video signal, and the composite synchronous signal is output to a synchronous switching unit 8 for synchronous switching and shaping in a level amplitude of 5 VPP; the composite signal receiving and processing unit may be abbreviated as CVS receiving and processing unit 7, the synchronous switching unit 8 selects synchronous input of a composite signal (CVS) or a video signal of a display graphics array (VGA) according to an on-screen display (OSD) operation of a user, and outputs a correct composite synchronous signal to the (ADC) sampling clock recovery unit 6, and a sampling clock satisfying analog-to-digital conversion sampling is generated by frequency multiplication to provide a stable and reliable sampling clock for analog-to-digital conversion of the analog-to-digital conversion unit 4,
and the other path of the composite signal is transmitted to the video signal amplifying unit 3 for voltage amplification, then transmitted to the analog-to-digital conversion unit 4 for analog-to-digital conversion, and then transmitted to the video processing unit 100 as a digital signal output by the analog-to-digital conversion unit 4.
First, a video signal is input through a DVI-I (Digital Visual Interface, DVI for short) Interface. When the input is digital DVI signal, a standard DVI-D signal line can be selected to directly connect the display device and the signal source. When the video signals are VGA or SOG video signals which are separated and synchronized, a DVI-A to VGA signal wire which is provided in a matched mode can be selected for switching. When the input is a composite VIDEO signal of VIDEO + XS/HS/VS and CVS, a DVI-A to BNC signal wire rod which is provided in a matching way can be selected for switching.
When a composite signal (CVS) of 1VPP is input from the BLUE channel (BLUE) of the DVI-I interface, the composite signal (CVS) is high-impedance isolated by the MOS transistor Q12, low-pass filtered, and then input to the synchronous extraction unit 8 for synchronous extraction.
The composite signal (CVS) which is subjected to high-impedance isolation by the MOS tube Q12 and then is subjected to low-pass filtering is input into an LM1881 video synchronization separation chip for synchronous extraction, and the LM1881 video synchronization separation chip strips the composite synchronization signal only having 0.3V from the video signal and outputs the composite synchronization signal to the synchronization switching unit 5 at the level amplitude of 5VPP for synchronous switching and shaping.
The LM1881 video synchronization separation chip strips out the composite synchronization signal only having 0.3V, and outputs the composite synchronization signal to the 74HC4052 chip for synchronous switching and shaping in the level amplitude of 5 VPP.
As shown in fig. 1 to 2, the present invention further provides a port switching and signal processing circuit, which includes a digital signal receiving and processing unit 1 for performing electrostatic discharge (ESD) protection and impedance matching, a display graphics array (VGA) \ green Synchronization (SOG) signal receiving and processing unit for performing electrostatic discharge (ESD) protection and impedance matching, and a composite signal (CVS) receiving and processing unit for performing high-impedance isolation and low-pass filtering, wherein,
the output end of the digital signal receiving and processing unit 1 is directly connected with the video processing unit 100, the input digital signal can be directly transmitted to the video processing unit 100 after electrostatic discharge (ESD) protection and impedance matching are completed by the digital signal receiving and processing unit 1 for the next operation processing,
the output end of the display drawing array (VGA) \ green Synchronous (SOG) signal receiving and processing unit is respectively connected with a video signal amplifying unit 3 and a synchronous switching unit 5, and the video signal amplifying unit 3 carries out 1: 1, the display graphic array (VGA) \ green Synchronization (SOG) signal receiving and processing unit transmits a separation synchronization signal (H + V, HS + VS) and a composite synchronization signal (XS) contained in a video signal of the display graphic array (VGA) to the synchronous switching unit 5 for synchronous switching and shaping,
the output end of the video signal amplifying unit 3 is connected with an analog-to-digital conversion (ADC) unit 4, the output end of the analog-to-digital conversion (ADC) unit 4 is connected with the input end of the video processing unit 100, the output end of the synchronous switching unit 5 is connected with a sampling clock recovery unit 6, the output end of the sampling clock recovery unit 6 is connected with the input end of the analog-to-digital conversion (ADC) unit 4, the output end of the composite signal receiving and processing unit is connected with a synchronous extraction unit 8, the output end of the synchronous extraction unit 8 is connected with the input end of the synchronous switching unit 6, wherein,
the synchronous extraction unit 8 strips the composite synchronous signal with only 0.3V from the video signal, then outputs the composite synchronous signal to the synchronous switching unit 5 for synchronous switching and shaping with the level amplitude of 5VPP, the synchronous switching unit 5 selects the synchronous input of the composite signal (CVA) or the display graphic array (VGA) according to the operation of the user's on-screen menu type adjustment mode (OSD), and outputs the synchronous input to the sampling clock recovery unit 6, generates the sampling clock meeting the analog-to-digital conversion sampling by frequency multiplication, and then inputs the sampling clock to the analog-to-digital conversion (ADC) unit 4, and provides a stable and reliable sampling clock for the analog-to-digital conversion of the analog-to-digital conversion unit 4,
the input end of the synchronous switching unit 5 is connected with an MCU (micro controller unit), and the MCU is connected with a signal input module power supply management unit.
The port switching and signal processing circuit comprises a DVI-I interface, and the digital signal receiving and processing unit 1, a display graphics array (VGA) \\ green Synchronous (SOG) signal receiving and processing unit, a composite signal (CVA) receiving and processing unit and a video signal amplifying unit 3 are respectively connected with the DVI-I interface.
The composite signal (CVS) receiving and processing unit includes a MOS transistor Q12, a gate (i.e., G pole) of the MOS transistor Q12 is connected to a BLUE channel (BLUE) of the DVI-I interface, a drain (i.e., D pole) of the MOS transistor Q12 is connected between an output terminal of the display graphics array (VGA) \\ green Synchronization (SOG) signal receiving and processing unit and an input terminal of the video signal amplifying unit 2, and a source (i.e., S pole) of the MOS transistor Q12 is connected to an input terminal of the synchronization extracting unit 7, so that high-resistance isolation and low-pass filtering of a composite signal (CVS) can be realized.
The synchronous extraction unit 7 comprises an LM1881 video synchronous separation chip, the source electrode of the MOS tube Q12 is connected with the input end of the LM1881 video synchronous separation chip, and the CSOUT end of the LM1881 video synchronous separation chip is connected with the input end of the synchronous switching unit 5.
The synchronous switching unit 5 includes a 74HC4052 chip, a CSOUT terminal of the LM1881 video synchronization separation chip is connected to a 2Y1 terminal of the 74HC4052 chip, a separation synchronization signal output by the display graphics array (VGA) \ green Synchronization (SOG) signal reception processing unit includes a vertical synchronization signal (HS) and a horizontal synchronization signal (VS), the vertical synchronization signal (VS) is connected to a 1Y0 terminal of the 74HC4052 chip, and the horizontal synchronization signal (HS) is connected to a 2Y0 terminal of the 74HC4052 chip.
The port switching and signal processing method and the circuit thereof provided by the invention realize the input of different signals of a single port, avoid the problem of multiple interfaces, improve the ESD and EFT resistance of the composite video signal and are beneficial to passing ESD and EFT tests.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A port switching and signal processing method is characterized in that: firstly, inputting a video signal;
when the input video signal is a digital signal, the digital signal is directly transmitted to a video processing unit after electrostatic discharge protection and impedance matching are finished by a digital signal receiving and processing unit;
when the input video signals are display drawing array and green synchronous video signals, the display drawing array and the green synchronous video signals are divided into two paths for transmission and processing after electrostatic discharge protection and impedance matching of the video images are completed through a display drawing array/green synchronous signal receiving and processing unit,
one path of the synchronous switching unit is used for transmitting the separated synchronous signals and the composite synchronous signals contained in the display drawing array video signals to the synchronous switching unit for synchronous switching and shaping, the synchronous switching unit is used for operating and selecting the composite signals or synchronous input of the display drawing array video signals according to a screen menu type adjusting mode of a user, the correct display drawing array synchronous video signals are transmitted to the sampling clock recovery unit so as to generate a sampling clock meeting analog-to-digital conversion sampling by frequency doubling, and then the sampling clock is input to the analog-to-digital conversion unit so as to provide a stable and reliable sampling clock for analog-to-digital conversion of the analog-to-digital conversion unit;
the other path inputs the display drawing array and the green synchronous video signal to a video signal amplifying unit for voltage amplification, then transmits the signals to an analog-to-digital conversion unit for analog-to-digital conversion, and transmits the digital signals output by the analog-to-digital conversion unit to the video processing unit;
when a composite signal is input, the composite signal is divided into two paths for transmission and processing, wherein,
one path inputs the composite signal to a composite signal receiving and processing unit for high-impedance isolation, then carries out low-pass filtering, then inputs the composite signal to a synchronous extraction unit for synchronous extraction, strips out the composite synchronous signal with only 0.3V, outputs the composite synchronous signal to the synchronous switching unit for synchronous switching and shaping in the level amplitude of 5VPP, selects the composite signal or displays the synchronous input of the video signal of the drawing array through the synchronous switching unit according to the operation of a screen menu type adjusting mode of a user, outputs the correct composite synchronous signal to a sampling clock recovery unit to generate a sampling clock meeting the sampling of analog-to-digital conversion, and then inputs the sampling clock to an analog-to-digital conversion unit to provide a stable and reliable sampling clock for the analog-to-digital conversion of the analog-to-digital conversion unit,
and the other path of the composite signal is transmitted to the video signal amplifying unit for voltage amplification, then transmitted to the analog-to-digital conversion unit for analog-to-digital conversion, and then transmitted to the video processing unit.
2. The method of claim 1, wherein: first, a video signal is input through a DVI-I interface.
3. The method of claim 2, wherein: when the composite signal of the 1VPP is input from the blue channel of the DVI-I interface, the composite signal is subjected to high-impedance isolation through an MOS (Q12), then is subjected to low-pass filtering, and then is input into a synchronous extraction unit for synchronous extraction.
4. The method of claim 3, wherein: and the composite signal which is subjected to high-impedance isolation by the MOS tube (Q12) and then is subjected to low-pass filtering is input into an LM1881 video synchronization separation chip for synchronous extraction, and the LM1881 video synchronization separation chip strips out the composite synchronization signal only having 0.3V and outputs the composite synchronization signal to the synchronization switching unit for synchronous switching and shaping in the level amplitude of 5 VPP.
5. The method of claim 4, wherein: the LM1881 video synchronization separation chip strips out the composite synchronization signal only having 0.3V, and outputs the composite synchronization signal to the 74HC4052 chip for synchronous switching and shaping in the level amplitude of 5 VPP.
6. A port switching and signal processing circuit is characterized in that: comprises a digital signal receiving and processing unit for electrostatic discharge protection and impedance matching, a display drawing array \ green synchronous signal receiving and processing unit for electrostatic discharge protection and impedance matching, and a composite signal receiving and processing unit for high-impedance isolation and low-pass filtering, wherein,
the output end of the digital signal receiving and processing unit is connected with a video processing unit,
the output end of the display drawing array/green synchronous signal receiving and processing unit is respectively connected with a video signal amplifying unit and a synchronous switching unit, the video signal amplifying unit amplifies the voltage of the signals, the display drawing array/green synchronous signal receiving and processing unit transmits the separated synchronous signals and the composite synchronous signals contained in the display drawing array video signals to the synchronous switching unit for synchronous switching and shaping,
the output end of the video signal amplifying unit is connected with an analog-to-digital conversion unit, the output end of the analog-to-digital conversion unit is connected with the input end of the video processing unit, the output end of the synchronous switching unit is connected with a sampling clock recovery unit, the output end of the sampling clock recovery unit is connected with the input end of the analog-to-digital conversion unit, the output end of the composite signal receiving and processing unit is connected with a synchronous extraction unit, the output end of the synchronous extraction unit is connected with the input end of the synchronous switching unit, wherein,
the synchronous extraction unit strips a composite synchronous signal with only 0.3V, then outputs the composite synchronous signal to the synchronous switching unit for synchronous switching and shaping in a level amplitude of 5VPP, the synchronous switching unit selects the composite signal or displays synchronous input of a drawing array according to the operation of a screen menu type adjustment mode of a user, outputs a correct synchronous signal to the sampling clock recovery unit, multiplies the frequency to generate a sampling clock meeting analog-to-digital conversion sampling, and then inputs the sampling clock to the analog-to-digital conversion unit to provide a stable and reliable sampling clock for analog-to-digital conversion of the analog-to-digital conversion unit.
7. The port switching and signal processing circuit of claim 6, wherein: the port switching and signal processing circuit comprises a DVI-I interface, and the digital signal receiving and processing unit, the display and drawing array \ green synchronous signal receiving and processing unit, the composite signal receiving and processing unit and the video signal amplifying unit are respectively connected with the DVI-I interface.
8. The port switching and signal processing circuit of claim 7, wherein: the composite signal receiving and processing unit comprises an MOS (Q12) tube, the grid electrode of the MOS tube (Q12) is connected with the blue channel of the DVI-I interface, the drain electrode of the MOS tube (Q12) is connected between the output end of the display drawing array/green synchronous signal receiving and processing unit and the input end of the video signal amplifying unit, and the source electrode of the MOS tube (Q12) is connected with the input end of the synchronous extraction unit.
9. The port switching and signal processing circuit of claim 8, wherein: the synchronous extraction unit comprises an LM1881 video synchronous separation chip, the source electrode of the MOS tube (Q12) is connected with the input end of the LM1881 video synchronous separation chip, and the CSOUT end of the LM1881 video synchronous separation chip is connected with the input end of the synchronous switching unit.
10. The port switching and signal processing circuit of claim 9, wherein: the synchronous switching unit comprises a 74HC4052 chip, the CSOUT end of the LM1881 video synchronous separation chip is connected with the 2Y1 end of the 74HC4052 chip, the separation synchronous signal output by the display drawing array \ green synchronous signal receiving and processing unit comprises a vertical synchronous signal and a horizontal synchronous signal, the vertical synchronous signal is connected with the 1Y0 end of the 74HC4052 chip, and the horizontal synchronous signal is connected with the 2Y0 end of the 74HC4052 chip.
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| CN104424911B (en) * | 2013-08-26 | 2016-08-31 | 英业达科技有限公司 | Video graphics array (VGA) interface protective circuit |
| CN106713809A (en) * | 2016-12-28 | 2017-05-24 | 中国科学院长春光学精密机械与物理研究所 | Video format conversion device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2876893Y (en) * | 2006-02-24 | 2007-03-07 | 环达电脑(上海)有限公司 | High grade digital display interface converting card device for computer |
| CN200980136Y (en) * | 2006-03-21 | 2007-11-21 | 高炳海 | A television-computer converter |
| CN101349984A (en) * | 2007-07-17 | 2009-01-21 | 鸿富锦精密工业（深圳）有限公司 | Device for testing video graphics interface |
| CN201869304U (en) * | 2010-12-07 | 2011-06-15 | 深圳市巨潮科技有限公司 | Port switching and signal processing circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200725475A (en) * | 2005-12-29 | 2007-07-01 | Inventec Corp | Sharing method of display chip |
| TWI419006B (en) * | 2007-09-21 | 2013-12-11 | Mstar Semiconductor Inc | Quick port switching method and associated apparatus |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2876893Y (en) * | 2006-02-24 | 2007-03-07 | 环达电脑(上海)有限公司 | High grade digital display interface converting card device for computer |
| CN200980136Y (en) * | 2006-03-21 | 2007-11-21 | 高炳海 | A television-computer converter |
| CN101349984A (en) * | 2007-07-17 | 2009-01-21 | 鸿富锦精密工业（深圳）有限公司 | Device for testing video graphics interface |
| CN201869304U (en) * | 2010-12-07 | 2011-06-15 | 深圳市巨潮科技有限公司 | Port switching and signal processing circuit |
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