CN102004220A - Method and system for testing chips - Google Patents
Method and system for testing chips Download PDFInfo
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- CN102004220A CN102004220A CN 200910194788 CN200910194788A CN102004220A CN 102004220 A CN102004220 A CN 102004220A CN 200910194788 CN200910194788 CN 200910194788 CN 200910194788 A CN200910194788 A CN 200910194788A CN 102004220 A CN102004220 A CN 102004220A
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Abstract
The invention provides a method and a system for testing chips. The method comprises the following steps of: testing n chips partitioned from a wafer to obtain n groups of test data, wherein each group of the test data comprises f types of test data; dividing the n groups of the test data into m compression groups, wherein each compression group comprises complete group test data; compressing each type of the test data in each compression group according to a certain functional relation respectively; storing results of the compression; and analyzing the stored test data, wherein m, n and f are natural numbers and n is bigger than m.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of method of testing of chip and system.
Background technology
At present, in field of semiconductor manufacture, after the manufacturing of finishing chip, need chip is tested, obtain the electrology characteristic of chip, obtain chip quality from described electrology characteristic, for example yield.
For example disclose a kind of IC-card chip and module chip test macro in the Chinese patent application of " 03115212.0 ", can IC-card have been tested, can carry out the test of various electrical properties easily according to user's requirement at application number.
In test; usually can test the every electric property and the reliability of chip; requirement with the user compares then; just be specification product if reach user's requirement; record is by mark (pass); just be not substandard product if reach customer requirements, write down defective mark (fail), the above-mentioned WS that also is called tests (wafer Sort tests).Above-mentioned test will be carried out the test of a large amount of kinds to each chip, and to test each sheet chip, therefore the data volume of the test result that obtains in test process is very huge, for example the test data for a chip just reaches 40MB-50MB, that have even surpass 100M, therefore will reach 4TB-5TB in 6 months to above-mentioned data storage, therefore only short-term reservation of the test data of all electrology characteristics usually, the time that for example keeps 1-2 week, and the information (also being called the CP data) of pass or fail is stored, the data that occupy so just significantly reduce, and for example same six months data volume is 150GB.
But, so just make the test data of original every electric property lose, therefore when chip is defective, just can't obtain the underproof reason of chip to test data analysis.
Summary of the invention
The invention solves the technical matters that can't obtain the underproof reason of chip to test data analysis.
In order to address the above problem, the invention provides a kind of method of testing of chip, comprise step: n the chip that wafer is partitioned into tested, and each chip carries out the test of f kind, obtains n group test data, and every group comprises f kind test data; N is organized test data be divided into m compressor units, comprise the test data of complete group in each compressor units; Each test data in each compressor units is compressed according to certain functional relation respectively; The result of described compression is stored; Test data to described storage is analyzed; Wherein m, n and f are natural number, and n is greater than m.
Optionally, described funtcional relationship comprises: ask arithmetical mean and ask in the geometric mean any one.
Optionally, describedly n is organized m equals 5 in the method that test data is divided into m compressor units, respectively 5%n is organized data, 20%n group data, 25%n group data, 25%n group data, 25%n group data and be divided into 5 compressor units.
Optionally, described test data is the test data that exceeds customer requirement value certain limit.
Corresponding the present invention also provides a kind of storage system of test data of chip, comprise: test cell, be used for n chip testing that wafer is partitioned into, wherein each chip carries out the test of f kind, obtain n group test data, every group comprises f kind test data: grouped element, and n is organized test data be divided into m compressor units, comprise the test data of complete group in each compressor units; Compression unit is used for each test data of each compressor units is compressed according to certain functional relation respectively; Storage unit is used for the result of described compression is stored; Analytic unit is used for the test data of described storage is analyzed; Wherein m, n and f are natural number, and n is greater than m.
Optionally, described compression unit comprises:
The arithmetic mean counting unit is used to ask arithmetical mean; Or
The geometric mean counting unit is used to ask geometric mean.
Optionally, described grouped element is organized test data with n and is divided into that m equals 5 in m the compressor units, respectively 5%n is organized data, 20%n group data, 25%n group data, 25%n group data, 25%n group data and is divided into 5 compressor units.
Optionally, described test data is the test data that exceeds customer requirement value certain limit.
Compare with prior art, the invention has the advantages that:
The present invention is by being divided into compressor units with test data, compress according to certain funtcional relationship then, so just make that data volume reduces greatly, but its data message that comprises is not lost, because in the time need analyzing to the data message of chip, can analyze the data after the compression, therefore be convenient to analyze the underproof reason of acquisition chip.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by physical size equal proportion convergent-divergent.
Fig. 1 is the process flow diagram of the method for testing of chip of the present invention;
Fig. 2 is the structural representation of the test macro of chip of the present invention.
Embodiment
Can know from background technology, in field of semiconductor manufacture, after the manufacturing of finishing chip, need chip is tested, obtain the electrology characteristic of chip, obtain chip quality from described electrology characteristic, for example yield.
In test; usually can test the every electric property and the reliability of chip; requirement with the user compares then; if reach user's requirement; be specification product just in the required value certain limit just, record is by mark (pass), if do not reach customer requirements; just exceed customer requirement value certain limit just for substandard product, write down defective mark (fail).Because the data volume of test is very huge, therefore the total data of test is not stored usually, make the test data of original every electric property lose like this, therefore when chip is defective, just can't obtain the underproof reason of chip test data analysis.
The present inventor thinks after research, under the underproof situation of chip, also need the performance of chip is done further to analyze, reached user's requirement in addition as fruit chip, the possibility performance has just reached user's requirement under the just qualified situation, its performance of possibility like this is also relatively poor, but owing to test data is lost, but therefore can't find that these reach the chip of qualified requirement poor-performing, and can't analyze the reason of its poor-performing.
Therefore the present inventor provides a kind of method of testing of chip, comprises step: n the chip that wafer is partitioned into tested, and each chip carries out the test of f kind, obtains n group test data, and every group comprises f kind test data; N is organized test data be divided into m compressor units, comprise the test data of complete group in each compressor units; Each test data in each compressor units is compressed according to certain functional relation respectively; The result of described compression is stored; Test data to described storage is analyzed; Wherein m, n and f are natural number, and n is greater than m.
Optionally, described funtcional relationship comprises: ask arithmetical mean and ask in the geometric mean any one.
Optionally, describedly n is organized m equals 5 in the method that test data is divided into m compressor units, respectively 5%n is organized data, 20%n group data, 25%n group data, 25%n group data, 25%n group data and be divided into 5 compressor units.
Optionally, described test data is the test data that exceeds customer requirement value certain limit.
Corresponding the present invention also provides a kind of test macro of chip, comprising: test cell, be used for n chip testing that wafer is partitioned into, and wherein each chip carries out the test of f kind, obtains n and organizes test data, and every group comprises f kind test data; Grouped element is organized test data with n and is divided into m compressor units, comprises the test data of complete group in each compressor units; Compression unit is used for each test data of each compressor units is compressed according to certain functional relation respectively; Storage unit is used for the result of described compression is stored; Analytic unit is used for the test data of described storage is analyzed; Wherein m, n and f are natural number, and n is greater than m.
Optionally, described compression unit comprises:
The arithmetic mean counting unit is used to ask arithmetical mean; Or
The geometric mean counting unit is used to ask geometric mean.
Optionally, described grouped element is organized test data with n and is divided into that m equals 5 in m the compressor units, respectively 5%n is organized data, 20%n group data, 25%n group data, 25%n group data, 25%n group data and is divided into 5 compressor units.
Optionally, described test data is the test data that exceeds customer requirement value certain limit.
The present invention is by being divided into compressor units with test data, compress according to certain funtcional relationship then, so just make that data volume reduces greatly, but its data message that comprises is not lost, because in the time need analyzing to the data message of chip, can analyze the data after the compression, therefore be convenient to analyze the underproof reason of acquisition chip.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes synoptic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the sectional view of expression device architecture can be disobeyed general ratio and be done local the amplification, and described synoptic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 1 is the process flow diagram of the method for testing of chip of the present invention, describes below with reference to Fig. 1.
As shown in Figure 1, the storage means of test data of chip comprises the following steps:
S10: n the chip that wafer is partitioned into tested, and each chip carries out the test of f kind, obtains n group test data, and every group comprises f kind test data.
Usually be unit with a wafer when chip manufacturing, a wafer is divided into several zones, for example n zone utilizes identical processing procedure to form 1 chip in each zone then.After chip manufacturing is finished, wafer is cut apart, for example be divided into n chip, n the chip that same wafer is partitioned into tested then, test to each chip can obtain one group of test data, therefore obtain n group test data altogether, each chip generally can carry out multiple test, for example power consumption, electric current, voltage or the like f kind test, therefore each chip can obtain f kind test data, and just every group of test data comprises f kind data.
In the present embodiment, only need record to compare, exceed the test data of customer requirement value certain limit with requirement of client.Described certain limit can be provided with according to actual conditions, for example can be set to the acceptability limit of customer requirement, also can be set to the interior littler scope of acceptability limit of customer requirement, be not beneficial to like this when also substandard product occurring and in time pinpoint the problems, improve the quality of chip.
S20: n is organized test data be divided into m compressor units, comprise the test data of complete group in each compressor units.
Concrete, the n group test data of n the chip that same wafer is partitioned into is divided into groups, can be divided into m compressor units, for example 2,3,4,5...... is because the chip of making on the same wafer has experienced identical manufacturing process, therefore its electric property is more approaching, like this test data of the chip made on the same wafer is compressed, for example asked average, this mean value is analyzed just obtained the underproof reason of this batch chip so.
Preferably, n organized m equals 5 in the method that test data is divided into m compressor units, respectively 5%n is organized data, 20%n group data, 25%n group data, 25%n group data, 25%n group data and be divided into 5 compressor units.For example n equals 100, and 100 groups of test datas are divided into 5 compressor units, so just 5 groups of data, 20 groups of data, 25 groups of data, 25 groups of data, 25 groups of data is divided into 5 compressor units.
Preferably, the method that described n group test data is divided into m compressor units is according to distributing the position of chip on the wafer, for example wafer is divided into m zone from the center of circle along radius, wherein be in the circle that is of wafer center, other is an annular, the test data that is in the chip in the same described zone is so assigned to same compressor units, if be divided into 5 zones, compressor units just is 5.Because wafer is circular, therefore the regional processing procedure that is in manufacturing process on the same circumference band of wafer is more approaching, therefore the chip performance of making is more approaching, like this test data of the chip made from the zone on the same circumference band be divided into that a compressor units compresses can be so that data and real data after the compression be more approaching.
Certainly, in other embodiment, can also utilize the mode of other grouping, for example n be organized the test data mean allocation, just the n/m group is a compressor units, altogether m compressor units.
S30: each test data in each compressor units is compressed according to certain functional relation respectively.
Concrete, for example have 5 compressor units, 20 groups test data is arranged in each compressor units, and every group comprises 10 kinds of test datas, can utilize the method for asking arithmetical mean like this, in 1 compressor units, just the same a kind of test data in 20 groups is asked arithmetical mean, and for example the test data in every group an of compressor units all comprises power consumption, just comprises 20 power consumption data so in each compressor units, these 20 power consumption data are asked arithmetical mean, and data have just been compressed 20 times like this.Equally the test data of all kinds in this compressor units is all asked arithmetical mean, all compressor units are all asked arithmetical mean according to the method described above, all like this test datas just are compressed to original 1/20th.
Also can for example adopt and ask the method for geometric mean or other the average method of asking to compress, for example square mean number or arithmetic square root or the like in other embodiments according to other funtcional relationship.
After utilizing above-mentioned method that data are compressed, data volume reduces greatly, but the information that has but kept test data in the data volume after compression, for example cause when defective because power is excessive, can be by the arithmetical mean of the power consumption in this compressor units be analyzed, test data in for example same compressor units derives from the same circumference band of wafer, therefore the performance of the chip of making on this circumference band is more approaching, if power consumption is excessive, power consumption in possible this compressor units is all bigger, therefore also the required value than the user is big for the mean value of power consumption, therefore this mean value is just analyzed and can be known underproof reason.
And, work as test data, for example power consumption is in the scope of customer requirement, but it is bigger to depart from the customer requirement value, for example at the edge of required value, this can't judge in the prior art, because only will exceed be labeled as " fail " of customer requirement scope in the prior art, being labeled as in the customer requirement scope " pass ", and just can not analyze again in the customer requirement scope, for example be offset bigger also can't the judging of customer requirement value, also do not analyze.But utilize storage means of the present invention, because stored all test datas, and be not only the information of fail and pass, so just can be to the test data of fail and pass but but departing from the bigger test data of customer requirement value analyzes, thereby before fail, pinpoint the problems timely, avoid the appearance of fail.
S40: the result of described compression is stored, and wherein m, n and f are natural number, and n is greater than m.
Concrete, will store in the data after step S20 is according to the certain functional relation compression, for example store in the storage medium.Because data volume reduces greatly after the data compression, therefore saved storage space greatly, so just the test data of chip can be preserved the long period, long preservation for example, thereby when chip is defective, its underproof reason is analyzed, be used to avoid the defective problem of next group chip.Therefore the storage means of test data of chip of the present invention has been saved storage space greatly, the long preservation of the test data of assurance, thus can be by timely data analysis having been improved chip quality.
S50: the test data to described storage is analyzed.
Concrete, can adopt analytical approach well-known to those skilled in the art.In the present embodiment, can be both can analyze the test parameter of the scope that exceeds customer requirement, just defective, the chip of record fail.Also can analyze in addition, just depart from the requirement of client value, but in the customer requirement scope, be marked as the chip of " pass " departing from the bigger test parameter of customer requirement value.
Accordingly, the present invention also provides a kind of test macro of chip, and Fig. 2 is the structural representation of the storage system of test data of chip of the present invention, and with reference to figure 2, the storage system of test data of chip comprises:
Preferably, described compression unit comprises: the arithmetic mean counting unit is used to ask arithmetical mean; Or the geometric mean counting unit, be used to ask geometric mean.
Preferably, described grouped element n is organized m equals 5 in the method that test data is divided into m compressor units, respectively 5%n is organized data, 20%n group data, 25%n group data, 25%n group data, 25%n group data and is divided into 5 compressor units.
Preferably, described test data is the test data that exceeds customer requirement value certain limit.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (8)
1. the method for testing of a chip is characterized in that, comprises step:
N the chip that wafer is partitioned into tested, and each chip carries out the test of f kind, obtains n group test data, and every group comprises f kind test data;
N is organized test data be divided into m compressor units, comprise the test data of complete group in each compressor units;
Each test data in each compressor units is compressed according to certain functional relation respectively;
The result of described compression is stored;
Test data to described storage is analyzed;
Wherein m, n and f are natural number, and n is greater than m.
2. method of testing according to claim 1 is characterized in that, described funtcional relationship comprises: ask arithmetical mean and ask in the geometric mean any one.
3. method of testing according to claim 1, it is characterized in that, describedly n is organized m equals 5 in the method that test data is divided into m compressor units, respectively 5%n is organized data, 20%n group data, 25%n group data, 25%n group data, 25%n group data and be divided into 5 compressor units.
4. method of testing according to claim 1 is characterized in that, described test data is the test data that exceeds customer requirement value certain limit.
5. the test macro of a chip is characterized in that, comprising:
Test cell is used for n chip testing that wafer is partitioned into, and wherein each chip carries out the test of f kind, obtains n group test data, and every group comprises f kind test data;
Grouped element is organized test data with n and is divided into m compressor units, comprises the test data of complete group in each compressor units;
Compression unit is used for each test data of each compressor units is compressed according to certain functional relation respectively;
Storage unit is used for the result of described compression is stored;
Analytic unit is used for the test data of described storage is analyzed;
Wherein m, n and f are natural number, and n is greater than m.
6. storage system according to claim 5 is characterized in that, described compression unit comprises:
The arithmetic mean counting unit is used to ask arithmetical mean; Or
The geometric mean counting unit is used to ask geometric mean.
7. test macro according to claim 6, it is characterized in that, described grouped element is organized test data with n and is divided into that m equals 5 in m the compressor units, respectively 5%n is organized data, 20%n group data, 25%n group data, 25%n group data, 25%n group data and is divided into 5 compressor units.
8. test macro according to claim 6 is characterized in that, described test data is the test data that exceeds customer requirement value certain limit.
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| CN 200910194788 CN102004220B (en) | 2009-08-28 | 2009-08-28 | Method and system for testing chips |
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| CN 200910194788 CN102004220B (en) | 2009-08-28 | 2009-08-28 | Method and system for testing chips |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105574039A (en) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Wafer test data processing method and system |
| CN105676105A (en) * | 2014-11-19 | 2016-06-15 | 比亚迪股份有限公司 | Chip test method and chip test machine |
| CN104183511B (en) * | 2013-05-21 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of method and crystal grain labeling method of the boundary for determining wafer sort data standard |
| CN108693456A (en) * | 2018-04-09 | 2018-10-23 | 马鞍山杰生半导体有限公司 | A kind of chip wafer test method |
-
2009
- 2009-08-28 CN CN 200910194788 patent/CN102004220B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183511B (en) * | 2013-05-21 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of method and crystal grain labeling method of the boundary for determining wafer sort data standard |
| CN105574039A (en) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Wafer test data processing method and system |
| CN105574039B (en) * | 2014-10-16 | 2019-05-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of processing method and system of wafer test data |
| CN105676105A (en) * | 2014-11-19 | 2016-06-15 | 比亚迪股份有限公司 | Chip test method and chip test machine |
| CN108693456A (en) * | 2018-04-09 | 2018-10-23 | 马鞍山杰生半导体有限公司 | A kind of chip wafer test method |
| CN108693456B (en) * | 2018-04-09 | 2021-07-20 | 马鞍山杰生半导体有限公司 | Wafer chip testing method |
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