CN101997412A - Control method - Google Patents

Abstract

A control method is suitable for controlling an output power supply of a switch type power supply to provide constant current. The switch-mode power supply includes a winding coupled to an input power source. The winding is controlled by a switch to store or release energy. The control method comprises the following steps: making the peak value of the maximum current flowing through the winding be a preset value; detecting a discharge time of the winding in a switching period; and controlling the switching period of the switch such that the ratio of the discharge time to the switching period of the switch is approximately equal to a fixed value.

Description

Control Method

technical field

The present invention relates to a switching-mode power supply (SMPS) and related operating methods.

Background technique

SMPS is already a power supply used by most consumer electronic devices. It controls the energy storage and release in the winding through the switching of a power switch to provide output power that meets the specification requirements. For example, under light load or no load, SMPS may need to operate in constant voltage mode, providing a constant voltage source that is roughly independent of the output current; while under heavy load (heavy load), it operates in constant current mode, providing a constant current source that is roughly independent of the output voltage.

FIG. 1 shows a known SMPS 10, which can provide constant voltage mode and constant current mode by means of primary side control. The SMPS 10 is a flyback architecture. A bridge rectifier (bridge rectifier) 12 roughly rectifies the AC power V _AC into an input power V _IN , and the primary winding 24 of the transformer 20, the power switch 15, and the current detection resistor 36 are connected in series to the input power V _IN and a ground wire. When the switch controller 18 turns on (ON) the power switch 15, the primary side winding 24 starts to increase the energy storage therein; when the switch controller 18 turns off (OFF) the power switch 15, the transformer 20 passes through its secondary winding (secondary winding) 22 and the auxiliary winding (auxiliary winding) 25 are released. The rectifier 16 and the capacitor 13 roughly rectify the electric energy released by the secondary winding 22 to provide an output power V _OUT to the output load 38 . The rectifier 28 and the capacitor 34 roughly rectify the electric energy released by the auxiliary winding 25 to provide an operating power V _CC to the switch controller 18 . The startup resistor 26 provides the current required by the switch controller 18 at the beginning; the voltage divider resistors 30 and 32 provide the switch controller 18 with the reflected voltage on the auxiliary winding 25 after being divided. . The reflected voltage on the auxiliary winding 25 approximately corresponds to the voltage across the secondary winding 22, so through the voltage dividing resistors 30 and 32, the switch controller 18 can know the voltage across the secondary winding 22 and control the power switch 15 accordingly. .

FIG. 2 shows part of a known switch controller 18a for constant voltage mode. A sampling circuit (sample/hold circuit) 42 samples the voltage from the FB pin when the power switch 15 is turned off, and generates a feedback voltage V _FB . An error amplifier (error amplifier) 44 compares the feedback voltage V _FB with the reference voltage V _REF1 to generate a compensation voltage V _COM . The comparator 50 compares the compensation voltage V _COM and the detection voltage V _CS , and the comparator 52 compares the current limit voltage V _CS-LIMIT and the detection voltage V _CS . The result outputs of the comparators 50 and 52 and the clock output of the oscillator 46 are coupled to a gate logic controller 48 for controlling the power switch 15 through the GATE pin. Through the negative feedback loop, the feedback voltage V _FB of FIG. 2 is controlled to be approximately equal to the reference voltage V _REF1 .

Although the circuit related to the constant current mode is not shown in FIG. 2 , in the known art, there are many SMPSs and their control methods that teach the constant current mode.譬如美国专利编号US 7016204-Close-loop PWM controller for primary-side controlled powerconverters、US7388764-Primary side constant output current controller、US7110270-Method and apparatus for maintaining a constant load current withline voltage in a switch mode power supply、US7505287- On-time control for constant current mode in a flyback power supply etc.

Contents of the invention

An embodiment of the present invention provides a control method suitable for controlling a switching power supply. The switching power supply includes a transformer coupled to an input power supply. The transformer is controlled by a switch to store or release energy to generate an output power. The control method includes: providing a capacitor; using the capacitor to store a difference between an actual charge amount and an estimated charge amount, wherein the actual charge amount corresponds to the total charge amount flowing through the transformer during a switching cycle of the switch , the estimated amount of charge is the total estimated amount of the actual amount of charge in the switching cycle; and, according to the voltage of the capacitor, one of the actual amount of charge and the estimated amount of charge is changed in a subsequent switching cycle , so that in the subsequent switching period, the actual charge amount is approximately equal to the estimated charge amount.

An embodiment of the present invention provides a constant current control method suitable for a switching power supply. The switching power supply includes a switch and a winding, which are connected in series and connected to an input power supply. The switching power supply provides an output power. The constant current control method includes: providing a first negative feedback loop to detect the winding current flowing through the winding, and generating an estimated average current approximately corresponding to the average current flowing through the winding; and, providing a first Two negative feedback loops, based on the estimated average current, so that the average output current of the output power supply is approximately a preset average output current value.

An embodiment of the present invention provides a method of generating a real current source representing the average current of a winding, suitable for a switching power supply, which includes the winding. The method includes: detecting the winding current flowing through the winding to generate a detection voltage; comparing the detection voltage with an average voltage; when the detection voltage is greater than the average voltage, using a first current source to a capacitor charging or discharging; when the detected voltage is less than the average voltage, discharge or charge the capacitor with a second current source; change the average voltage according to the voltage of the capacitor; and, according to the average voltage, correspondingly generate the actual current source.

An embodiment of the present invention provides a control method suitable for controlling a switching power supply to provide a constant current output power. The switching power supply includes a winding coupled to an input power. The winding is controlled by a switch to store or discharge energy. The control method includes: making the maximum current peak value flowing through the winding a preset value; detecting a discharge time of the winding in a switching cycle; and controlling the switching cycle of the switch so that the discharging time is consistent with the The ratio of the switching period of the switch is approximately equal to a constant value.

An embodiment of the present invention provides a constant current constant voltage power converter, which includes a constant current feedback loop and a constant voltage feedback loop. Wherein the constant current feedback loop and the constant voltage feedback loop share a compensation capacitor.

An embodiment of the present invention provides a switch controller suitable for a switching power supply. The switching power supply includes a transformer coupled to an input power supply. The transformer is controlled by a switch to store or discharge energy to generate an output power supply. The switch controller includes a capacitor, an actual current source, an estimated current source, and a feedback device. The actual current source charges the capacitor corresponding to an actual current flowing through the transformer, and generates an actual charge in a switching cycle. The estimated current source discharges the capacitor corresponding to an estimated current, and generates an estimated amount of charge during the switching period. The feedback device changes the actual charge amount or the estimated charge amount according to the voltage of the capacitor, so that in a subsequent switching cycle, the estimated charge amount is close to the actual charge amount.

An embodiment of the present invention provides a switch controller suitable for a switch mode power supply. The switching power supply includes a switch and a winding, which are connected in series and connected to an input power supply. The switching power supply provides an output power. The switch controller includes a first negative feedback loop and a constant current controller. The first negative feedback loop senses the winding current flowing through the winding and generates an estimated average current approximately corresponding to the average current flowing through the winding. The constant current controller is used to form a second negative feedback loop, and according to the estimated average current, the average output current of the output power supply is approximately a preset average output current value.

An embodiment of the present invention provides an average voltage detector suitable for a switching power supply, which includes a winding and a current detector. The current detector detects the current flowing through the winding to generate a corresponding detection voltage. The average voltage detector includes a capacitor, a charging current source, a discharging current source, and a refreshing device. The charging current source charges the capacitor. The discharge current source discharges the capacitor. The refreshing device adjusts a voltage average value with the voltage of the capacitor. When the detection voltage is higher than the average voltage, the capacitor is charged. When the detection voltage is lower than the average voltage, the capacitor is discharged.

Description of drawings

FIG. 1 is a known switching power supply.

Fig. 2 shows a part of the circuit in constant voltage mode of a known switching controller.

FIG. 3 is a switch controller implemented according to the present invention.

Figure 4 shows a discharge time detector.

Figure 5 shows a constant current controller.

FIG. 6 shows a timing diagram of the embodiment according to FIG. 1 and FIG. 3 .

Figure 7 and Figure 8 show two other constant current controllers.

FIG. 9 is a switch controller implemented according to the present invention.

Figure 10 is a voltage peak detector implemented in accordance with the present invention.

Fig. 11 is a constant current controller implemented according to the present invention.

Figure 12 is a voltage-to-current converter.

13 and 14 are two-switch controllers implemented according to the present invention.

Fig. 15 is a switch controller implemented according to the present invention.

Figure 16 is a constant current controller implemented in accordance with the present invention.

Figure 17 and Figure 18 show two average voltage detectors.

Figure 19 is another peak controller implemented in accordance with the present invention.

Fig. 20 is another switch controller implemented in accordance with the present invention.

[Description of main component symbols]

10 Switching Mode Power Supply

12 Bridge Rectifier

13, 34 Capacitance

15 Power switch

16, 28 rectifier

18, 18a, 18b, 18c, 18d, 18e, switch controller

18f

20 Transformer

22 Secondary side winding

24 Primary side winding

25 Auxiliary winding

26 Starting resistor

30, 32 Voltage divider resistor

36 Current Sense Resistor

38 Output load

42 Sampling circuit

44 Error Amplifier

46 Oscillator

48 Gate logic control circuit

50, 52 Comparator

102, 102a Discharge time detector

104, 104a, 104b, 104c, 310, 310a constant current controller

106 Voltage Controlled Oscillator

108 CS peak controller

110 Comparator

112 Inverter

114 AND gate

116 Pulse generator

118 Actual current source

120 Estimated current source

122, 124 Capacitance

126 switch

140, 142 Comparator

144 counter

146 Digital to Analog Converter

202, 202a Constant current controller

204, 204a Voltage-to-current converter

206, 206a Voltage peak detector

302 Error Amplifier

306, 306a, 306b average voltage detector

364, 366 Constant current source

366, 368, 382, 384 capacitors

386, 388 Voltage-to-current converters

_ISEC current

I _CON preset current value

V _{AC AC} power supply

V _CS-AVG voltage average

V _IN input power supply

V _OUT output power supply

V _CC operating power

V _FB feed voltage

V _REF1 , V _REF-CC reference voltage

V _COM compensation voltage

V _CS detection voltage

V _CS-LIMIT current limit voltage

V _AUX sense voltage

V _TH Threshold Voltage

_VCC-CAP voltage

V _GATE gate voltage

S _DIS discharge signal

S _SMP pulse signal

T _DIS discharge time

V _CTL control voltage

T switching period

Detailed ways

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail with accompanying drawings.

For the convenience of description, equivalent or similar functions will be denoted by the same symbol. Therefore, elements with the same symbol in different embodiments do not mean that the two elements are necessarily the same. The scope of the present invention should be determined based on the scope of protection required by the claims.

FIG. 3 shows a switch controller 18b implemented according to the present invention, which can replace the switch controller 18 in FIG. 1 to realize constant current and constant voltage control. The following explanation assumes that the switch controller 18b of FIG. 3 is used in FIG. 1, and that the SMPS 10 of FIG. 20% of the electric energy will be completely discharged.

The constant voltage control operation in the switch controller 18b is similar to the switch controller 18a in FIG. 2 , which can be deduced by those skilled in the art from FIG. 2 , and will not be repeated here.

The difference between Fig. 3 and Fig. 2 is that Fig. 3 has a CS peak controller 108, a discharge time detector 102, a constant current controller 104, and a voltage-controlled oscillator (VCO) 106, and these devices can It is suitable for constant current control operation, so that the current obtained by the output load 38 is approximately the predetermined constant current I _OUT-SET .

The CS peak controller 108 effectively sets the highest peak current flowing through the secondary winding 22 to a predetermined value I _SEC-SET . The discharge time detector 102 generates a discharge signal S _DIS through the FB pin and the induced voltage V _AUX of the auxiliary winding 25 as a result of detecting the discharge time T _DIS of the secondary winding 22 . According to the discharge time T _DIS provided by the discharge signal S _DIS and the switching period T provided by the Gate pin, the constant current controller 104 can know the secondary-side voltage output by the secondary-side winding 22 in the current switching period T. Whether the amount of charge is equal to the total estimated amount of charge generated by the predetermined constant current I _OUT-SET in the switching period T. If there is a difference, the control voltage V _CTL will be changed, thereby changing the clock frequency output by the voltage controlled oscillator 106 . The changed clock frequency affects the next switching cycle T, which in turn affects the total estimated charge in the next switching cycle, forming a negative feedback loop, the purpose of which is to make the subsequent total estimated charge converge to equal to the secondary side charge. Such a negative feedback loop can make the average output current of the secondary winding 22 converge to approximately equal to the predetermined constant current I _OUT-SET , thereby achieving the purpose of constant current control.

The CS peak controller 108 can make the highest peak current flowing through the current detection resistor 36 in FIG. 1 be the preset value I _PRI-SET , and equivalently make the highest peak current flowing through the primary side winding 24 be the preset value I _{PRI -SET} . Since the ratio of the highest peak current of the primary side winding 24 to the highest peak current of the secondary side winding 22 will be equal to the turns ratio of the secondary side winding 22 to the primary side winding 24, the CS peak controller 108 equivalently causes the current flowing through The highest peak current of the secondary winding 22 is a preset value I _SEC-SET . For example, the CS peak controller 108 can make the peak value of the detection voltage V _CS not greater than the current limit voltage V _CS-LIMIT , such as 0.85 volts. An implementation of the CS peak controller 108 has been disclosed in US Patent Application No. 12/275,201, Taiwan Patent Application No. 097129355, and Chinese Patent Application No. 200810131240 by the same inventor. In the above application, the CS peak controller 108 uses a difference between the peak voltage of the current detection voltage V _CS and the current limit voltage V _CS-LIMIT , and then uses this difference to adjust the comparison voltage V compared with the detection voltage V _{CS CS-USE} , so that the detection voltage V _CS peak value in subsequent switching cycles is getting closer to the current limit voltage V _CS-LIMIT . At heavy load, after several switching cycles, the peak value of the detection voltage V _CS will converge to approximately equal to the current limit voltage V _CS-LIMIT . Therefore, the highest peak current of the secondary side winding 22 is correspondingly approximately equal to the preset value I _SEC-SET .

FIG. 19 is another CS peak controller 500, which can make the peak value of the detection voltage V _CS approximately equal to the peak limit voltage V _REF-LIMIT . When using the CS peak controller 500 of FIG. 19 with the CS peak controller 108 of FIG. 3 , the peak limit voltage V _REF-LIMIT is the current limit voltage V _CS-LIMIT . In one switching cycle, if the peak value of the detection voltage V _CS in Figure 19 is greater than the peak limit voltage V _REF-LIMIT , the capacitor 508 will be charged by the current source 510 to pull up the voltage V _BIAS , a higher V _BIAS will have a higher Current I _BIAS flows through resistor R _BIAS . Therefore, in the next switching cycle, the peak value of the detection voltage V _CS will be lower. If the detection voltage V _CS in Figure 19 is always lower than the peak limit voltage V _REF-LIMIT in a switching cycle, the capacitor 508 will discharge with a very small current through the BJT and the resistor R _LEAKAGE , and slightly reduce the voltage V _BIAS , Therefore, the detection voltage V _CS peak value of the next switching cycle is slightly raised. In design, the current I _R of the current source 510 is much larger than the leakage current caused by the BJT to the capacitor 508 . After several switching cycles, the peak value of the detection voltage V _CS will be approximately equal to the peak limit voltage V _REF-LIMIT .

FIG. 4 shows a discharge time detector 102a. When the discharge signal S _DIS is at a logic high level, it indicates that the transformer 20 in FIG. 1 is still passing through the rectifier 16 to discharge the output load 38 . When the discharge of the transformer 20 ends, the induced voltage on the FB pin will drop suddenly. Therefore, the sudden drop can be used to detect the end of discharge to determine the discharge time T _DIS . Therefore, in FIG. 4 , the comparator 110 compares the voltage on the FB pin with a threshold voltage V _TH . The discharge time T _DIS only occurs when the power switch 15 is turned off, so in FIG. 4 , the two input terminals of the AND gate 114 are respectively connected to the output terminal of the comparator 110 and the output terminal of the inverter 112 . The input terminal of the inverter 112 is connected to the GATE pin.

Figure 5 shows a constant current controller 104a. The current value ratio (I _REAL /I _EXP ) of the actual current source 118 and the estimated current source 120 is a preset ratio value N _RATIO . The actual current source 118 charges the capacitor 122 when the discharge signal S _DIS is at a logic high level, that is, during the discharge time T _DIS . During the discharge time T _DIS , the charge charged by the actual current source 118 to the capacitor 122 is referred to as the actual charge Q _RFAL . During the switching period T, the estimated current source 120 continues to discharge the capacitor 122 , and the discharged charge is referred to as an estimated amount of charge Q _EST . The pulse generator 116 triggers and sends out a pulse signal S _SMP when the voltage of the GATE pin rises, so that the capacitor 124 passes through the switch 126 to sample the voltage V _CC-CAP of the capacitor 122 to generate the control voltage V _CTL .

The voltage-controlled oscillator (VCO) 106 in FIG. 3 , for example, can be designed to reduce its oscillation frequency as the control voltage V _CTL increases, and also increase the switching period T at the same time.

Since the CS peak controller 108 in FIG. 3 has made the highest peak current flowing through the secondary side winding 22 the preset value I _SEC-SET , it can be assumed that when the constant current control needs to be active, the secondary side winding 22 The highest peak current value is the preset value I _SEC-SET . In the switching period T, the secondary-side electric charge Q _SEC output by the secondary-side winding 22 can be calculated according to the following formula (1):

Q _SEC ＝0.5*I _SEC-SET *T _DIS ..........(1)

For the desired constant current I _OUT-SET , in the switching period T, the total estimated charge output Q _OUT can be calculated by the following formula (2):

Q _OUT ＝I _OUT-SET *T......(2)

As a result of the constant current control operation, it is hoped that the secondary side charge quantity Q _SEC is equal to the total estimated charge quantity Q _OUT , that is, 0.5*I _SEC-SET *T _DIS is equal to I _OUT-SET *T.

In FIG. 5 , the current value ratio N _RATIO (=I _REAL /I _EXP ) of the actual current source 118 and the estimated current source 120 is designed to be equal to (0.5*I _SEC-SET /I _OUT-SET ), and the voltage V _CC- The variation of _CAP after switching period T (defined as ΔV _CC-CAP ) can be derived from the following formula:

ΔV _CC-CAP

＝(Q _REAL -Q _EST )/C _CC-CAP

＝(I _REAL *T _DIS -I _EXP *T)*K ₁

＝(0.5*I _SEC-SET *T _DIS -I _OUT-SET *T)*K ₂ ------(3)

＝(Q _SEC -Q _OUT )*K ₂ ------(4)

Wherein, K ₁ and K− ₂ are two constants, and C _CC-CAP is the capacitance value of the capacitor 122 .

Assuming that after the current switching period T, the voltage V _CC-CAP rises, that is, ΔV _CC-CAP is greater than zero, then according to formula (4), it can be deduced that in the current switching period T, the generated secondary side charge Q _SEC Exceeding the total estimated charge Q _OUT , that is, the actual output current is greater than the desired constant current I _OUT-SET . After the current switching period T, the rise of the voltage V _CC-CAP will lead to the rise of the control voltage V _CTL and cause the increase of the next switching period T. In this way, a negative feedback loop is formed. As long as the negative feedback loop is properly designed, the results of formulas (4) and (5) can approach zero as time goes by. In other words, the negative feedback loop adjusts the switching period T so that T/T _DIS is approximately equal to N _RATIO (=I _REAL /I _EXP ), so that Q _SEC -Q _OUT =0, and then achieves a constant current output Purpose.

Fig. 6 shows a timing diagram of the embodiment according to Fig. 1 and Fig. 3, wherein, from top to bottom, respectively, the gate voltage V _GATE on the GATE pin, the detection voltage V _CS on the CS pin, and the induced voltage V _AUX , the current I _SEC flowing through the secondary winding 22 , the discharge signal S _DIS , the pulse signal S _SMP , the control voltage V _CTL , and the voltage V _CC-CAP of the capacitor 122 . At time _t1 , the gate voltage V _GATE rises, the power switch 15 is turned on, and the transformer 20 starts charging, so the detection voltage V _CS starts to rise. The rising edge of the gate voltage V _GATE also triggers the pulse of the pulse signal S _SMP to generate the control voltage V _CTL generated by the sampling voltage V _CC-CAP . At this time, the capacitor 122 is slowly discharged so that the voltage V _CC-CAP gradually decreases. At time t ₂ , the drop of the gate voltage V _GATE will make the detection voltage V _CS equal to the current limit voltage V _CS-LIMIT , and correspondingly make the highest peak current flowing through the primary winding 24 be the preset value I _PRI-SET . At this time, corresponding to the highest peak current I _PRI-SET of the primary winding 24 , the current I _SEC flowing through the secondary winding 22 is a preset value I _SEC-SET . During the discharge time T _DIS between time t ₂ and time t ₃ , the transformer 20 is discharged, so the discharge signal S _DIS is at a high logic level. During the discharge time T _DIS , since the charging current of the capacitor 122 is greater than the discharging current, the voltage V _CC-CAP gradually rises. At time t ₃ , the discharge of the current I _SEC is completed, resulting in a sudden drop of the induced voltage V _AUX , so the discharge time T _DIS is defined, and the capacitor 122 stops being charged by the current. From time _t3 to the next discharge time, the capacitor 122 is slowly discharged so that the voltage V _CC-CAP gradually decreases. At time _t4 , enter the next switching cycle, the gate voltage V _GATE rises, and perform the same action as time _t1 . It can be known from FIG. 6 and the previous explanation that the rise of the control voltage V _CTL will increase the next switching cycle T, so that the rise of the control voltage V _CTL after the next switching cycle is less or reduced. Such a negative feedback loop will eventually stabilize the control voltage V _CTL at a stable value.

FIG. 7 shows another constant current controller 104b, which is similar to that of FIG. 5 and can achieve a similar purpose to that of FIG. 5 . Different from FIG. 5 , FIG. 7 has a comparator 140 whose main purpose is to compare the voltage V _CC-CAP of the capacitor 122 with the reference voltage V _REF-CC within the pulse time defined by the pulse signal S _SMP , and has a Generate charging or discharging current to adjust the control voltage V _CTL . For example, if it is found that the voltage V _CC-CAP is higher than the reference voltage V _REF-CC during the pulse time defined by the pulse signal S _SMP , then the comparator 140 charges the capacitor 124 during the pulse time to make the control voltage V _{The CTL} rises a little, and then the next switching period T is slightly increased.

FIG. 8 shows another constant current controller 104c, which is similar to that of FIG. 7 and can achieve a similar purpose to that of FIG. 7 . Different from FIG. 7 , FIG. 8 has a comparator 142 , a counter 144 , and a digital-to-analog converter 146 . The counter 144 is triggered by the rising edge of the gate voltage V _GATE , and counts up or down according to the output of the comparator 142 at that time. The digital-to-analog converter 146 converts the digital output of the counter 144 into an analog output, which is used as the control voltage V _CTL . For example, if it is found that the voltage V _CC-CAP is higher than the reference voltage V _REF-CC at the rising edge of the gate voltage V _GATE , then the counter 144 will count up to 1, so that the control voltage V _CTL is slightly increased, and then Slightly increase the next switching cycle T.

In the above embodiments of FIG. 5 , FIG. 7 and FIG. 8 , using a single capacitor 122 to record the difference between the actual charge Q _REAL and the estimated charge Q _EST has at least one advantage: the capacitance value of the capacitor 122 does not change Affects the rising or falling trend of the control voltage V _CTL . Therefore, the embodiments of FIG. 5 , FIG. 7 and FIG. 8 can allow the capacitance value of the capacitor 122 to vary.

FIG. 9 shows a switch controller 18c implemented according to the present invention, which can replace the switch controller 18 in FIG. 1 to implement constant current and constant voltage control operations. The following explanation assumes that the switch controller 18c of FIG. 9 is used in FIG. 1, and the SMPS 10 of FIG. 1 is operated in a dis-continuous conduction mode (DCM).

Figure 9 differs from Figure 3 in the following points. 1) There is no CS peak controller 108 in FIG. 9 , but the same comparator 52 as in FIG. 2 is used to roughly limit the peak value of the detection voltage V _CS . Because of problems such as signal delay and the rate of change of the detection voltage V _CS , when the comparator 52 acts to cause the power switch 15 to be turned off, it is impossible to make the voltage peak value V _CS-PEAK of the detection voltage V _CS just equal to the current limit voltage V _CS-LIMIT . 2) As shown in FIG. 9, a voltage peak detector 206 is added to detect the voltage peak value V _CS-PEAK of the voltage V _CS at the moment when the power switch 15 is turned off. And 3) the constant current controller 202 in FIG. 9 adjusts the control signal V _CTL according to the discharge signal S _DIS and the peak voltage V _CS-PEAK .

FIG. 10 is a voltage peak detector 206a implemented according to the present invention, which is applicable to the embodiment of FIG. 9 . In Fig. 10, the pulse generator and switch make the capacitor return to zero on the rising edge of the gate voltage V _GATE . When the detection voltage V _CS increases as the on-time of the power switch 15 increases, the voltage of the capacitor will follow the detection voltage V _CS . The voltage peak detector 206a in FIG. 10 can be understood by those with ordinary knowledge in the technical field, and will not be further described here.

FIG. 11 is a constant current controller 202a implemented according to the present invention, which can be applied to the embodiment in FIG. 9 . In the constant current controller 202 a of FIG. 11 , the actual current source 118 in the constant current controller 104 a of FIG. 5 is replaced by a voltage-to-current converter 204 . The voltage-to-current converter 204 converts the peak voltage V _CS-PEAK into a corresponding current having a value I _CSS-PEAK . I _CSS-PEAK corresponds to the peak voltage V _CS-PEAK , which corresponds to the peak current I _SEC-PEAK passing through the secondary winding 22 in the current switching cycle. In other words, I _CSS-PEAK will be proportional to the current peak I _SEC-PEAK . The sequence operation in FIG. 11 can be understood by those skilled in the art based on the illustration in FIG. 5 , and will not be repeated here.

In the design of FIG. 11 , I _CSS-PEAK /I _SEC-PEAK =I _EXP /I _OUT-SET can be set. In this way, ΔV _CC-CAP (which is the change of the voltage V _CC-CAP after the switching period T) can be derived from the following formula:

ΔV _CC-CAP

＝(Q _REAL -Q _EST )/C _CC-CAP

＝(0.5*I _CSS-PEAK *T _DIS -I _EXP *T)*K ₃

＝(0.5*I _SEC-PEAK *T _DIS -I _OUT-SET *T)*K ₄ ------(5)

＝(Q _SEC -Q _OUT )*K ₄ ------(6)

Wherein, K ₃ and K ₄ are two constants. From the results of formulas (5) and (6) similar to formulas (3) and (4), it can be found that as long as a negative feedback loop is properly designed, in FIG. 9, the control voltage V _CTL controls the voltage controlled oscillator 106, which can Make the results of the formulas (5) and (6) gradually approach to 0, so as to achieve the purpose of constant current operation.

FIG. 12 is a voltage-to-current converter 204a, which can be understood by those with ordinary knowledge in the technical field, and will not be described here.

Just as the constant current controller 104a in FIG. 5 can have the changes in FIG. 7 and FIG. 8 , the constant current controller 202a in FIG. 11 can also have similar changes. For example, an embodiment suitable for the constant current controller 202 in FIG. 9 can be the same as that in FIG. 7 or 8 , except that the actual current source 118 in FIG. 7 or 8 is replaced by the voltage-to-current converter 204 in FIG. 11 .

In FIG. 9, the constant current controller 202 adjusts the oscillation frequency of the voltage-controlled oscillator 106, that is, changes the switching period T in the formula (5), hoping to make the result of the formula (5) close to 0 after the next switching period. .

In addition to changing the oscillation frequency, it is also possible to roughly fix the oscillation frequency, and then change the peak value of the current flowing through the primary side winding 24 in the next switching cycle, that is, change the peak value of the voltage V _CS-PEAK to achieve Constant current operation. The constant current control method of changing the voltage peak value V _CS-PEAK is exemplified in the switch controllers 18d, 18e and 18g in FIG. 13, FIG. 14 and FIG.

FIG. 13 is similar to FIG. 9 . Different from FIG. 9 , the control voltage V _CTL of the constant current controller 202 in FIG. 13 is sent to an input terminal of the error amplifier 302 . The higher one of the control voltage V _CTL and the feedback voltage V _FB is compared with the reference voltage V- _REF1 . When the constant current controller 202 determines that the average output current of the secondary side winding 22 is too high, the control voltage V _CTL increases to decrease the compensation voltage V _COM output by the error amplifier 302 . A relatively low compensation voltage V _COM will limit or reduce the voltage peak value V _CS-PEAK of the next switching cycle. The constant current controller 202 in FIG. 13 provides a negative feedback loop to achieve constant current control operation. The negative feedback loop of the constant current control operation includes the constant current controller 202 , the error amplifier 302 , the comparator 50 , the gate logic control circuit 48 , the power switch 15 , and the voltage peak detector 206 according to the signal sequence. The negative feedback loop of the constant voltage control operation provided in FIG. 13 includes a sampling circuit 42, an error amplifier 302, a comparator 50, a gate logic control circuit 48, a power switch 15, and an auxiliary winding 25 according to the sequence of signals. . Generally speaking, the output of the error amplifier 302 in FIG. 13 is connected to a compensation capacitor (as shown in the figure). In the embodiment of FIG. 13 , the negative feedback loop of the constant current control operation and the negative feedback loop of the constant voltage control operation share the compensation capacitor. The compensation capacitor can be built into the integrated circuit implementing the switch controller 18d, or externally connected to the integrated circuit. During constant current operation, the feedback voltage V _FB is lower than the control voltage V _CTL , so the control voltage V _CTL controls the compensation capacitor. In other words, during constant current operation, the negative feedback loop of constant current control operation controls the compensation capacitor, while the negative feedback loop of constant voltage control operation does not. During constant voltage operation, the control voltage V _CTL is lower than the feedback voltage V _FB , so the feedback voltage V _FB controls the compensation capacitor.

FIG. 14 is similar to FIG. 9 . Different from FIG. 9, the control voltage V _CTL of the constant current controller 202 in FIG. 14 is sent to an adder. The result of adding the control voltage V _CTL to the detection voltage V _CS is used as an input of the comparator 52 to be compared with the current limit voltage V _CS-LIMIT . When the constant current controller 202 judges that the average output current of the secondary side winding 22 is too high, the control voltage V _CTL rises, thereby raising the initial voltage value of an input terminal of the comparator 52 and lowering the voltage of the next switch. cycle peak voltage V _CS-PEAK . Therefore, the average output current of the secondary side winding 22 in the next cycle will be reduced.

FIG. 20 is similar to FIG. 13 . The constant current controller 203 _of FIG. 20 can have the same internal circuit as the constant current controller 202 of FIG. Receive voltage peak value V _CS-PEAK . The CS peak controller 51 in FIG. 20 makes the peak value of the detection voltage V _CS approximately equal to the compensation voltage V _COM as the switching period increases. The CS peak controller 51 can be implemented by using the CS peak controller 500 in FIG. 19 or the CS peak controller 108 in FIG. 3 . The constant current controller 203 in FIG. 20 uses the current compensation voltage V _COM and the discharge signal S _DIS to judge the comparison result between the actual output current in the current switching cycle and the desired constant current I _OUT-SET , and adjust the following The compensation voltage V _COM for one switching cycle. The compensation voltage V _COM will affect the peak voltage V _CS-PEAK , thus affecting the actual output current. The negative feedback loop of the constant current control operation in FIG. 20 includes the constant current controller 203 , the error amplifier 302 , and the CS peak controller 51 according to the order of the signals.

In the above embodiment, the SMPS 10 in FIG. 1 is operated in a discontinuous conduction mode (dis-continuous conduction mode, DCM) to achieve constant current control. The following embodiments will introduce how to make the SMPS 10 of FIG. 1 operate in the continuous conduction mode (continuous conduction mode, CCM), and also achieve the operation of constant current control.

FIG. 15 shows a switch controller 18f implemented according to the present invention, which can replace the switch controller 18 in FIG. 1 to realize constant current and constant voltage control operations under CCM.

FIG. 15 is similar to FIG. 13 . Different from FIG. 13, FIG. 15 does not have the discharge time detector 102 in FIG. 13; the constant current controller 310 in FIG. 15 is slightly changed; and, FIG. 15 replaces the voltage peak value in FIG. detector 206 .

FIG. 15 does not require a discharge time detector to determine the discharge time T _DIS , because in CCM, the off time T _OFF of the power switch 15 is the discharge time T _DIS .

Under CCM, the secondary-side electric charge Q _SEC output through the secondary-side winding 22 should be 0.5(I _SEC-PEAK +I _SEC-VALLEY )*T _DIS =I _SEC-AVG *T _OFF , where I _SEC-PEAK , I _SEC-VALLEY and I _SEC-AVG are respectively the current peak value, current valley value and current average value of the secondary side winding 22 in the current switching cycle. From the derivation of formulas (5) and (6), it can be found that the peak current I _SEC-PEAK corresponds to the peak voltage V _CS-PEAK , so the average current I _SEC-AVG will correspond to the average voltage V _CS-AVG . Therefore, the average voltage detector 306 in FIG. 15 finds out the average voltage V _CS-AVG and sends it to the constant current controller 310 to achieve the constant current control operation.

FIG. 16 is a constant current controller 310a implemented according to the present invention, which can be applied to the embodiment of FIG. 15 . In FIG. 16, the voltage average value V _CS-AVG is converted by the voltage-to-current converter 360 into a current having a value I _CSS-AVG . The voltage-to-current converter 360 may be implemented similarly to the voltage-to-current converter 204a of FIG. 12 . In the design of Fig. 16, I _CSS-AVG /I _SEC-AVG = I _EXP /I _OUT-SET should be satisfied. Similar to the constant current control operation in Fig. 13, as long as the voltage average value V _CS-AVG can be found, Fig. 15 provides a negative feedback loop to achieve constant current control operation.

As the constant current controller 104a in FIG. 5 has the changes in FIGS. 7 and 8, the constant current controller 310a in FIG. 16 can be changed similarly. Although not illustrated, this change can be inferred from the previous explanation and will not be repeated.

FIG. 17 shows an average voltage detector 306a that may be used in the switch controller 18f of FIG. 15 . The average voltage detector 306a itself provides a negative feedback loop, so that the average voltage V _CS-AVG is approximately equal to the average voltage of the primary winding 24 when the power switch 15 is turned on. The capacitor 368 stores the average voltage V _CS-AVG , which is also the initial voltage value of the capacitor 366 when the power switch 15 is turned on. When the power switch 15 is turned on, that is, when the gate voltage V _GATE is at a logic high level, if the detection voltage V _CS is lower than the voltage average value V _CS-AVG , the constant current source 364 supplies the capacitor 366 with a preset current value I _CON Discharging; if the detection voltage V _CS is higher than the average voltage V _CS-AVG , the constant current source 362 charges the capacitor 366 with a preset current value I _CON . In other words, during the turn-on time of the power switch 15, if the detection voltage V _CS (corresponding to the current flowing through the primary side winding 24) is higher than the average voltage V _CS-AVG (corresponding to the currently guessed average current of the primary side winding 24) The time is longer than the time when the voltage is lower than the average value V _CS-AVG , then the voltage of the capacitor 366 will increase. Therefore, when the power switch 15 is turned off, the average voltage V _CS-AVG of the capacitor 368 will be slightly pulled up due to the effect of charge sharing. The variation of the average voltage V _CS-AVG will make the detection voltage V _CS higher than the average voltage V _CS-AVG close to the time lower than the average voltage V _CS-AVG in the next cycle. If the average voltage V _CS-AVG memorized by the capacitor 368 does not change, it means that the detection voltage V _CS is higher than the average voltage V _CS-AVG for the same time as it is lower than the average voltage V _CS-AVG . At this time, the average voltage value V _CS-AVG really represents the average value of the detection voltage V _CS .

FIG. 18 shows another average voltage detector 306b that may be adapted for use in switch controller 18f of FIG. 15 . The average voltage detector 306b also provides a negative feedback loop, so that the average voltage V _CS-AVG is approximately equal to the average voltage of the primary winding 24 when the power switch 15 is turned on. Similarly, the capacitor 382 stores the average voltage V _CS-AVG . The function of the voltage-to-current converter 386 and the capacitor 384 is to calculate the integral value S _VCS of the detection voltage V _CS when the power switch 15 is turned on. The integral value S _VCS may correspond to the actual amount of charge flowing through the primary winding 24 during a switching cycle. The function of the voltage-to-current converter 388 and the capacitor 384 is to calculate the integral value S _VCSAVG of the average voltage V _CS-AVG when the power switch 15 is turned on. This integral value S _VCSAVG can be regarded as an estimated charge amount of the actual charge amount. If the integral value S _VCS is greater than the integral value S _VCSAVG , the voltage of the capacitor 384 will be increased, which also means that the average voltage V _CS-AVG is low. Thus, when the power switch 15 is turned off, the average voltage V _CS-AVG is slightly increased due to the principle of charge sharing. Therefore, the integrated value S _VCSAVG approaches the integrated value S _VCS in the next cycle. The average voltage V _CS-AVG is roughly locked to a certain value, so that the integral value S _VCS is approximately equal to the integral value S _VCSAVG , which also means that the average voltage V _CS-AVG is approximately equal to the average value of the detection voltage V _CS .

The way of adjusting the average voltage V _CS-AVG in FIG. 17 and FIG. 18 is similar to the way of adjusting the control voltage V _CTL in FIG. 5 . To simulate the method of adjusting the control voltage V _CTL in Figure 7, Figure 17 and Figure 18 can also compare the voltage of the capacitor 366 or 384 with a reference voltage V _REF-AVG , and then use the comparison result to compare the current to the capacitor 368 or 382 Charge and discharge to fine-tune the voltage average value V _CS-AVG . Such a negative feedback loop can also achieve the same effect of finding the approximate average voltage V _CS-AVG .

To simulate the method of adjusting the control voltage V _CTL in Fig. 8, Fig. 17 and Fig. 18 can also compare the voltage of the capacitor 366 or 384 with a reference voltage V _REF-AVG , and then use the comparison result to make a counter count or Count down to fine-tune the average voltage V _CS-AVG output by a digital-to-analog converter. In this way, the capacitor 368 or 382 can be omitted. Such a negative feedback loop can also achieve the same effect of finding the approximate average voltage V _CS-AVG .

Although the above embodiments are all implemented with the flyback architecture, the present invention is not limited to the flyback architecture, and can also be applied to other types of power converter architectures such as booster or buck.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the appended claims.

Claims (10)

1. a control method is applicable to control one switch type power supplying device, and this switch type power supplying device includes a transformer, be coupled to an input power supply, this transformer is controlled with energy storage by a switch or is released energy, and to produce an out-put supply, this control method includes:

One electric capacity is provided;

Deposit the difference that an actual quantity of electric charge and is estimated the quantity of electric charge with this electric capacity, wherein, flow through in the switch periods of this actual quantity of electric charge corresponding to this switch total charge dosage of this transformer, this is estimated the quantity of electric charge and estimates for this actual quantity of electric charge total pre-in this switch periods; And

According to the voltage of this electric capacity, change in the follow-up switch periods, this actual quantity of electric charge and this estimate the quantity of electric charge one of them, thereby make in this follow-up switch periods, this actual quantity of electric charge approximates this greatly and estimates the quantity of electric charge.

2. control method as claimed in claim 1, wherein, this transformer has a primary side winding and a primary side winding, and this actual quantity of electric charge is corresponding to the primary side quantity of electric charge of this primary side winding of flowing through in this switch periods.

3. control method as claimed in claim 2, wherein, this control method also includes:

One preset value is provided;

Make the peak-peak electric current of this primary side winding of flowing through be approximately this preset value;

Provide an actual current source and to estimate current source, wherein this actual current source ratio is in this preset value;

Detect the discharge time of this primary side winding in a switch periods;

Come from first electric charge of in this discharge time this electric capacity charging being accumulated generation with this actual current, as this actual quantity of electric charge; And

Estimate electric current with this and come from second electric charge of in this switch periods this capacitor discharge being accumulated, estimate the quantity of electric charge as this; And

According to the voltage of this electric capacity, change this preset value.

4. control method as claimed in claim 2, wherein, this control method also includes:

The peak-peak electric current that makes this primary side winding of flowing through is a preset value;

Provide an actual current source and to estimate current source, wherein this actual current source and this current value of estimating current source are a preset ratio value;

Detect the discharge time of this primary side winding in a switch periods;

Come from first electric charge of in this discharge time this electric capacity charging being accumulated generation with this actual current, as this actual quantity of electric charge; And

Estimate electric current with this and come from second electric charge of in this switch periods this capacitor discharge being accumulated, estimate the quantity of electric charge as this.

5. control method as claimed in claim 2, wherein, this control method also includes:

Provide an actual current source and to estimate current source, wherein the about correspondence of the current value in this actual current source current peak or the current average of this primary side winding of flowing through;

Accumulate this actual current with this electric capacity and come from first electric charge that is produced in the discharge time, as this actual quantity of electric charge; And

Accumulate this with this electric capacity and estimate electric current and come from second electric charge that is produced in the switch periods, estimate the quantity of electric charge as this.

6. control method as claimed in claim 5, wherein, this conversion step includes;

This voltage according to this electric capacity changes a control signal;

Relatively this control signal and a reference signal are to produce a compensating signal; And

With this compensating signal, limit this primary side current peak of this primary side winding of flowing through.

7. control method as claimed in claim 5 also includes:

This voltage according to this electric capacity changes a control signal; And

According to this control signal, limit this primary side current peak of this primary side winding of flowing through.

8. control method as claimed in claim 5 also includes:

Detect this primary side winding this discharge time in a switch periods.

9. control method as claimed in claim 1, wherein, this actual quantity of electric charge is corresponding to the primary side quantity of electric charge of this primary side winding of flowing through in this switch periods.

10. control method as claimed in claim 9, wherein, this control method also includes:

Provide an actual current source and to estimate current source, wherein the electric current correspondence in this actual current source electric current of this primary side winding of flowing through;

Accumulate this actual current with this electric capacity and come from first electric charge that is produced when this switch opens, as this actual quantity of electric charge; And

Accumulate this with this electric capacity and estimate electric current and come from second electric charge that is produced when this switch opens, estimate the quantity of electric charge as this;

Wherein, this conversion step includes:

This voltage according to this electric capacity changes this and estimates current source, estimates the quantity of electric charge to change in this follow-up switch periods this.

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