CN101997082A - Self-converging bottom electrode ring - Google Patents
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- CN101997082A CN101997082A CN 200910167554 CN200910167554A CN101997082A CN 101997082 A CN101997082 A CN 101997082A CN 200910167554 CN200910167554 CN 200910167554 CN 200910167554 A CN200910167554 A CN 200910167554A CN 101997082 A CN101997082 A CN 101997082A
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- 230000008859 change Effects 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 125000006850 spacer group Chemical group 0.000 claims abstract description 18
- 238000009413 insulation Methods 0.000 claims description 44
- 230000004888 barrier function Effects 0.000 claims description 42
- 239000011810 insulating material Substances 0.000 claims description 24
- 239000004020 conductor Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 239000012782 phase change material Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- 239000012774 insulation material Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000009466 transformation Effects 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 229910000618 GeSbTe Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 15
- 238000000151 deposition Methods 0.000 description 14
- 230000008021 deposition Effects 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 150000003376 silicon Chemical class 0.000 description 4
- 229910052798 chalcogen Inorganic materials 0.000 description 3
- 150000004770 chalcogenides Chemical class 0.000 description 3
- 150000001787 chalcogens Chemical class 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- 229910005872 GeSb Inorganic materials 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910018321 SbTe Inorganic materials 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
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Abstract
A method and memory cell including a self-converging bottom electrode ring. The method includes forming a step spacer, a top insulating layer, an intermediate insulating layer, and a bottom insulating layer on a substrate. The method includes forming a step spacer within the top insulating layer and the intermediate insulating layer. The size of the step spacer is easily controlled. The method also includes forming a via in the bottom insulating layer with the step spacer as a shield. The method includes forming a bottom electrode ring within a via that includes a cup-shaped outer conductive layer within the via and forming an inner insulating layer within the cup-shaped outer conductive layer. The method includes forming a phase change layer on the bottom electrode ring and forming a top electrode on the bottom electrode ring.
Description
Technical field
The present invention relates to the formation about the auto-convergence bottom electrical polar ring of Nonvolatile memory unit, and more especially about changing internal storage location mutually.
Background technology
Two main groups are arranged: Nonvolatile memory and volatile ram in calculator memory.It is unwanted continuing the input energy for maintenance information in Nonvolatile memory, but then needs in volatile ram.The example of Nonvolatile memory device is CD (CD and DVD), magnetic hard-disk device and phase transition internal memory.The example of volatile ram device comprises DRAM (DRAM (Dynamic Random Access Memory)) and SRAM (static random access memory).The present invention be directed to phase transition internal memory (phase changememory) and in the phase change internal memory, form the method for less internal storage location.
In phase transition internal memory, information is to be stored in can be controlled in the out of phase material.One of them demonstrates the different electronic properties that can be used in store information mutually for these.This amorphous phase and crystalline phase are typically to be used for the position to store (0 with 1 data) two mutually, and this has detectable difference because of them in electronics resistance.Be more particularly, this amorphous phase has the resistance higher than this crystalline phase.Usually glass chalcogenide (glass chalcogenides) is to be used for as phase-change material.The group of this material comprises chalcogen (chalcogen) (periodic table 16/VIA family) and more electropositive elements.When design phase transition internal memory unit, selenium (Se) and tellurium (Te) are to be used in the most frequently used semiconductor group that produces the glass chalcogenide.This example can be Ge2Sb2Te5 (GST), SbTe and In2Se3.Yet some phase-change materials do not utilize chalcogen, for example GeSb.Therefore, as long as they can keep independent amorphous and crystalline state, all materials all can be used in phase change material unit.
This amorphous and crystalline phase are reversible in phase-change material.Because ohmic heating, electronic impulse is flow through and is changed material mutually and change material mutually to melt this.High strength and short duration pulsed causing melt and cooling time fast relatively; This changes the organized crystal grain of the not free formation of material mutually, produces amorphous phase by this.Relatively low-intensity continues pulse this phase-change material is slowly cooled off with long, so form organized crystal grain and be called as in this crystalline phase.Simultaneously, less item region of variation causes less needs to melt the energy of this phase-change material.
Usually, bottom electrode is to be used for this phase-change material of heating in this phase change region.The shape of this bottom electrode, size influences this bottom electrode with formation is providing this to change the effective mass that changes required electric current mutually of material mutually.Therefore, it is worth making the bottom electrode that minimizes the operation energy needed and provides this to change the material heating that evenly distributes mutually.
Summary of the invention
Exemplary embodiments of the present invention is a kind of method that is used for forming memory cell architectures in substrate.This substrate can be but be not restricted to: naked silicon base, have the silicon base of being deposited on upper surface insulation material layer this silicon base or have this silicon base of formed bottom contact in silicon base.
In this substrate in order to this method of forming this memory cell architectures must the bottom insulation layer of deposition first insulating material in the substrate, intermediary's insulating barrier of deposition second insulating material on this bottom insulation layer and on this intermediary's insulating barrier the top layer of deposition the 3rd insulating material.This second insulating material is can remove independently and the 3rd insulating material is can remove independently from this second insulating material from this first insulating material.Through hole forms step for to form through hole in this top layer and this intermediary's insulating barrier.The otch step causes this top layer to protrude in this intermediary's insulating barrier in this through hole space for to form otch in this through hole.
It is to form the ladder distance piece in this through hole that the ladder distance piece forms step, causes on this bottom insulation layer and produces cavity.The size of this cavity is to have nothing to do in this hole size and photoetching.The size of this cavity is according to this otch and deposition.Typically, will obtain more deposition than large through-hole, and will obtain less deposition than small through hole.Therefore, the critical size of this cavity is with the size of auto-convergence to this otch.This ladder distance piece forms step and has also formed and be contained in this ladder distance piece and extend to the Shu passage of this bottom insulation layer.Etching step is this passage in this ladder distance piece and be extended the top surface that passes this bottom insulation layer and extend to this substrate.In Shu specific embodiment of the present invention, its this first insulating material and the 3rd insulating material are made of same material, during this etching step in this top layer also be removed.It is formation bottom electrical polar ring in this passage in this bottom insulation layer that the bottom electrode ring forms step.This bottom electrical polar ring comprises outer conductive material and inner insulation material.Being deformed into step mutually is that phase-change material is deposited on this bottom electrical polar ring.It is that top electrodes is formed on this phase-change material that top electrode layer forms step.
Another exemplary aspect of the present invention is a kind of memory cell architectures.This memory cell architectures is made of substrate.This substrate can include, but are not limited to naked silicon base, have the silicon base of being deposited on top surface insulation material layer this silicon base or have this silicon base of formed bottom contact in silicon base.
This memory cell architectures has in this suprabasil bottom insulation layer, and it is made of first insulating material.The bottom electrical polar ring is to form in this bottom insulation layer.This bottom electrical polar ring is made of cup type outer conductive material and the Shu inner insulation material in this outer conductive material.Phase change layer is made of and on this bottom electrical polar ring and this bottom insulation layer, this bottom electrical polar ring has less vary in diameter compared to the vary in diameter of this phase change layer phase-change material.Top electrode layer is constituted and is formed on this phase change layer by electric conducting material.
Description of drawings
Be regarded as theme of the present invention and be in the conclusion of specification, being pointed out especially and in application claims, specifically asked.Aforementioned and other purpose of the present invention, feature and advantage are from being obvious with adopting following detailed description the in detail in conjunction with being accompanied by graphic, wherein:
The 1st figure represents initial wafer, substrate and insulating barrier.
The 2nd figure represents that through hole forms.
The 3rd figure represents that notch shape becomes.
The 4th figure represents that spacer material deposition and cavity form.
The 5th figure represents that the ladder distance piece forms.
The 6th figure represents that the passage of bottom electrode ring forms.
The 7th figure represents that the ladder distance piece removes.
The the 8th to 10 figure represents that the bottom electrode ring forms.
The 11st figure represents to change mutually assembly and top electrodes forms.
Embodiment
The present invention is to be described with reference to the 1st to 11 figure.When with reference to these when graphic, the whole similar assemblies that all show are to indicate with similar element numbers.Embodiments of the invention normally at but be not limited in the electrode retaining collar of the auto-convergence size (critical size) that forms phase transition internal memory (PCM) device.This electrode retaining collar can be used in and change the phase transformation state in the PCM device.
The 1st figure represents initial wafer 102.In certain embodiments of the invention, this initial wafer is to be made of substrate 104, bottom insulation layer 106, intermediary's insulating barrier 108, top layer 110 and 112 of bottom contacts.This substrate can be by silicon, silicon dioxide or any other FEOL (front-end-of-line on silicon; FEOL) initial wafer constitutes, and it is included in the access transistor of this wafer the inside.This bottom contact 112 can be made of any electric conducting material of enough drive currents that can carry this PCM device.In a specific embodiment of the present invention, this bottom contact 112 is made of tungsten (W).
Aforementioned three insulating barriers 106,108 and 110 can be made of any electrical insulating material, yet have limiting factor.This bottom insulation layer 106 must be removable independently from this intermediary's insulating barrier 108, and this intermediary's insulating barrier 108 must be removable independently from this top layer 110.In a specific embodiment of the present invention, this bottom insulation layer 106 is made of silicon nitride, and this intermediary's insulating barrier 108 is made of silicon dioxide, and this top layer 110 is made of silicon nitride.The deposition technique of aforementioned three insulating barriers is to knowing usually that having of this field the knowledgeable is for knowing.For example: this deposition can be utilized various chemical vapor deposition (CVD) processes.
Now turn to the 2nd figure, through hole (via) 202 forms in this top layer 110 and this intermediary's insulating barrier 108.The bottom of this through hole 202 is top surfaces of this bottom insulation layer 106.This through hole can know that usually photoetching shielding (mask) and reactive ion etching (RIE) technology that the knowledgeable knows form with having in this field.In certain embodiments of the invention, this through hole 202 is formed directly on this bottom electrode 112.
The 3rd figure is presented at the formation of the otch 302 in this through hole 202.This top layer 110 protrudes in this intermediary's insulating barrier 108 in this through hole 202.Have in this field and know that usually the knowledgeable will understand various wet etchings and can be applied to the formation otch.Employed wet etching is according to the material that is used in this top layer 110 and this intermediary's insulating barrier 110.In an embodiment of the present invention, wherein this top layer 110 is made of and this intermediary's insulating barrier 108 is made of silicon dioxide silicon nitride, uses diluted hydrofluoric acid (dilute hydrofluoric acid; DHF) wet etching, etched to form this otch 302 so that this intermediary's insulating barrier 108 can be used compared to this top layer 110 for very high speed.
In the 4th figure, highly suitable shape (conformal) spacer layers 402 is deposited on this top layer 110 and is deposited in the through hole 202 that is held in this intermediary's insulating barrier 108.Cavity 404 forms in the center (seeing also the 3rd figure) of this through hole 202 in this spacer layers 402 and approximately.This otch 302 (seeing also the 3rd figure) is avoided this through hole 202 of this spacer materia complete filling.The diameter of this cavity 404 is to have nothing to do in the diameter of this through hole 202 and is to double the diameter that is formed on this otch that forms between this top layer 110 and this intermediary's insulating barrier 108.Can obtain more deposition and less through hole 202 can obtain less deposition than large through-hole 202.Therefore, the diameter of this cavity 404 (critical size) is with the size of auto-convergence to this otch.Moreover this critical size is for haveing nothing to do in photoetching.In an embodiment of the present invention, this spacer layers is constituted and is utilized CVD technology and deposit by amorphous silicon.
The 5th figure represents the formation of ladder distance piece (step spacer) 502 and the passage 504 in this ladder distance piece 502.This ladder distance piece 502 and this passage are to form by this spacer layers 402 of etching (please refer to the 4th figure).This cavity 404 (please refer to the 4th figure) cause this etching be penetrated into this through hole 202 the center and this ladder distance piece 402 etched intact before and etch into this spacer layers under this cavity 404, therefore in this through hole 202, stay a ring.This passage 504 extends to the top surface of this bottom insulation layer 106 from the top of this ladder distance piece 502.The sidewall of this passage 504 is this ladder distance piece 502.This field has to be known usually that the knowledgeable will understand and can adopt directive property RIE technology to this etching.
Now turn to the 6th figure, this passage 504 extends through this bottom insulation layer 106.This ladder distance piece 502 is the hard shieldings that are used for as etching into this bottom insulation layer 106.This passage 504 extends to pass this bottom insulation layer 106 downwards, causes the bottom of this passage 504 to be the top surface of this substrate 104 or the top surface of this bottom contact 112.In addition, this top layer also is removed.In a specific embodiment of the present invention, this top layer and this bottom insulation layer 106 are made of silicon nitride, can adopt directive property RIE for etching into this bottom insulation layer and removing this top layer.
In the 7th figure, this ladder distance piece is removed.Have in this field know usually that the knowledgeable will understand the etching of being adopted will be according to the material type that is used for this ladder distance piece.In a specific embodiment of the present invention, this ladder distance piece is made of amorphous silicon, and potassium hydroxide (KOH) and tetramethylammonium hydroxide (tetramethylammonium hydroxide; TMAH) then can be used for this etching.
The 8th figure shows forming by the outer lead layer 802 that electric conducting material constituted.This outer conductive layers 802 be along and be aligned in the sidewall of (line) this passage 504 and bottom and form.In certain embodiments of the invention, this outer conductive layers 802 is to contact 112 contacts with this bottom.This field has to be known usually that the knowledgeable will understand and can use various electric lead materials, for example but be not limited in titanium nitride (TiN) or tantalum nitride (TaN).Deposition for various conductor materials can adopt conventional CVD technology.
The 9th figure shows forming by the internal insulating layer 902 that insulating material constituted.This internal insulating layer 902 is the remainders that are deposited on this outer conductive layers 802 and fill this passage 504.In an embodiment of the present invention, this internal insulating layer 902 is made of silicon nitride.This field has knows that usually the knowledgeable will understand the CVD dielectric medium technology that can adopt routine for the formation of this internal insulating layer 902.
Forward the 10th figure to, the outer conductive layers 802 of this intermediary's insulating barrier of this passage outside and this internal insulating layer 902 and this passage outside can be removed.This field has to be known usually that the knowledgeable will understand and can adopt for example for removing of the outer conductive layers 802 of this intermediary's insulating barrier of this passage outside and this internal insulating layer 902 and this passage outside but be not restricted to chemico-mechanical polishing (CMP) technology.
The top surface that can expose this bottom insulation layer 106 for removing of the outer conductive layers 802 of this intermediary's insulating barrier of this passage outside and this internal insulating layer 902 and this passage outside and the top surface of formed this bottom electrical polar ring 1002.The top surface of the top surface of this bottom insulation layer 106 and formed this bottom electrical polar ring 1002 is the top surfaces that are parallel to this substrate, forms flat surfaces for changing the deposition of layer mutually by this.This bottom electrical polar ring 1002 is to constitute by being contained in 802 glasss of institutes of this internal insulating layer 902 this outer conductive layers wherein.This bottom electrical polar ring 1002 is to be contained in this bottom insulation layer 106.In a specific embodiment of the present invention, this bottom electrical polar ring 1002 is directly to be positioned in this bottom contact 112.
Shown in the 11st figure, this changes layer 1102 mutually and top electrodes 1104 is to form on this bottom insulation layer 106 and this bottom electrical polar ring 1002.In an embodiment of the present invention, this changes layer 1102 mutually for identical at least wide block with this bottom electrical polar ring 1002.This top electrodes 1104 is to change mutually on the layer 1102 at this to form.In certain embodiments of the invention, this changes layer 1102 mutually and is made of and this top electrodes 1104 is made of titanium nitride (TiN) germanium-antimony-tellurium (GST).This field has to be known usually that the knowledgeable will understand for this and changes layer 1102 mutually and the formation of this top electrodes 1104 can be adopted various technologies, for example but be not restricted to, change the CVD technology of material deposition and metal sputtering (sputter) technology of metal deposition mutually.Moreover because this bottom electrode 802 is the results that are formed with as this auto-convergence cavity 404 (seeing also the 4th figure), this bottom electrode 802 has the vary in diameter littler than the vary in diameter of this phase change layer 1102.
In an alternate embodiment of the invention, this change mutually the layer 1102 be during changing insulating barrier 1106 mutually formation.This changes insulating barrier 1106 mutually is to form on this bottom insulation layer 106 and on this bottom electrical polar ring 1002.Groove changes mutually on this bottom electrical polar ring 102 in the insulating barrier 1106 at this subsequently and forms, and the bottom that causes this groove is the top surface of this bottom electrical polar ring 1002 and the top surface of this bottom insulation layer 106.This top electrodes 1104 changes layer 1102 mutually at this subsequently and changes formation on the insulating barrier 1106 mutually with this.In an embodiment of the present invention, this changes insulating barrier 1106 mutually and is made of silicon dioxide.This field has to be known usually that the knowledgeable will understand for this formation, groove that changes insulating barrier 1106 mutually and forms and be applicable to that the formation on the surface that forms this top electrodes 1104 can adopt various technologies.These technologies can comprise be not limited in for this change the CVD technology of the formation of insulating barrier 1106 mutually, the photoetching shielding that forms for groove is with RIE technology and for the excessive CMP technology that removes that changes layer 1102 mutually.
The present invention has for the described preferred embodiment of sub-lithographic printing method (sub-lithographic printing method) (it is inclined to as an illustration property but not is restriction), yet it should be noted that and can the field be had know usually the knowledgeable to improve and change according to above-mentioned instruction.Therefore, should recognize any change of carrying out this specific embodiment those disclosed herein all belong to scope of the present invention with spirit in and contained by the application claims that added.So, having viewpoint described in the invention and have by Patent Law required details and speciality, it is asked and is thirsted for protection and be suggested in these additional application claims by patent (Letters Patent).
Claims (18)
1. method that forms memory cell architectures, this method comprises:
Form at least one bottom insulation layer in a substrate, this bottom insulation layer is made of first insulating material;
Form at least one intermediary insulating barrier in this substrate, this intermediary's insulating barrier is made of second insulating material, can remove this second insulating material independently from this first insulating material;
Form at least one top layer in this substrate, this top layer is made of the 3rd insulating material, can remove the 3rd insulating material independently from this second insulating material;
In this top layer and this intermediary's insulating barrier, form a through hole;
In this intermediary's insulating barrier, form a kerf, cause that this top layer protrudes in this intermediary's insulating barrier in this through hole;
Form the ladder distance piece of a spacer materia in this through hole, cause to produce a cavity on this bottom insulation layer, the diameter of this cavity is independent of the diameter of this through hole, and this ladder spacer loop is around a passage, and this passage extends to this bottom insulation layer;
This bottom insulation layer of etching causes this passage to extend through this bottom insulation layer;
Remove this ladder distance piece;
Form a bottom electrical polar ring of this passage in this bottom insulation layer of complete filling, this bottom electrical polar ring is made of an outer conductive material and an inner insulation material;
On this bottom electrical polar ring, form a phase change layer that is constituted by a phase-change material; And
On this phase-change material, form a top electrode layer that is constituted by an electric conducting material.
2. method according to claim 1, the step that wherein forms this otch in this intermediary's insulating barrier comprises this intermediary's insulating barrier of etching, causes this top layer to protrude in this interior intermediary's insulating barrier of this through hole.
3. method according to claim 1, the step that wherein forms this ladder distance piece comprises:
In this through hole with and deposit a spacer layers along this otch, this spacer layers comprises this cavity; And
This spacer layers of etching causes and form this passage in this ladder distance piece.
4. method according to claim 3, wherein this spacer layers is made of amorphous silicon.
5. method according to claim 1, the step that wherein forms this passage in this bottom insulation layer comprises the surface of etching by this bottom insulation layer that this passage exposed in this ladder distance piece.
6. method according to claim 1, wherein this substrate comprises and being positioned under this bottom electrical polar ring and by bottom contact that electric conducting material constituted.
7. method according to claim 1, the step that wherein forms this bottom electrical polar ring comprises:
Formation is by the outer conductive layers that this outer conductive material constituted, and this outer conductive layers complete matching is in the sidewall and the bottom of this passage in this bottom insulation layer;
Formation is by the internal insulating layer that this internal insulating layer constituted, and this inner insulation material is comprised in this outer conductive layers and this passage in this bottom insulation layer of complete filling; And
Polish this bottom insulation layer, this intermediary's insulating barrier, this outer conductive layers and this internal insulating layer, cause the top surface of this bottom insulation layer, the top surface of this outer conductive layers and the top surface of this internal insulating layer to be parallel to the top surface of this substrate, and remove this intermediary's insulating barrier fully.
8. method according to claim 1, the step that wherein forms this phase change layer comprises:
On this bottom electrical polar ring and on this bottom insulation layer, form a phase transformation insulating barrier;
Form groove in this phase transformation insulating barrier on this bottom electrical polar ring, this groove is the same wide with this bottom electrical polar ring at least; And
With this groove of phase-change material complete filling.
9. method according to claim 1, wherein this outer conductive material is a tungsten.
10. method according to claim 1, wherein this first insulating material and this three insulating material are silicon nitride.
11. method according to claim 1, wherein this second insulating material is a silicon dioxide.
12. method according to claim 1, wherein this inner insulation material is a silicon nitride.
13. method according to claim 1, wherein this phase-change material is germanium-antimony-tellurium (GST).
14. an internal storage location comprises:
One substrate;
In this suprabasil bottom insulation layer, this bottom insulation layer is made of one first insulating material;
A bottom electrical polar ring that in this bottom insulation layer, forms, this bottom electrical polar ring is made of the inner insulation material in this outer conductive material and one glass of type outer conductive material;
A phase change layer that on this bottom electrical polar ring and this bottom insulation layer, constitutes by phase-change material, this bottom electrical polar ring has the vary in diameter littler than the vary in diameter of this phase change layer; And
One top electrode layer, this top electrode layer is made of an electric conducting material.
15. internal storage location according to claim 14, wherein this phase change layer is the same with this a bottom electrical polar ring at least wide block.
16. internal storage location according to claim 15 also comprises a phase transformation insulating barrier that is made of second insulating material, this phase change layer is included in this phase transformation insulating barrier.
17. internal storage location according to claim 14, wherein this bottom electrical polar ring comprises:
By the outer conductive layers that this outer conductive material constituted, this outer conductive layers is comprised in the lower surface and this bottom insulation layer of top surface, this phase change layer of this substrate; And
By the internal insulating layer that this inner insulation material constituted, this internal insulating layer is comprised in the lower surface of this outer conductive layers and this phase change layer.
18. internal storage location according to claim 14, wherein this substrate comprises and being positioned under this bottom electrical polar ring and by bottom contact that electric conducting material constituted.
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