CN101989412B - Gate line driving circuit of liquid crystal panel - Google Patents
Gate line driving circuit of liquid crystal panel Download PDFInfo
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- CN101989412B CN101989412B CN2009101650932A CN200910165093A CN101989412B CN 101989412 B CN101989412 B CN 101989412B CN 2009101650932 A CN2009101650932 A CN 2009101650932A CN 200910165093 A CN200910165093 A CN 200910165093A CN 101989412 B CN101989412 B CN 101989412B
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Abstract
The invention discloses a gate line driving circuit, which comprises a driving chip at least comprising a first output part and a second output part, a liquid crystal panel at least comprising a first gate line, a second gate line and a third gate line, a first switch and a second switch. One end of the first gate line is electrically connected with the first output part, and the other end is electrically connected with a control end of the first switch. One end of the third gate line is electrically connected with the second output part, and the other end is electrically connected with a control end of the second switch. An input end of the first switch is electrically connected with the working voltage, and an output end of the first switch is electrically connected with an input end of the second switch; and an output end of the second switch is electrically connected with a ground point. One end of the second gate line is electrically connected between the output end of the first switch and the input end of the second switch.
Description
Technical field
The present invention relates to a kind of driving circuit of liquid crystal panel, particularly relate to a kind of gate line drive circuit.
Background technology
At present, liquid crystal panel is owing to advantages such as low-power, low radiation, and widely common people accept.The driving of liquid crystal panel mainly is a deflection angle of being controlled each liquid crystal molecule in a slice liquid-crystalline glasses by a slice film crystal tube drive circuit, produces various pictures thus.Say accurately; The film crystal tube drive circuit is by many gate lines arranged side by side (Gate Line), claims sweep trace (Scan Line) again, with many data lines arranged side by side (Data Line); Claim signal wire (Signal Line) again, mutually orthogonal and form a matrix control circuit.When frame (Frame) upgraded, gate line can start one by one, that is the feed-in noble potential, received the signal of many data lines of quadrature on the gate line then, to upgrade pairing a plurality of pixels on the gate line.Therefore, in order to control the signal of each pixel, the enabling signal of many gate lines staggers mutually.
With reference to figure 1, it is the structural representation of the driving circuit of existing liquid crystal panel.Among the figure, chip for driving 10 comprises a plurality of efferents, like first efferent 11, second efferent 12 and the 3rd efferent 13; 20 of liquid crystal panels comprise a plurality of gate lines, like first grid polar curve 21, second grid line 22 and the 3rd gate line 23.In addition, also have many data lines with the gate line quadrature on the liquid crystal panel 20, because of not have direct relation not shown with the present invention.In the prior art; Each bar gate line all is electrically connected to an efferent; As shown in Figure 1, first efferent 11 electrically connects first grid polar curve 21, second efferent 12 electrically connects second grid line 22 and the 3rd efferent 13 electrically connects the 3rd gate line 23.Next with reference to figure 2, it is the signal waveforms of the drive signal of existing liquid crystal panel.Among the figure, because chip for driving 10 is exported trigger voltage to gate line from each output port successively; Therefore; First grid polar curve drive signal presents noble potential at the first period T1 starting state, second grid line drive signal presents the starting state of noble potential at the second period T2, and the 3rd gate line drive signal presents the starting state of noble potential at the 3rd period T3.
Yet; A liquid crystal panel has hundreds of gate line easily; Even a chip for driving has the dozens of efferent, a liquid crystal panel still needs the dozens of chip for driving to accomplish the start-up mode one by one of above-mentioned dullness, keeps the smoothness of picture with the frame on the fast updating screen.
In order to solve each item problem of prior art, the inventor proposes a kind of gate line drive circuit of liquid crystal panel, with implementation and the foundation as the above-mentioned shortcoming of improvement based on research and development and many practical experience for many years.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of gate line drive circuit of liquid crystal panel, improving existing gate line drive circuit, and then reduce the use amount of chip for driving.
According to the object of the invention, a kind of gate line drive circuit is proposed, it comprises: chip for driving comprises first efferent and second efferent at least; Liquid crystal panel comprises first grid polar curve, second grid line and the 3rd gate line at least; First switch and second switch.Wherein, an end of first grid polar curve electrically connects first efferent, and the other end electrically connects the control end of first switch.One end of the 3rd gate line electrically connects second efferent, and the other end electrically connects the control end of second switch.The input end of first switch electrically connects WV, and the output terminal of first switch electrically connects the input end of second switch, and the output terminal of second switch electrically connects earth point.One end of second grid line is electrically connected between the input end of output terminal and second switch of first switch.
In addition, gate line drive circuit of the present invention also can comprise noble potential stabilizing circuit and electronegative potential stabilizing circuit, to promote the degree of stability of second grid line drive signal of the present invention.Wherein, the noble potential stabilizing circuit is in order to stablizing the high potential signal of second grid line, and the electronegative potential stabilizing circuit is in order to stablize the low-potential signal of second grid line.
Hold the above, the gate line drive circuit according to liquid crystal panel of the present invention has the following advantages:
(1) this gate line drive circuit can drive three gate lines with two output ports, and also available three output ports drive five gate lines; The rest may be inferred, and this gate line drive circuit only needs the efferent of existing half quantity of image element circuit can reach identical effect, the chip for driving that therefore can save half quantity.
(2) though this gate line drive circuit need to increase a plurality of thin film transistor switch, yet these thin film transistor switch in the liquid crystal panel drive circuit manufacture process, can reach easily through revising the light shield pattern, increase extra cost hardly.
Description of drawings
Fig. 1 is the structural representation of driving circuit of the liquid crystal panel of prior art;
Fig. 2 is the signal waveforms of drive signal of the liquid crystal panel of prior art;
Fig. 3 is the structural representation of gate line drive circuit of the present invention;
Fig. 4 is the signal waveforms of gate line drive signal of the present invention;
Fig. 5 is the structural representation of the gate line drive circuit of one embodiment of the invention;
Fig. 6 is the structural representation of the gate line drive circuit of another embodiment of the present invention;
Fig. 7 is the signal waveforms of the gate line drive signal of one embodiment of the invention;
Fig. 8 is the structural representation of the gate line drive circuit of further embodiment of this invention;
Fig. 9 is the signal waveforms of the gate line drive signal of another embodiment of the present invention;
Figure 10 is the gate line drive circuit of one embodiment of the invention and the structural representation of current potential stabilizing circuit;
Figure 11 is the structural representation of the electronegative potential stabilizing circuit of one embodiment of the invention;
Figure 12 is the structural representation of the noble potential stabilizing circuit of one embodiment of the invention; And
Figure 13 is the structural representation of the current potential stabilizing circuit of one embodiment of the invention.
[main element symbol description]
10: chip for driving; 34: the four switches;
11: the first efferents; 311,321,331,341: transistor switch;
12: the second efferents; 41,411,412: the noble potential stabilizing circuit;
13: the three efferents; 42,421,422: the electronegative potential stabilizing circuit;
20: liquid crystal panel; 51: transistor 51;
21: first grid polar curve; 52: transistor 52;
22: the second grid line; 53: transistor 53;
23: the three gate lines; 54: electric capacity 54;
24: the four gate lines; 55: transistor 55;
25: the five gate lines; 56: transistor 56;
31: the first switches; 57: transistor 57;
32: second switch; 58: transistor 58;
33: the three switches; 59: transistor 59;
60: transistor 60; P2: the second unstable section;
61: the first control ends; T1: first period;
62: the second control ends; T2: second period;
63: input end; T3: the 3rd period;
64: output terminal; T4: the 4th period;
65: electric capacity 65; T5: the 5th period; And
P1: the first unstable section; Vdd: WV.
Embodiment
Below will the embodiment according to the gate line drive circuit of liquid crystal panel of the present invention be described with reference to relevant drawings, for the ease of understanding, the similar elements among the following embodiment is explained with identical Reference numeral.
Consult Fig. 3, it is the structural representation of gate line drive circuit of the present invention.Among the figure, gate line drive circuit comprises: chip for driving 10 comprises first efferent 11 and second efferent 12 at least; Liquid crystal panel 20 comprises first grid polar curve 21, second grid line 22 and the 3rd gate line 23 at least; First switch 31 and second switch 32.One end of first grid polar curve 21 electrically connects first efferent 11, and the other end electrically connects the control end of first switch 31.One end of the 3rd gate line 23 electrically connects second efferent 12, and the other end electrically connects the control end of second switch 32.One input end of first switch 31 electrically connects WV Vdd, and an output terminal of first switch 31 electrically connects an input end of second switch 32, and an output terminal of second switch 32 electrically connects earth point.One end of second grid line 22 then is electrically connected between the input end of output terminal and second switch 32 of first switch 31.
Continue to consult Fig. 4, it is the signal waveforms of gate line drive signal of the present invention.Among the figure, when first efferent 11 during at first period T1 output trigger voltage to first grid polar curve 21, first grid polar curve drive signal is a high potential state.At this moment, because first switch 31 receives the high potential signal from first grid polar curve 21, thereby makes the input end and the output terminal conducting of first switch 31, and then make an end of second grid line 22 be electrically connected to WV Vdd.At this moment, because second efferent 12 only provides the 3rd gate line 23 1 low-potential signals, so second switch 32 is in not on-state.So first grid polar curve drive signal and second grid line drive signal are high potential state in the first period T1.Next; When the second period T2; First efferent 11 provides low-potential signal to first grid polar curve 21 thereby cause the 31 not conductings of first switch, and second switch 32 also still is in not on-state, so second grid line drive signal still is in high potential state in the second period T2.At last, when second efferent 12 during at the 3rd period T3 output trigger voltage to the three gate lines 23, the 3rd gate line drive signal is a high potential state.At this moment, because second switch 32 receives the high potential signal from the 3rd gate line 23, thereby makes the input end and the output terminal conducting of second switch 32, and then make an end of second grid line 22 be electrically connected to earth point.Thus, first switch 31 and second switch 32 promptly capable of using makes second grid line drive signal in the second period T2, present high potential state, and when the 3rd period T3, presents low-potential state.
With reference to figure 5, it is the structural representation of the gate line drive circuit of one embodiment of the invention.Among the figure, first switch 311 is preferably transistor switch, and for cooperating the manufacture process of general liquid crystal panel drive circuit, transistor switch 311 preferably can be field-effect transistor (FET) switch, especially can be thin film transistor (TFT) (TFT FET) switch.Thus, the realization means of transistor switch 311 can be the light shield pattern of the former liquid crystal panel driving circuit of simple modification, thereby increase extra material cost hardly.In addition, because transistor switch 311 only uses as switch, therefore needn't painstakingly distinguish the constituent of source electrode (Source) and drain electrode (Drain).In like manner, second switch 321 also can be transistor switch.
Hold the above, the signal that the shortcoming of this gate line drive circuit is to receive many data lines when the pairing pixels of first grid polar curve 21 is when upgrading, and these signals can miss in the first period T1 plants in the second grid line 22 pairing pixels; When the second period T2, be updated to correct pixel data then again.Yet because the speed that pixel data upgrades is exceedingly fast, this negative effect can be discovered by naked eyes hardly, thereby can ignore.And this gate line drive circuit but can be saved down almost half efferent, that is only need the chip for driving 10 of almost half quantity can reach the effect identical with known techniques when driving hundreds of gate lines of a monoblock liquid crystal panel 20, and details are as follows now.
Please refer to the 6th figure, it is the structural representation of the gate line drive circuit of another embodiment of the present invention.Among the figure, first efferent 11 and second output port 12 drive the mode of first grid polar curves 21 and the 3rd gate line 23, and control the mode of second grid line 22 through first switch 31 and second switch 32, before being specified in, do not repeat them here.Please continue with reference to the 7th figure, when second efferent 12 when the 3rd period T3 exports a trigger voltage and gives the 3rd gate line 23, the 3rd gate line drive signal is a high potential state.At this moment, because the 3rd switch 33 receives the high potential signal from the 3rd gate line 23, thereby makes the input end and the output terminal conducting of the 3rd switch 33, and then make the 4th gate line 24 1 ends be electrically connected to WV Vdd.At this moment, because the 3rd efferent 13 only provides the 5th gate line 25 1 low-potential signals, therefore the 4th switch 34 is in not on-state.So the 3rd gate line drive signal and the 4th gate line drive signal are all high potential state in the 3rd period T3.Next; When the 4th period T4; Second efferent 12 provides low-potential signal to the 3rd gate line 23 thereby cause the 33 not conductings of the 3rd switch, and the 4th switch 34 also still is in not on-state, and therefore the 4th gate line drive signal still is in high potential state in the 4th period T4.At last, when the 3rd efferent 13 when the 5th period T5 exports a trigger voltage and gives the 5th gate line 25, the 5th gate line drive signal is a high potential state.At this moment, because the 4th switch 34 receives the high potential signal from the 5th gate line 25, thereby makes the input end and the output terminal conducting of the 4th switch 34, and then make an end of the 4th gate line 24 be electrically connected to earth point.Thus, the 3rd switch 33 promptly capable of using and the 4th switch 34 make the 4th gate line drive signal in the 4th period T4, present high potential state, and when the 5th period T5, present low-potential state.
Hold the above; By finding out among the figure; The signal that the shortcoming of this gate line drive circuit is to receive many data lines when first grid polar curve 21 and the pairing pixels of the 3rd gate line 23 is when upgrading; These signals can miss in the first period T1 plants in the second grid line 22 pairing pixels, and mistake is planted in the 4th gate line 24 pairing pixels in the 3rd period T3; When the second period T2 and the 4th period T4, be updated to correct pixel data then respectively again.Yet because the speed that pixel data upgrades is exceedingly fast, this negative effect can be discovered by naked eyes hardly, thereby can ignore.And this gate line drive circuit 3 output ports capable of using drive 5 gate lines, that is only need the chip for driving 10 of almost half quantity can reach the effect identical with prior art.
Next, with reference to figure 8, it is the structural representation of the gate line drive circuit of further embodiment of this invention.Among the figure, first switch 311 can be preferably that transistor switch, second switch 321 preferably can be transistor switch, the 3rd switch 331 preferably can be transistor switch, and the 4th switch 341 also can be preferably transistor switch.Wherein, transistor switch 321 drives with transistor switch 331 same leads capable of using.
With reference to figure 9, it is the signal waveforms of the gate line drive signal of another embodiment of the present invention.Because second grid line drive signal in the second period T2, is all carried out electrical isolation through first switch 31 with second switch 32 with WV Vdd and earth point.Therefore, second grid line drive signal can present unsettled noble potential in the second period T2, shown in the first unstable section P1; In addition, though second grid line drive signal has been electrically connected to earth point through second switch 32 when the 3rd period T3, still possibly produce phenomenons such as floating ground because second switch 32 receives electromagnetic interference (EMI), shown in the second unstable section P2.Therefore, for solving the jitter problem, the present invention proposes a solution as follows.
With reference to Figure 10, it is the gate line drive circuit of one embodiment of the invention and the structural representation of current potential stabilizing circuit.Among the figure, the present invention proposes a noble potential stabilizing circuit 41 and an electronegative potential stabilizing circuit 42 in addition, with the unsteady phenomenon of the current potential that solves the first unstable section P1 and the second unstable section P2.Explain for convenient, omit the diagram of chip for driving and output port thereof among the figure.Wherein, Noble potential stabilizing circuit 41 can be realized by thin film transistor switch simply; The control end of this thin film transistor switch can be electrically connected at the output terminal of first switch 31; The input end of this thin film transistor switch then is electrically connected at WV Vdd, and the output terminal of this thin film transistor switch is electrically connected at second grid line 22.Thus; When first grid polar curve 21 presents low-potential state and causes first switch 31 to be closed in the second period T2; Trigger noble potential stabilizing circuit 41 owing to second grid line 22 still is in high potential state, and then make second grid line 22 and WV Vdd electrically connect through the output terminal and the output terminal of noble potential stabilizing circuit 41.Therefore, second grid line 22 can obtain replenishing of WV Vdd and avoid unsteady at the high potential state of the second period T2.
In like manner, electronegative potential stabilizing circuit 42 preferably can be the thin film transistor (TFT) logic switch.The input end 63 of this thin film transistor (TFT) logic switch is electrically connected at second grid line 22; The output terminal 64 of this thin film transistor (TFT) logic switch is electrically connected at earth point; First control end 61 of this thin film transistor (TFT) logic switch is electrically connected at second grid line 22 then, and 62 of second control ends of this thin film transistor (TFT) logic switch are electrically connected at the 3rd gate line 23.Thus; When the signal of second grid line 22 is that the signal of logic low potential and the 3rd gate line 23 is when being logic high potential; That is the 3rd during period T3; The input end 63 and output terminal 64 conductings of this thin film transistor (TFT) logic switch, and second grid line 22 is electrically connected to earth point, to eliminate the second unstable section P2.
Next, for asking comprehensive, the present invention provides a kind of detailed structure of thin film transistor (TFT) logic switch following in one embodiment.With reference to Figure 11, it is the structural representation of the electronegative potential stabilizing circuit of one embodiment of the invention.Explain for convenient, second grid line 22, the 3rd gate line 23 and electronegative potential stabilizing circuit 421 only are shown among the figure.Wherein, electronegative potential stabilizing circuit 421 comprises transistor 51, transistor 52, transistor 53 and electric capacity 54.Its detailed annexation is shown in figure 11, repeats no more at this.Explain that at present its working method is following, when the second period T2, second grid line 22 is in noble potential and the 3rd gate line 23 is in electronegative potential.At this moment; Transistor 51 because second grid line 22 and conducting and transistor 52 because the 23 not conductings of the 3rd gate line; And then cause transistor 53 not conductings; Therefore second grid line 22 is still kept high potential state when the second period T2, can not have a negative impact because of electronegative potential stabilizing circuit 421.When the 3rd period T3, second grid line 22 is in electronegative potential and the 3rd gate line 23 is in noble potential.At this moment, transistor 51 is because second grid line 22 and not conducting, and transistor 52 is because the 3rd gate line 23 and conducting, so with the grid of the noble potential feed-in transistor 53 of the 3rd gate line 23 with conducting it.Thus, second grid line 22 is electrically connected to earth point through transistor 53, with the unsteady phenomenon of the current potential that solves the second unstable section P2.Certainly, those of ordinary skills can know the electronegative potential stabilizing circuit 42 of other species structure based on above-mentioned detailed structure easily by inference, and not break away from spirit of the present invention.
Next, in order to confirm that noble potential stabilizing circuit 41 and electronegative potential stabilizing circuit 42 can coexist and do not produce antagonism.The present invention proposes the structural representation of current potential stabilizing circuit in one embodiment, and is shown in figure 12.Among the figure, the annexation of each member and local working method are described in detail in front, repeat no more at this.It is following only to describe actual working state: when the first period T1; First grid polar curve 21 is in noble potential and causes transistor switch 311 conductings; The 3rd gate line 23 is in electronegative potential and causes transistor switch 321 not conductings, noble potential stabilizing circuit 411 conductings this moment and the 421 not conductings of electronegative potential stabilizing circuit.When the second period T2, first grid polar curve 21 and the 3rd gate line 23 all are in electronegative potential and cause transistor switch 311 and transistor switch 321 not conductings, yet cause 411 conductings of noble potential stabilizing circuit owing to second grid line 22 still is in high potential state.When the 3rd period T3; Since transistor switch 321 conductings and with the current potential of second grid line 22 toward drop-down; Cause the gate drive voltage of noble potential stabilizing circuit 411 not enough and close, so noble potential stabilizing circuit 411 not conducting noble potential electronegative potential stabilizing circuits 421 conducting electronegative potential then.At last, the present invention also proposes the structural representation of another kind of current potential stabilizing circuit in one embodiment, and with reference to Figure 13, it is the structural representation of the current potential stabilizing circuit of one embodiment of the invention.This current potential stabilizing circuit comprises a noble potential stabilizing circuit 412 and an electronegative potential stabilizing circuit 422.This noble potential stabilizing circuit 412 comprises transistor 55 and transistor 56; This electronegative potential stabilizing circuit 422 comprises transistor 57, transistor 58, transistor 59, transistor 60 and electric capacity 65.Wherein the input end of transistor 55 and control end all are electrically connected at first grid polar curve 21, and the output terminal of transistor 55 then is electrically connected at the input end of transistor 57, the control end and the second grid line 22 of transistor 56.The input end of transistor 56 is electrically connected at WV Vdd, and the output terminal of transistor 56 then is electrically connected at second grid line 22.The output head grounding of transistor 57, transistor 58 and transistor 60.The output terminal of the control end of transistor 57 and transistor 60, the input end of transistor 58 and transistor 59 all is electrically connected at an end of electric capacity 65, and the other end of electric capacity 65 is ground connection then.Transistor 57 is electrically connected at second grid line 22 with the input end of transistor 60, and the control end of transistor 59 and input end then are electrically connected at the 3rd gate line 23.
Hold the above, explain that at present the working method of its stable potential is following: when the first period T1, first grid polar curve 21 is in noble potential and causes transistor switch 311 conductings, and the 3rd gate line 23 is in electronegative potential and causes transistor switch 321 not conductings.At this moment, transistor 55 causes second grid line 22 to be in noble potential with transistor 56 equal conductings.Meanwhile, because second grid line 22 is in noble potential, transistor 58 conductings; And because the 3rd gate line 23 is in electronegative potential, transistor 59 not conductings.Therefore, transistor 58 is delivered to ground voltage the control end of transistor 57 and transistor 60; And then cause transistor 57 and transistor 60 not conductings.When the second period T2; First grid polar curve 21 and the 3rd gate line 23 all are in electronegative potential; Yet cause transistor 56 conductings owing to second grid line 22 still is in high potential state, and then make second grid line 22 when the second period T2, still stably maintain high potential state.When the 3rd period T3, the 3rd gate line 23 is in noble potential, thereby causes transistor 59 conductings; After transistor 59 conductings, transistor 57 and transistor 60 also and then conducting, wherein the purpose of electric capacity 65 is to stablize the noble potential of the 3rd gate line 23.At this moment, toward drop-down, the gate drive voltage that causes transistor 56 is not enough and close with the current potential of second grid line 22 for transistor 57 and transistor 60, so noble potential stabilizing circuit 412 not conducting noble potential electronegative potential stabilizing circuits 422 conducting electronegative potential then.
The above is merely exemplary, but not is restrictive.Anyly do not break away from spirit of the present invention and scope, and, all should be included in the scope of appending claims its equivalent modifications of carrying out or change.
Claims (7)
1. gate line drive circuit, it comprises:
Chip for driving comprises first efferent and second efferent at least;
Liquid crystal panel comprises first grid polar curve, second grid line and the 3rd gate line at least;
First switch; And
Second switch;
Wherein, One end of said first grid polar curve electrically connects said first efferent; The other end electrically connects the control end of said first switch, and an end of said the 3rd gate line electrically connects said second efferent, and the other end electrically connects the control end of said second switch; And the input end of said first switch electrically connects WV; The output terminal of said first switch electrically connects the input end of said second switch, and the output terminal of said second switch electrically connects earth point, and an end of said second grid line is electrically connected between the said input end of said output terminal and said second switch of said first switch.
2. gate line drive circuit according to claim 1, wherein said first switch is a thin film transistor switch.
3. gate line drive circuit according to claim 1, wherein said second switch are thin film transistor switch.
4. gate line drive circuit according to claim 1 also comprises the noble potential stabilizing circuit, to stablize the high potential signal of said second grid line.
5. gate line drive circuit according to claim 4; Wherein said noble potential stabilizing circuit can be thin film transistor switch; The control end of said thin film transistor switch is electrically connected at the said output terminal of said first switch; And the input end of said thin film transistor switch is electrically connected at said WV, and the output terminal of said thin film transistor switch is electrically connected at said second grid line.
6. gate line drive circuit according to claim 1 also comprises the electronegative potential stabilizing circuit, to stablize the low-potential signal of said second grid line.
7. gate line drive circuit according to claim 6; Wherein said electronegative potential stabilizing circuit can be the thin film transistor (TFT) logic switch; The input end of said thin film transistor (TFT) logic switch is electrically connected at said second grid line; The output terminal of said thin film transistor (TFT) logic switch is electrically connected at said earth point; First control end of said thin film transistor (TFT) logic switch is electrically connected at the second grid line, and second control end of said thin film transistor (TFT) logic switch is electrically connected at said the 3rd gate line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101650932A CN101989412B (en) | 2009-07-30 | 2009-07-30 | Gate line driving circuit of liquid crystal panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101650932A CN101989412B (en) | 2009-07-30 | 2009-07-30 | Gate line driving circuit of liquid crystal panel |
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| Publication Number | Publication Date |
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| CN101989412A CN101989412A (en) | 2011-03-23 |
| CN101989412B true CN101989412B (en) | 2012-07-04 |
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| CN2009101650932A Expired - Fee Related CN101989412B (en) | 2009-07-30 | 2009-07-30 | Gate line driving circuit of liquid crystal panel |
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| CN106910452B (en) * | 2017-05-05 | 2019-02-15 | 京东方科技集团股份有限公司 | Shift register cell, its driving method, gate driving circuit and display device |
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