CN101980225B - Method for implementing testability analysis and diagnosis decision system for electronic products - Google Patents

Method for implementing testability analysis and diagnosis decision system for electronic products Download PDF

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CN101980225B
CN101980225B CN 201010545014 CN201010545014A CN101980225B CN 101980225 B CN101980225 B CN 101980225B CN 201010545014 CN201010545014 CN 201010545014 CN 201010545014 A CN201010545014 A CN 201010545014A CN 101980225 B CN101980225 B CN 101980225B
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testability
fault
analysis
information
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CN101980225A (en
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连光耀
黄鑫
黄考利
孙江生
吕晓明
刘晓芹
魏忠林
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63908 Troops of PLA
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Abstract

The invention relates to a method for implementing a testability analysis and diagnosis decision system for electronic products and is applied to the field of electronic product design. The method comprises the following steps of: (1) arranging a testability design modeling module which comprises a graphical testability model of equipment, testability design information integration and description, and testability information acquisition and testability information storage; (2) arranging an inherent testability analysis module which comprises fault coverage analysis, fault ambiguity group discrimination, and redundancy testing analysis; and (3) arranging an actual testability analysis module which comprises diagnosis strategy generation and testability design result analysis. The invention has the advantages that: (1) the situation of deficiency of testability assisted software in China is changed, and the method is used for performing testability verification and analysis on complex electronic products; (2) each functional unit of the system can be independently used, and the system has good expandability; and (3) inherent testability analysis function and actual testability analysis function can be provided for the electronic products.

Description

A kind of electronic product testability analysis and the implementation method of diagnosing decision system
Technical field
The present invention relates to a kind of electronic product testability analysis and the implementation method of diagnosing decision system, be mainly used in the testability check analysis of sophisticated electronic product.
Background technology
At present, the testability design has progressively become design attributes of equal importance with reliability design in the design of electronic products, and it requires just to consider synchronously test problem in the beginning of design of electronic products, and carries out testability analysis work.The shortage of assistant analysis instrument is " bottleneck " that restriction China testability design level improves always for a long time.Although domestic testability research has obtained some achievements, the testability designing technique still rests on the level of assimilating foreign technology.Especially aspect the exploitation of testability Autocad, although many fruitful work have been done by many units, mostly all be in laboratory stage, the aid that is not shaped is applied in the actual product testability design and analysis process.Therefore, product development department has to buy the testability Autocad of external costliness, and this type of software is mostly expensive, makes research institute bear tremendous economic pressure, increases design cost.In addition, because software is offshore company's exploitation, not only core technology rests in others' hand, and also has the risk at implanted back door, relies on for a long time these softwares and can make China under one's control, brings hidden danger to national security.
Summary of the invention
Technical matters to be solved by this invention provides a kind of electronic product testability analysis and the implementation method of diagnosing decision system, is used for the testability check analysis of sophisticated electronic product.
For solving the problems of the technologies described above, the technical solution used in the present invention is: the present invention includes testability design setting model module, intrinsic testability analysis module, actual testability analysis module and input/output module, concrete steps are as follows:
(1) testability design setting model module:
Set up the patterned testability model of equipment by improved many signal flow diagrams model, adopt the information model method to realize that the testability design information is integrated, describe with XML-based method realization information, use improved depth-first search traversing graph algorithm to obtain correlation matrix from the patterned testability model of described equipment, realize the testability acquisition of information, adopt improvement orthogonal list method to carry out the storage of testability information;
The implementation method of described improved many signal flow diagrams model is as follows:
Figure DEST_PATH_IMAGE001
Hierarchical structure: product model is divided into 7 layers, and every one deck all adopts the modeling pattern of many signal flow diagrams, each straton unit as one independently integral body carry out refinement, obtain down from level to level aggregated(particle) structure, adopt the modeling of many signal flow diagrams;
Figure 2010105450143100002DEST_PATH_IMAGE002
Fault mode: define a class special module and realize the fault mode modeling; In described special module, each fault mode only allows to carry out modeling for a functional fault, when described fault mode has carried out the fault mode modeling for a parts, the fault mode title appears in the functional attributes of described parts automatically, and the functional fault rate of described parts is obtained by the failure rate accumulation of the fault mode of described parts;
Figure DEST_PATH_IMAGE003
Single input, single efferent modular construction: be Account Dept's assembly module organization definition of many signal flow diagrams singly input, single output form, the signal that defines in the described Account Dept assembly module transmits at directed line by interface;
(2) intrinsic testability analysis module:
Carry out the analysis of fault coverage condition, the differentiation of fault ambiguity group and redundancy testing analysis according to the information of described testability design setting model module; Described fault coverage condition analysis and utilization test approachability analysis obtains " fault that can not be detected " information, it is quantity and the size that finds the fault ambiguity group that a plurality of duplicate row vectors consist of in the correlation matrix that described fault ambiguity group is differentiated, and described redundancy testing analysis is that test event corresponding to identical column vector in the described correlation matrix only kept one;
(3) actual testability analysis module:
According to the testability design information of described intrinsic testability analysis module, carry out Diagnostic Strategy and generate and the analysis of testability design result;
It is exactly generation system fault diagnosis tree information that described Diagnostic Strategy generates, and it comprises two processes:
Figure 269589DEST_PATH_IMAGE001
Test event is selected: adopt a kind of analytical approach of scale-of-two particle group optimizing to find system's Minimal completeness test event set;
Figure 186729DEST_PATH_IMAGE002
Diagnosing sequence is optimized: call system's Minimal completeness test event set that previous step generates, adopt the correlation models method completion system fault diagnosis work that improves;
The analysis of described testability design result is to calculate the testability design objective of equipping under current Fault Diagnosis Strategy, described testability design objective comprises fault detect rate, Percent Isolated, fault ambiguity group quantity and size, mean time to detection, mean failure rate isolation time, fault isolation validity and the system qualification rate of resurveying, and utilizes the testability index definition standard of IEEE Std 1522-2004 standard to set up the Measurement criterion of described testability design objective.
7 layers that product model is divided into of hierarchical structure described in the step (1) comprise system layer, subsystem layer, LRU layer, SRU layer, module layer, submodule layer, device layer and fault mode layer.
Information model method described in the step (1) by the physical entity in the labeled test environment, behavior entity and data entity describe imperfectly the equipment and its each information entity between relation.
" fault that can not be detected " described in the step (2) information is exactly the failure message of complete " 0 " row in the described correlation matrix.
The analytical approach of scale-of-two particle group optimizing comprises the steps: described in the step (3)
Step 1 constitutes the optimum results that a test event is selected, initialization population: initial position and the initial velocity of setting at random each particle with each particle;
Step 2 is calculated the corresponding equipment Test design result of each particle;
Step 3, for each particle, the result of the desired positions pbest that the comparison corresponding testability design result of current location and it live through, if better than pbest, renewal pbest is current location, otherwise does not upgrade pbest;
Step 4, to all particles in the population, select the best pbest in a body position as population desired positions gbest, if the population desired positions of current time is not worse than former desired positions, gbest with current time is updated among the former gbest result so, otherwise does not upgrade gbest;
Step 5 is upgraded all particle positions;
Step 6 if reach the termination condition of iterations maximum, then finishes, otherwise turns step 2.
The implementation procedure of improving the correlation models method described in the step (3) is as follows: the detection and the isolation weights that at first calculate each test point, judge the execution sequence of test point by the weights size, take the preferred result of test point as the basis, detect afterwards first and isolate, formulate Diagnostic Strategy with the sequencing that test point is selected.
The beneficial effect that adopts technique scheme to produce is:
(1) changed China and lacked the situation that the testability assistant software designs, be used for the sophisticated electronic product is carried out the testability check analysis.
(2) each functional unit of native system can independently use, and possesses good extensibility.
(3) can provide intrinsic testability analysis function and actual testability analysis function to electronic product.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 1 is structured flowchart of the present invention;
Fig. 2 is the structured flowchart of testability design setting model module among the present invention;
Fig. 3 is the structured flowchart of intrinsic testability analysis module among the present invention;
Fig. 4 is the structured flowchart of actual testability analysis module among the present invention;
Fig. 5 is simulative automobile training simulation system structured flowchart in the embodiment of the invention;
Fig. 6 is simulative automobile training simulation system testability design setting model structured flowchart in the embodiment of the invention;
Fig. 7 is fault diagnosis tree structured flowchart in the embodiment of the invention.
Embodiment
By Fig. 1-4 as can be known, a kind of electronic product testability analysis and the implementation method of diagnosing decision system, it comprises testability design setting model module, intrinsic testability analysis module, actual testability analysis module and input/output module, the specific implementation step is as follows:
(1) testability design setting model module:
Set up the patterned testability model of equipment by improved many signal flow diagrams model, adopt the information model method to realize that the testability design information is integrated, describe with XML-based method realization information, use improved depth-first search traversing graph algorithm to obtain correlation matrix from the patterned testability model of described equipment, realize the testability acquisition of information, adopt improvement orthogonal list method to carry out the storage of testability information;
This module is carried out the testability design setting model to Complex electronic equipments, realizes the model description to the equipment Test design, and concrete grammar is as follows:
Figure 28783DEST_PATH_IMAGE001
Equip patterned testability model:
The basis of realizing the testability design and analysis is to set up effective testability model.The present invention adopts improved many signal flow diagrams model to carry out the equipment Test modeling, and concrete methods of realizing is:
Figure 2010105450143100002DEST_PATH_IMAGE004
. the hierarchical structure definition, Hierarchical Design characteristics for equipment, also adopt the method for designing of stratification to improve to many signal flow diagrams model, the patterned testability model of described equipment is divided into 7 layers: system layer, subsystem layer, the LRU(Field Replaceable Unit) layer, SRU(internal field replaceable units) layer, module layer, the submodule layer, device layer, the fault mode layer, every one deck all adopts many signal flow diagrams modeling pattern, the subelement of every one deck again as one independently integral body carry out refinement, obtain the hierarchical structure of lower one deck, and adopt many signal flow diagrams to carry out modeling;
Figure DEST_PATH_IMAGE005
. the fault mode definition, realize the fault mode modeling by defining a class certain moduli piece, in the fault mode module, stipulate that each fault mode only allows to carry out modeling for a certain functional fault, if carried out the fault mode modeling for a parts, the fault mode title appears in the functional attributes of this parts automatically so, and the functional fault rate of this parts is obtained by the probability of malfunction accumulation of its fault mode;
Figure 2010105450143100002DEST_PATH_IMAGE006
. single input, the parts organization definition of single output, consider the intuitive of modeling and the convenience of modelling verification, be single input with the Account Dept's assembly module organization definition in many signal flow diagrams, the form of single output, correlativity between the fault of described Account Dept assembly module and the test is connected signal embodiment by definition, all signals that define in the described Account Dept assembly module transmit at the directed connection line by interface, the function that defines in the described Account Dept assembly module can both propagate in its latter linked test point module, which test event is specifically tested defined by the user for which function, use more intuitively, the modeling Accuracy Verification is convenient.
Figure 610943DEST_PATH_IMAGE002
Integrated and the description of testability design information:
The equipment Test design information is integrated to be the data storage problem that solves equipment Test design relevant information, is the description of patterned testability model in database.The testability design information of Complex electronic equipments has stratification, structures, and therefore, information is integrated take hierarchical information and structural information as main body, carries out integrated to function information, detecting information, diagnostic message, the repair message of equipment department's assembly.
The present invention adopts the testability design information integrated approach of information model.By the physical entity in the labeled test environment, behavior entity and data entity describe imperfectly the equipment and its each information entity between relation, the purpose that the information that reaches is integrated.
The information of carrying out on the integrated basis of the information of finishing is described, and the present invention adopts the method for XML-based, and detailed process is as follows:
Figure 425315DEST_PATH_IMAGE004
. the information of analytical equipment testability design information entity is described demand, sets up data structuring model;
Figure 310095DEST_PATH_IMAGE005
. set up the peculiar markup language of field of automatic testing, determine that testability designs the Schema of different information entities, this Schema namely is that this information is described requirement definition, also is the structural model of testability design information entity;
Figure 636515DEST_PATH_IMAGE006
. generate XML document according to Schema, document is checked and verifies;
Figure DEST_PATH_IMAGE007
. the XML-based document realizes that the information between the testability design information entity is integrated, exchange and shared.
Figure 960049DEST_PATH_IMAGE003
The testability acquisition of information:
The patterned testability model of described equipment is carried out the extraction of relevant information to obtain the equipment correlation matrix, this process is similar to traversal digraph problem, adopts Depth Priority Algorithm, and its basic thought is:
All summits are not accessed in assumed initial state figure below, then depth-first search can be from figure certain vertex v, after accessing this summit, successively from the not accessed abutment points depth-first traversal figure of v, until the summit that all and v have the path to communicate among the figure all is accessed to: if still have the summit not accessed among the figure this moment, then starting point is made on not accessed summit among the alternative figure, repeats said process, until till all summits all are accessed among the figure.
This is the process of a recurrence.In the algorithm implementation procedure, whether accessed for the ease of distinguishing the summit, set up access flag array visited[0 n-1], its initial value is " false ", in case certain summit is accessed, then its corresponding component is set to " true ".
Because the patterned testability model of described equipment is not simple digraph, also comprise test node, at the incidence relation that the patterned testability model of described equipment is carried out will judging in the ergodic process test node and intermodule, realize that concrete steps are as follows so adopt improved depth-first search traversing graph algorithm:
Figure 628928DEST_PATH_IMAGE004
. for showing whether test node of access summit, set up access array test[0 n-1], its initial value is made as " false ", in case certain accessed summit is test node, its corresponding component is set to " true ";
Figure 684609DEST_PATH_IMAGE005
. be 0 test node beginning ergodic process from the visited value, the visited value of this test point of mark is 1, and reverse traversal testability designs a model, until all traverse with the reverse module that communicates of this test point among the figure;
Figure 501255DEST_PATH_IMAGE006
If. have access to test point in the ergodic process, and its visited and tested value all be 1, then return last layer and continue ergodic process that if its visited value is 0, and the tested value is 1, the continuation ergodic process.
Figure 2010105450143100002DEST_PATH_IMAGE008
The storage of testability information:
Correlation matrix has neutral element characteristics more, in large scale, and is higher to data structural design space availability ratio, and the present invention adopts improved orthogonal list method to come the memory dependency matrix, and concrete structure is as follows:
Typedef?struct?node
{
int?i,j;
struct?node?*right,*down
}NODE
(2) intrinsic testability analysis module:
This module is take the information of described testability design setting model module as foundation, and implementation method is as follows:
Figure 300584DEST_PATH_IMAGE001
The fault coverage condition is analyzed:
Utilize the test approachability analysis, obtain " fault that can not be detected " information, ultimate principle is according to described correlation matrix analysis, in described correlation matrix fault of complete " 0 " row be exactly can not be tested fault;
The fault ambiguity group is differentiated:
Purpose is in order to find " fault ambiguity group size and number " information, discrimination principles is: the corresponding fault of a plurality of duplicate row vectors consists of a fault ambiguity group in the described correlation matrix, and the quantity of fault is exactly the ambiguity group size in the described fault ambiguity group;
Figure 316130DEST_PATH_IMAGE003
Redundancy testing is analyzed:
Purpose is to obtain " unnecessary test event " information, and analysis principle is: exist redundantly in the described correlation matrix between test event corresponding to identical column vector, only keep one, other test events are processed as " unnecessary test event ".
(3) actual testability analysis module:
Testability design information behind the described intrinsic testability analysis is as foundation, and concrete steps are as follows:
Figure 620072DEST_PATH_IMAGE001
Diagnostic Strategy generates:
" system fault diagnosis tree " information of generation comprises following two processes:
Figure 960443DEST_PATH_IMAGE004
. test event is selected:
Find the set of equipment Minimal completeness test event, adopt a kind of analytical approach of scale-of-two particle group optimizing, concrete steps are as follows:
Step 1 constitutes the optimum results that test event is selected with each particle, and the initialization population is set initial position and the speed of each particle at random;
Step 2 is calculated equipment Test design result corresponding to each particle;
Step 3 is for each particle, the result of the desired positions pbest that lives through of the corresponding testability design result of current location and it relatively, if better than pbest, renewal pbest is current location, otherwise does not upgrade pbest;
All particles in the step 4 pair population, select the best pbest in a body position as population desired positions gbest, if the population desired positions of current time is not worse than former desired positions, the gbest with current time is updated among the former gbest result so, otherwise does not upgrade gbest;
Step 5 is upgraded all particle positions;
If step 6 reaches as a result condition (being that iterations reaches maximum), then finish, carry out otherwise turn step 2.
The complexity of the method is system's acceptable, by manual control iterations and number of particles, can reduce program execution time.
Figure 603913DEST_PATH_IMAGE005
. diagnosing sequence optimization:
Gather to come the work of completion system fault diagnosis by calling the equipment Minimal completeness test event that described test event selects to obtain, employing realizes based on improved correlation models method: the detection and the isolation weights that calculate each test point, judge the execution sequence of test point by the weights size, formulate Diagnostic Strategy take the preferred result of test point as the basis, detect afterwards first and isolate, formulate Diagnostic Strategy with the sequencing that test point is selected.
Figure 1397DEST_PATH_IMAGE002
The testability design result is analyzed:
The equipment Test design objective of calculating under current Fault Diagnosis Strategy comprises fault detect rate, Percent Isolated, fault ambiguity group quantity and size, mean time to detection, mean failure rate isolation time, fault isolation validity, the system qualification rate etc. of resurveying.For many indexs of testability, term name disunity, definition also inconsistent present situation, the present invention has used the definition standard of the testability index of IEEE Std 1522-2004 standard, and the supposed premise of single fault only appears based on system's synchronization, set up above-mentioned testability design Measurement criterion.Be respectively:
Fault detect rate (FDR)
Be defined as in setting time, by built-in test equipment (Built-In Test Equipment, BITE) and (or) external test facility (External Test Equipment, the ETE) number of faults that correctly detects and the ratio of fault sum.
Nonweighted fault detect rate computing method are:
Wherein, N T---the fault sum that occurs during the system works;
The number of defects that can be detected.
The fault detect rate computing method of weighting are:
Wherein, λ i---the probability of happening of i fault;
N D, N TDefine the same.
Figure 792635DEST_PATH_IMAGE005
. Percent Isolated (FIR)
Be commonly defined as in setting time, by BITE and (or) ratio of the number of faults that detects within the number of faults of the small source of trouble number in stipulating of set and the same time of the correct isolation of ETE, represent with percentage.During actual computation, the source of trouble need to be divided into a plurality of separate fault isolation ambiguity group, each fault isolation ambiguity group includes the source of trouble (number of the source of trouble is exactly the ambiguity group size) of some, and fault isolation is carried out towards the fault isolation ambiguity group.
Nonweighted Percent Isolated computing method are:
Figure DEST_PATH_IMAGE009
FIR UWi---the source of trouble is isolated to the ambiguity group size and equals iNon-weighting Percent Isolated;
N i---under rated condition, equal to the ambiguity group size with the correct isolation of prescriptive procedure iSource of trouble number;
The fault of L---regulation can equal N every the ambiguity group size without L under the restraint condition D
N DDefine the same.
The Percent Isolated computing method of weighting are:
Figure DEST_PATH_IMAGE010
Wherein, FIR Wj---the source of trouble is isolated to the ambiguity group size and equals jThe weighting Percent Isolated;
L j---under rated condition, equal to the ambiguity group size with the correct isolation of prescriptive procedure jSource of trouble number;
L, λ i, N DDefine the same.
. fault isolation ambiguity group size (AGS)
The fault isolation ambiguity group is corresponding with the Percent Isolated index, and the number that comprises the source of trouble in the fault ambiguity group that obtains after the fault isolation is exactly the size (AGS) of current fault isolation ambiguity group.
The fault isolation ambiguity group size (AGS) of whole system is based on weighting Percent Isolated index and calculates, and computing method are:
Figure DEST_PATH_IMAGE011
Wherein, FIR Wi---the source of trouble is isolated to the ambiguity group size and equals iThe weighting Percent Isolated;
The L definition is the same.
D. mean time to detection (MFDT)
Refer to after a fault occurs, detect and indicate the mean value of this fault required time by BITE/ETE.Its mathematical model can be expressed as:
Figure DEST_PATH_IMAGE012
t Di---BIT/ETE detects and indicates i detectable failure required time;
Define the same.
Mean failure rate testing cost (MFDC)
Refer to after a fault occurs, detect and indicate the mean value of the required expense of this fault by BITE/ETE.Its mathematical model can be expressed as:
Figure DEST_PATH_IMAGE013
C Di---BIT/ETE detects and indicates i the required expense of detectable failure;
Define the same.
Fault isolation validity (IE)
Refer to that given fault diagnosis model can reach the degree of maximum fault isolation (isolation is to the single source of trouble), be based on the failure rate weighted calculation and obtain that the reasoning and calculation formula is:
Figure DEST_PATH_IMAGE014
FIR Wj---the source of trouble is isolated to the weighting Percent Isolated that the ambiguity group size equals j;
The L definition is the same.
Obviously, be 1 fault ambiguity group if system only has a class size, IE=1 so.
G. the qualification rate of resurveying (RTOK)
RTOK is used for characterizing false-alarm to the impact that system causes, and refers to the probability of happening that the source of trouble is isolated by mistake in the system, and computing formula is:
Figure DEST_PATH_IMAGE015
Wherein, FIR Wj---the source of trouble is isolated to the weighting Percent Isolated that the ambiguity group size equals j;
The L definition is the same.
Embodiment shown in Fig. 5-7 is the testability analysis that carries out as example take the simulative automobile training simulation system of certain unit exploitation.The effect of described analogue system mainly is by real scene simulation training driver, reduces driver's training cost.Fig. 5 is the structured flowchart of described simulative automobile training simulation system.The below describes its each functional module:
(1) MIM message input module such as road conditions, driving (being designated as M1) is the interactive interface of system and extraneous control desk;
(2) pavement behavior signal formation part: PT80-1M(is designated as M2);
(3) information of road surface forms and the information part: PT61-3M(is designated as M3), PT61-2M(is designated as M4), PT61-1M(is designated as M5) and spatial information simulate (being designated as M6);
(4) driving information forming section: PT62-1(is designated as M7), PT62-2(is designated as M8), PT62-15(is designated as M9);
(5) television optics signal formation part: PT85-2(is designated as M10);
(6) automatic Pilot and each system connect the simulation part: PT03-1M(is designated as M11);
(7) condition of the vehicle indicating section: indication information forming section (being designated as M12), the PT52-1(such as automobile instrument, car light are designated as M13), PT52-2(is designated as M14).
This system has 14 modules, and (M1～M14), system's input is designated as IN1 and IN2, supposes a corresponding class functional fault of output of each module, and probability of malfunction equates.Therefore, the component units in this system integrates as C={M1, M2 ..., M14}, set of signals is S={FN1, FN2, FM1-1, FM1-2, FM1-3, FM1-4, FM2-1, FM2-2, FM3-1, FM3-2, FM4, FM5, FM6, FM7, FM8-1, FM8-2, FM9-1, FM9-2, FM10, FM11, FM12-1, FM12-2, FM13, FM14} arranges a test at each output terminal, and all test event settings are (T1～T22) as shown in Figure 5.
Simulative automobile training simulation system testability design setting model structured flowchart as shown in Figure 6.Fault diagnosis tree structured flowchart after utilizing method among the present invention to analyze as shown in Figure 7.Testability design objective report after utilizing method among the present invention to analyze comprises fault detect rate, Percent Isolated, fault ambiguity group size, fault isolation validity, the qualification rate of resurveying, mean test time and average testing expense situation.

Claims (4)

1. an electronic product testability analysis and diagnosis decision system is characterized in that described system comprises testability design setting model module, intrinsic testability analysis module, actual testability analysis module and input/output module:
(1) testability design setting model module:
Set up the patterned testability model of equipment by improved many signal flow diagrams model, adopt the information model method to realize that the testability design information is integrated, describe with XML-based method realization information, use improved depth-first search traversing graph algorithm to obtain correlation matrix from the patterned testability model of described equipment, realize the testability acquisition of information, adopt improvement orthogonal list method to carry out the storage of testability information;
The implementation method of described improved many signal flow diagrams model is as follows:
1. hierarchical structure: the patterned testability model of equipment is divided into 7 layers, and every one deck all adopts the modeling pattern of many signal flow diagrams, each straton unit as one independently integral body carry out refinement, obtain down from level to level aggregated(particle) structure, adopt the modeling of many signal flow diagrams;
2. fault mode: define a class special module and realize the fault mode modeling; In described special module, each fault mode only allows to carry out modeling for a functional fault, when described fault mode has carried out the fault mode modeling for a parts, the fault mode title appears in the functional attributes of described parts automatically, and the functional fault rate of described parts is obtained by the failure rate accumulation of the fault mode of described parts;
3. single input, single efferent assembly module structure: be Account Dept's assembly module organization definition of many signal flow diagrams singly input, single output form, the signal that defines in the described Account Dept assembly module transmits at directed line by interface;
(2) intrinsic testability analysis module:
Carry out the analysis of fault coverage condition, the differentiation of fault ambiguity group and redundancy testing analysis according to the information of described testability design setting model module; Described fault coverage condition analysis and utilization test approachability analysis obtains " fault that can not be detected " information, it is quantity and the size that finds the fault ambiguity group that a plurality of duplicate row vectors consist of in the correlation matrix that described fault ambiguity group is differentiated, and described redundancy testing analysis is that test event corresponding to identical column vector in the described correlation matrix only kept one;
(3) actual testability analysis module:
According to the testability design information of described intrinsic testability analysis module, carry out Diagnostic Strategy and generate and the analysis of testability design result;
It is exactly generation system fault diagnosis tree information that described Diagnostic Strategy generates, and it comprises two processes:
1. test event is selected: adopt a kind of analytical approach of scale-of-two particle group optimizing to find system's Minimal completeness test event set;
2. diagnosing sequence optimization: call system's Minimal completeness test event set that previous step generates, adopt the correlation models method completion system fault diagnosis work that improves;
The analysis of described testability design result is to calculate the testability design objective of equipping under current Fault Diagnosis Strategy, described testability design objective comprises fault detect rate, Percent Isolated, fault ambiguity group quantity and size, mean time to detection, mean failure rate isolation time, fault isolation validity and the system qualification rate of resurveying, and utilizes the testability index definition standard of IEEE Std 1522-2004 standard to set up the Measurement criterion of described testability design objective.
2. a kind of electronic product testability analysis according to claim 1 and diagnosis decision system is characterized in that " fault that can not be detected " described in the step (2) information is exactly the failure message of complete " 0 " row in the described correlation matrix.
3. a kind of electronic product testability analysis according to claim 1 and diagnosis decision system is characterized in that the analytical approach of scale-of-two particle group optimizing described in the step (3) comprises the steps:
Step 1 constitutes the optimum results that a test event is selected, initialization population: initial position and the initial velocity of setting at random each particle with each particle;
Step 2 is calculated the corresponding equipment Test design result of each particle;
Step 3, for each particle, the result of the desired positions pbest that the comparison corresponding testability design result of current location and it live through, if better than pbest, renewal pbest is current location, otherwise does not upgrade pbest;
Step 4, to all particles in the population, select the best pbest in a body position as population desired positions gbest, if the population desired positions of current time is not worse than former desired positions, gbest with current time is updated among the former gbest result so, otherwise does not upgrade gbest;
Step 5 is upgraded all particle positions;
Step 6 if reach the termination condition of iterations maximum, then finishes, otherwise turns step 2.
A kind of electronic product testability analysis according to claim 1 with the diagnosis decision system, the implementation procedure that it is characterized in that the correlation models of improvement described in the step (3) method is as follows: the detection and the isolation weights that at first calculate each test point, judge the execution sequence of test point by the weights size, take the preferred result of test point as the basis, detect afterwards first and isolate, formulate Diagnostic Strategy with the sequencing that test point is selected.
CN 201010545014 2010-11-16 2010-11-16 Method for implementing testability analysis and diagnosis decision system for electronic products Expired - Fee Related CN101980225B (en)

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