CN101980103A - Power state management method and related computer system - Google Patents
Power state management method and related computer system Download PDFInfo
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Abstract
The invention discloses a power state management method and a related computer system. The power state management method is applied to a computer system; and the computer system comprises a central processing unit, a core logic unit electrically connected to the central processing unit, and peripheral equipment electrically connected to the core logic unit. The method comprises the following steps that: the core logic unit responds to a power state switching signal actively sent by the central processing unit in a first power state to execute a state checking program; and when the state checking program is successfully executed, the core logic unit sends an agreement signal to the central processing unit and a notification signal to the peripheral equipment so as to make the central processing unit enter a second power state, and the peripheral equipment is changed from a third power state to a fourth power state. The power state management method and the related computer system have quicker-response power-saving effect.
Description
Technical field
The present invention is a power supply status management method and a computer system, refers to have the computer system of CPU (central processing unit), core logic unit and peripherals especially and uses power supply status management method on it.
Background technology
Along with the new line of environmental consciousness and global energy gradually the phenomenon of shortage take place, the energy conservation characteristic of enhanced products how becomes the direction of product designer and manufacturer effort.And personal computer has been indispensable device indispensable in family, the office, make that stand-by time is more and more long, the unused time is less and less, and along with long unlatching and running, the electric power that consumes is considerable, therefore how at the state decline low power consumption of the performance that do not detract, also be that each manufacturer wants the target reached.
See also Fig. 1, it is a personal computer system a Core Feature block schematic diagram, wherein CPU (central processing unit) (hereinafter to be referred as CPU) 10 is by a Front Side Bus (FrontSide Bus, abbreviation FSB) 11 is connected to a north bridge chips 12, and north bridge chips 12 is electrically connected with South Bridge chip 13, image chip 14 and system storage 15 again, and then constitutes the core of computer system.And be can finish appropriate power management to reach purpose of energy saving, the power management standard of a kind of what is called " advanced configuration and power-management interface (AdvancedConfiguration and Power Interface; hereinafter to be referred as ACPI) " just is developed, and ACPI is at operating system (Operating System, abbreviation OS) realizes power management on the level, its power supply status with full machine system is called " Global State ", and be divided into G0, G1, G2,4 kinds of states such as G3, wherein G1 derives G1S1 especially again, G1S2, G1S3, G1S4, therefore strictness has 7 kinds of states, be G0, G1S1, G1S2, G1S3, G1S4, G2, G3 below is the Description of content of 7 kinds of states:
G0, the general work state of computing machine comprises just in executive operating system and various application programs etc.;
G1, also claim sleep (Sleeping) state, be divided into G1S1～G1S4 and stated G1 before, the difference mode of 4 kinds of states mainly is to decide with the speed that turns back to the G0 state, G1S1 turns back to the fastest of G0, and G1S2 takes second place, and G1S3 once more, G1S4 then returns the slowest, and the thin portion of S1～S4 is respectively in addition:
S1, the memory cache continued power in the CPU are keeping stored contents, but CPU stops execution command, and CPU and random access memory all continue to have power supply, and other devices then do not have special instructions, can enter power down mode or do not enter.
S2 also claims deep sleep (Deeper Sleep) state, and this moment, CPU can cut off the power supply.
S3, also claim to suspend to random access memory (Suspend To RAM is called for short STR) state, it is to random access memory part continued power, comprise frame buffer (Frame Buffer) and main system memory (Main Memory) etc., but remainder cuts off the power supply without exception.
S4 also claims hibernation (Hibernate) state, perhaps also claims Suspend To Disk (STD).S4 completely is written back to the data in the work in the hard disk, comprise picture frame impact damper, main system memory, hard disk memory buffer etc., complete then tester in power-down state is if compare S4 with S3, then S4 is than the S3 power saving, but that S3 enters and leave the speed of battery saving mode is fast than S4;
G2, G2 are very close with G3, and a continued power wakes up outside the device of effect for some tools, and remainder cuts off the power supply without exception, and tool wakes the device of effect up and comprises keyboard, mouse, network interface card, USB port etc.; And
G3 also claims mechanical shutdown (Mechanical Off), and implication is exactly that all cut off the power supply, do not keep any electric energy, in general only to move or the dismounting computing machine, or meet with power failure and UPS is not installed, otherwise can not enter this state mostly.
And above-mentioned 7 kinds of state G0, G1S1, G1S2, G1S3, G1S4, G2, the conversion of G3 mainly is to control by operating system, and start by CPU (central processing unit) 10, carrying out data by CPU (central processing unit) 10 utilizations to South Bridge chip 13 writes, and then startup power management states G0, G1S1, G1S2, G1S3, G1S4, G2, the conversion of G3, and when receiving after these data write circulation, South Bridge chip 13 just sends one and stops this CPU (central processing unit) 10 of clock signal (STPCLK), and after CPU (central processing unit) 10 receives that this stops clock signal (STPCLK), when if this CPU (central processing unit) 10 has been ready to enter battery saving mode, this CPU (central processing unit) 10 just can be sent the instruction of a suspension of licence (STPGNT) again and transmit by the commentaries on classics of north bridge chips 12 and notify this South Bridge chip 13, controls the conversion that whole computer system is finished power management states at last.
In addition, outside the power supply status control of whole computer system, ACPI also has at CPU itself and peripherals itself and carries out the control of power supply status, wherein CPU is distinguished into 4 kinds of states such as C0, C1, C2, C3, device also is divided into 4 kinds of states such as D0, D1, D2, D3, the wherein numeral little expression power consumption of healing of healing, otherwise then more power saving.For example, even total system is to be subjected to the power management control of operating system and to be in general work state (G0), CPU still can select to be in 4 kinds of states such as C0, C1, C2 or C3 according to the judgement of own hardware own, it when wherein being in C0 general normal operation state, be called time-out (Halt) state when being in C1, this moment, CPU can stop to carry out.And C2 also claims to stop clock pulse (Stop-Clock) state, promptly is only to keep power supply at the visible part of software among the CPU (mainly referring to working storage), and remainder then can be stopped power supply.Claim sleep (Sleep) state as for C3, at this moment CPU can not go to keep the data consistency between memory cache and system storage yet.And the D0～D3 of device aspect, D0 represents at full speed running, and D3 then not stops comprehensively, and D1, D2 then are power savings in various degree, and wherein D2 is than the D1 power saving, then can be designed voluntarily, be defined by the equipment research staff as for the power saving degree of reality.
But in traditional means, CPU is when carrying out the self-management of power supply statuss such as above-mentioned C0, C1, C2, C3, can't produce interactive with other the power supply status of peripherals, therefore cause the purpose that can't more effectively reach province's energy, and how to improve above-mentioned disappearance, become fundamental purpose of the present invention.
Summary of the invention
The invention provides a kind of power supply status management method, be applied in the computer system, the peripherals that this computer system comprises a CPU (central processing unit), is electrically connected on a core logic unit of this CPU (central processing unit) and is electrically connected on this core logic unit, this power supply status management method comprise the following steps: that the response of this core logic unit is in the power supply status switching signal that this CPU (central processing unit) of one first power supply status initiatively sends and carries out a status checking program; And when this status checking program is passed through, this core logic unit sends one and agrees that signal is to this CPU (central processing unit) and send a notification signal to this peripherals, with so that this CPU (central processing unit) enters a second source state, and make this peripherals enter one the 4th power supply status by one the 3rd power supply status.
The present invention also provides a kind of computer system with power supply status management function, and this computer system with power supply status management function comprises: a CPU (central processing unit), and it initiatively sends a power supply status switching signal in one first power supply status; One core logic unit, be electrically connected on this CPU (central processing unit), in order to receive and to respond this power supply status switching signal and carry out a status checking program, and when this status checking program by the time send one and agree a signal and a notification signal, wherein this approval signal is sent to this CPU (central processing unit) and makes it enter a second source state; And a peripherals, be electrically connected on this core logic unit, in order to receive this notification signal and make this peripherals enter one the 4th power supply status by one the 3rd power supply status.
According to above-mentioned conception, power supply status management method of the present invention and the computer system with power supply status management function, this CPU (central processing unit) that wherein is in this first power supply status selects whether initiatively to send this power supply status switching signal according to the busy degree of itself.
According to above-mentioned conception, power supply status management method of the present invention and the computer system with power supply status management function, wherein this status checking program comprises the following steps: to check the data processing state between this CPU (central processing unit) and this core logic unit.
According to above-mentioned conception, power supply status management method of the present invention and computer system with power supply status management function, whether the data processing state between this CPU (central processing unit) and this core logic unit of wherein checking: detecting has data to transmit action on the Front Side Bus between this core logic unit and this CPU (central processing unit) if can be, or whether a memory bus of detecting between this core logic unit and a system storage has data to transmit action.
According to above-mentioned conception, power supply status management method of the present invention and the computer system with power supply status management function wherein comprise the information of representing the 4th power supply status in this notification signal that this core logic unit sends.
According to above-mentioned conception, power supply status management method of the present invention and computer system with power supply status management function, wherein this core logic unit comprises a north bridge chips and a South Bridge chip, and this peripherals can be an image process unit that is electrically connected on this north bridge chips or an element that is electrically connected on this South Bridge chip.
According to above-mentioned conception, whether power supply status management method of the present invention and the computer system with power supply status management function, this status checking program that wherein this core logic unit carried out comprise the following steps: to detect has data to transmit action on the Front Side Bus between this north bridge chips and this CPU (central processing unit); Whether a memory bus of detecting between this north bridge chips and a system storage has data to transmit action; Whether an AGP bus of detecting between this north bridge chips and this image process unit has data to transmit action; And detect this South Bridge chip and this interelement USB (universal serial bus) and whether have data to transmit to move.
Power supply status management method of the present invention and relevant computer system have reacts power saving effect faster.
Description of drawings
Fig. 1, it is a personal computer system a Core Feature block schematic diagram.
Fig. 2, it is that the present invention is the function block schematic diagram that improves the conventional means computer system with power supply status management function that disappearance develops out.
Fig. 3, it is that the present invention improves the power supply status management method process flow diagram that the conventional means disappearance develops out.
Fig. 4, it is the computer system preferred embodiment synoptic diagram that can use the technology of the present invention means.
Embodiment
See also Fig. 2, it is that the present invention is the function block schematic diagram that improves the conventional means computer system with power supply status management function that disappearance develops out, this system mainly comprises CPU (central processing unit) 20, core logic unit 21 and peripherals 22, on it and moving an operating system (not shown).And when whole computer system is subjected to the control of electric power management mechanism in the operating system and is in general work state (G0), CPU (central processing unit) 20 also is to be in general normal operation state (C0) usually, but CPU (central processing unit) 20 still can be selected whether to switch to other 3 kinds of power supply statuss such as C1, C2 or C3 according to busy degree itself and carries out power saving.
Therefore, shown in the power supply status management method process flow diagram of Fig. 3, CPU (central processing unit) 20 in being in first power supply status determines according to busy degree itself will be when first power supply status switches to the second source state, it initiatively sends a power supply status switching signal and gives core logic unit 21 (step 30), and the core logic unit 21 that is electrically connected on this CPU (central processing unit) 20 is after receiving this power supply status switching signal, just can respond the triggering of this power supply status switching signal and carry out a status checking program, whether be fit to carry out the switching (step 31) of power supply status in order to the data processing state of checking 21 of CPU (central processing unit) 20 and core logic units, for example, core logic unit 21 can remove to detect the various bus that connects on the it (Front Side Bus 210 that joins with CPU (central processing unit) 20 for example, or the memory bus 211 of joining with system storage 23 etc.) whether there are data to transmit action (transaction) in, if there are data to transmit action, then core logic unit 21 will disagree with that CPU (central processing unit) 20 carries out its own power source state and switch (step 32).If no datat transmits action, think that promptly this status checking program passes through, just send an agreement signal and a notification signal (step 33) respectively to CPU (central processing unit) 20 and peripherals 22 this moment, this approval signal of wherein delivering to this CPU (central processing unit) 20 can make CPU (central processing unit) 20 switch the second source state (step 34) that enters, comprise the information of representing one the 4th power supply status and deliver in this notification signal of this peripherals 22, have corresponding relation between the 4th power supply status of this peripherals 22 and the second source state of CPU (central processing unit) 20, this type of corresponding pass can define by set up comparison list in core logic unit 21.Thus, this notification signal just can make this peripherals 22 enter the 4th power supply status (step 35) by the 3rd power supply status originally, for example switches to D1 from D0.Thus, when CPU (central processing unit) 20 when carrying out the self-management of power supply statuss such as above-mentioned C0, C1, C2, C3, core logic unit 21 of the present invention can be controlled the power supply status of other peripherals according to resulting power state information about CPU (central processing unit) 20, and then reaches better province's energy effect.
See also Fig. 4 again, it is the computer system preferred embodiment synoptic diagram that can use the technology of the present invention means, wherein mainly comprises CPU (central processing unit) 40, forms the north bridge chips 41 and the South Bridge chip 42 of core logic unit and the image process unit 43 and other elements 44 that can be considered peripherals.Same, when whole computer system was in general work state (G0), the CPU (central processing unit) 40 that is in first power supply status can determine whether will switch to the second source state from first power supply status according to the busy degree of itself.And when CPU (central processing unit) 40 decisions will be carried out the power supply status switching, it initiatively sends a power supply status switching signal to the South Bridge chip 42 in the core logic unit, and South Bridge chip 42 is after receiving this power supply status switching signal, just change the north bridge chips of passing in the core logic unit 41 again, north bridge chips 41 just responds the triggering of this power supply status switching signal and the executing state scrutiny program, in order to check whether the data processing state between CPU (central processing unit) 40 and core logic unit is fit to carry out the switching of power supply status, for example, north bridge chips 41 can be detected the various bus that is connected on the core logic unit (Front Side Bus 410 that joins of north bridge chips 41 and CPU (central processing unit) 40 for example, or north bridge chips 41 quickens connectivity port (AGP) bus 411 with the figure that image process unit 43 joins, or north bridge chips 41 and system storage 45 memory bus 412 of joining, or South Bridge chip 42 and other elements 44 USB (universal serial bus) 413 of joining etc.) whether there are data to transmit action (transaction) in, if there are data to transmit action, then north bridge chips 41 will disagree with that CPU (central processing unit) 40 carries out its own power source state and switch.If no datat transmits action, think that promptly this status checking program passes through, so just sending one to CPU (central processing unit) 40, north bridge chips 41 agrees signal.In addition, north bridge chips 41 can utilize the many signal pins of setting up 49 to send a notification signal to the image process unit 43 that can be considered peripherals respectively with other elements 44.This approval signal of wherein delivering to this CPU (central processing unit) 40 can make CPU (central processing unit) 40 switch the second source state (for example C1, C2, C3 etc.) that enters, this notification signal of delivering to image process unit 43 and other elements 44 then makes image process unit 43 and other elements 44 enter the 4th power supply status by the 3rd power supply status, for example switch to D1, or switch to D2 or the like by D1 from D0.
Be that example is elaborated with image process unit 43 again, see also following table 1.
Table 1
Table 1 is illustrated in the power saving means that can use under the different power supply statuss, for example the lock of drawing engine cuts out and shows that the lock of output terminal cuts out or the like to the clock pulse in loop to the clock pulse in loop to the lock of the clock pulse gate (clockgating) of loop (PLL), drawing engine in the image process unit 43, and this genus can use equally to other peripheral cell, so do not repeat them here.In addition, the notification signal that north bridge chips sent is except image process unit 43 and element 44 peripherals such as grade, and also may command north bridge chips itself and South Bridge chip carry out the switching of power supply status, can reach purpose of power saving equally.
Indulge the above, CPU (central processing unit) of the present invention is when carrying out the self-management of power supply statuss such as above-mentioned C0, C1, C2, C3, core logic unit 21 of the present invention can be controlled the power supply status of other peripherals according to resulting power state information about CPU (central processing unit) 20, react power saving effect faster in order to reach, and then effectively reach fundamental purpose of the present invention.The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
CPU: 10; Front Side Bus: 11; North bridge chips: 12; South Bridge chip: 13; Image chip: 14; System storage: 15; CPU: 20; Core logic unit: 21; Ancillary equipment: 22; Front Side Bus: 210; System storage: 23; Memory bus: 211; CPU: 40; North bridge chips: 41; South Bridge chip: 42; Image process unit: 43; Element: 44; Front Side Bus: 410; AGP bus: 411; Memory bus: 412 USBs: 413; Many signal pins: 49; System storage: 45.
Claims (12)
1. power supply status management method, it is characterized in that, be applied in the computer system, the peripherals that this computer system comprises a CPU (central processing unit), is electrically connected on a core logic unit of this CPU (central processing unit) and is electrically connected on this core logic unit, this power supply status management method comprises the following steps:
The response of this core logic unit is in the power supply status switching signal that this CPU (central processing unit) of one first power supply status initiatively sends and carries out a status checking program; And
When this status checking program is passed through, this core logic unit sends one and agrees that signal is to this CPU (central processing unit) and send a notification signal to this peripherals, with so that this CPU (central processing unit) enters a second source state, and make this peripherals enter one the 4th power supply status by one the 3rd power supply status.
2. power supply status management method according to claim 1 is characterized in that, this CPU (central processing unit) that is in this first power supply status selects whether initiatively to send this power supply status switching signal according to the busy degree of itself.
3. power supply status management method according to claim 1 is characterized in that, this status checking program comprises the following steps: to check the data processing state between this CPU (central processing unit) and this core logic unit.
4. power supply status management method according to claim 3, it is characterized in that, whether the data processing state between this CPU (central processing unit) and this core logic unit of checking: detecting has data to transmit action on the Front Side Bus between this core logic unit and this CPU (central processing unit) if being, or whether a memory bus of detecting between this core logic unit and a system storage has data to transmit action.
5. power supply status management method according to claim 1 is characterized in that, comprises the information of representing the 4th power supply status in this notification signal that this core logic unit sends.
6. the computer system with power supply status management function is characterized in that, this computer system with power supply status management function comprises:
One CPU (central processing unit), it initiatively sends a power supply status switching signal in one first power supply status;
One core logic unit, be electrically connected on this CPU (central processing unit), in order to receive and to respond this power supply status switching signal and carry out a status checking program, and when this status checking program by the time send one and agree a signal and a notification signal, wherein this approval signal is sent to this CPU (central processing unit) and makes it enter a second source state; And
One peripherals is electrically connected on this core logic unit, in order to receive this notification signal and make this peripherals enter one the 4th power supply status by one the 3rd power supply status.
7. the computer system with power supply status management function according to claim 6 is characterized in that, this CPU (central processing unit) that is in this first power supply status selects whether initiatively to send this power supply status switching signal according to the busy degree of itself.
8. the computer system with power supply status management function according to claim 6, it is characterized in that this status checking program that this core logic unit carried out comprises the following steps: to check the data processing state between this CPU (central processing unit) and this core logic unit.
9. the computer system with power supply status management function according to claim 8, it is characterized in that, whether the data processing state between this CPU (central processing unit) and this core logic unit of checking: detecting has data to transmit action on the Front Side Bus between this core logic unit and this CPU (central processing unit) if being, or whether a memory bus of detecting between this core logic unit and a system storage has data to transmit action.
10. the computer system with power supply status management function according to claim 6, it is characterized in that, this core logic unit sends this notification signal by many signal pins that are electrically connected to this peripherals, and comprises the information of representing the 4th power supply status in this notification signal.
11. the computer system with power supply status management function according to claim 6, it is characterized in that, this core logic unit comprises a north bridge chips and a South Bridge chip, and this peripherals is an element that is electrically connected on an image process unit of this north bridge chips or is electrically connected on this South Bridge chip.
12. the computer system with power supply status management function according to claim 11 is characterized in that this status checking program that this core logic unit carried out comprises the following steps:
Whether detect has data to transmit action on the Front Side Bus between this north bridge chips and this CPU (central processing unit);
Whether a memory bus of detecting between this north bridge chips and a system storage has data to transmit action;
Whether the figure acceleration connectivity port bus of detecting between this north bridge chips and this image process unit has data to transmit action; And
Whether detect this South Bridge chip has data to transmit action with this interelement USB (universal serial bus).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103123463A (en) * | 2011-11-21 | 2013-05-29 | 联想(北京)有限公司 | Method and device for controlling states of system |
| CN103135722A (en) * | 2011-11-23 | 2013-06-05 | 联想(北京)有限公司 | Electronic device and state control method for system in electronic device |
| WO2023082860A1 (en) * | 2021-11-10 | 2023-05-19 | Oppo广东移动通信有限公司 | Data processing chip, module, terminal and power management method |
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| CN1492299A (en) * | 2003-09-09 | 2004-04-28 | 威盛电子股份有限公司 | Computer system with power management and its method |
| CN1776569A (en) * | 2005-11-28 | 2006-05-24 | 威盛电子股份有限公司 | Power-saving mode adjusting method and its logic chip and computer system |
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| EP0770952B1 (en) * | 1995-10-26 | 2003-12-10 | International Business Machines Corporation | Power management in an information processing system |
| CN1492299A (en) * | 2003-09-09 | 2004-04-28 | 威盛电子股份有限公司 | Computer system with power management and its method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103123463A (en) * | 2011-11-21 | 2013-05-29 | 联想(北京)有限公司 | Method and device for controlling states of system |
| CN103123463B (en) * | 2011-11-21 | 2016-08-17 | 联想(北京)有限公司 | A kind of method and device of control system state |
| CN103135722A (en) * | 2011-11-23 | 2013-06-05 | 联想(北京)有限公司 | Electronic device and state control method for system in electronic device |
| CN103135722B (en) * | 2011-11-23 | 2016-07-06 | 联想(北京)有限公司 | A kind of electronic equipment and the method that system mode in described electronic equipment is controlled |
| WO2023082860A1 (en) * | 2021-11-10 | 2023-05-19 | Oppo广东移动通信有限公司 | Data processing chip, module, terminal and power management method |
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Application publication date: 20110223 |