CN101976550A - Liquid crystal panel and driving method thereof - Google Patents
Liquid crystal panel and driving method thereof Download PDFInfo
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- CN101976550A CN101976550A CN201010524373.0A CN201010524373A CN101976550A CN 101976550 A CN101976550 A CN 101976550A CN 201010524373 A CN201010524373 A CN 201010524373A CN 101976550 A CN101976550 A CN 101976550A
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Abstract
The invention relates to a liquid crystal panel and a driving method thereof, and the liquid crystal panel comprises a gate driver, a first scanning line, a second scanning line, a third scanning line, a connecting line and a control unit. The gate driver comprises the first scanning end; the first scanning line and the second scanning line are respectively coupled from a first switch to a fourth switch, and the other end of the first switch, the other end of a third switch and one end of the third scanning line are coupled with the first scanning end; the connecting line is coupled with the other end of a second switch and the other end of the fourth switch, and the connecting line outputs logic low voltage; and the control unit is used for respectively outputting a first control signal to a fourth control signal, thereby controlling the conduction and the closing of the first switch to the fourth switch. The liquid crystal panel and the driving method can lead the same scanning signal to sequentially drive the three scanning lines, further reduce the number of the gate drivers, reduce the working frequency of the gate driver, reduce the power consumption and increase the configuration space on the liquid crystal panel.
Description
Technical field
The present invention relates to a kind of liquid crystal panel and driving method thereof, and particularly relevant for a kind of number of gate drivers and the liquid crystal panel and driving method thereof of frequency of operation of reducing.
Background technology
In general, in the conventional art, the sweep signal output terminal of the sweep trace of display panel and gate drivers (gate driving IC) is man-to-man mode, and therefore, in case sweep trace increases, then the output terminal of gate driving IC also can increase thereupon.Under the trend that the resolution of LCD promotes day by day, the design of display panel then need be disposed more gate driving IC and be driven more multi-scan-line, just improves the cost of drive IC thus.
And LCD is to ask compact to cater to consumer's hobby, has therefore compressed the configuration space in the panel.With the aspect of panel designs, the lifting of resolution can cause the fan-out scope of sweep trace and data line to become big, and it diminishes the configurable space of panel; On the other hand, but allow the layout scope of each bars cabling diminish, it causes impedance to improve and influences quality of display pictures.Comprehensive above problem just makes panel designer to average out a little to reach optimal design from promoting resolution, reduction impedance and configuration space.
Summary of the invention
In view of this, the invention provides a kind of liquid crystal panel, it comprises gate drivers, first sweep trace, second sweep trace, three scan line, connecting line and control module.This gate drivers has the first scanning end; This first sweep trace is coupled between first switch and the second switch, and the other end of this first switch is coupled to this first scanning end; This second sweep trace is coupled between the 3rd switch and the 4th switch, and the other end of the 3rd switch is coupled to this first scanning end; One end of this three scan line is coupled to this first scanning end; This connecting line is coupled to the other end of this second switch, the 4th switch, this connecting line output logic low-voltage; This control module is exported first respectively and is controlled signal to the 4th control end that controls signal to described first switch to the, four switches, with the conducting of controlling described first switch to the, four switches with close.
According to described liquid crystal panel, this control module is integrated in this gate drivers.
According to described liquid crystal panel, when this first scanning end was in the high level time slot, described first switch cut out in all the other times in 0 to 1/3rd period conducting of described high level time slot; Described second switch was closed in 0 to 1/3rd period of described high level time slot, in all the other time conductings; Described the 3rd switch cuts out in all the other times in 1/3rd to 2/3rds periods conducting of described high level time slot; Described the 4th switch cut out in 1/3rd to 2/3rds periods of described high level time slot, in all the other time conductings.
According to described liquid crystal panel, this gate drivers also has the second scanning end and the 4th sweep trace, the 5th sweep trace, the 6th sweep trace; The 4th sweep trace is coupled between the 5th switch and the 6th switch, and the other end of the 5th switch is coupled to this second scanning end; The 5th sweep trace is coupled between minion pass and the octavo pass, and the other end that this minion is closed is coupled to this second scanning end; One end of the 6th sweep trace is coupled to this second scanning end; This connecting line is coupled to the other end of the 6th switch, this octavo pass.
According to described liquid crystal panel, described control module is exported first respectively and is controlled signal to the 4th and control signal to the control end that described the 5th switch to the octavo is closed, to control the conducting that described the 5th switch to the octavo closes and to close.
According to described liquid crystal panel, when this second scanning end was in the high level time slot, described the 5th switch cut out in all the other times in 0 to 1/3rd period conducting of described high level time slot; Described the 6th switch cut out in 0 to 1/3rd period of described high level time slot, in all the other time conductings; Described minion is closed 1/3rd to 2/3rds periods conducting at described high level time slot, closes in all the other times; Described octavo is closed and is closed in 1/3rd to 2/3rds periods of described high level time slot, in all the other time conductings.
According to an embodiment, the invention provides a kind of driving method of liquid crystal panel, this liquid crystal panel comprises gate drivers, first sweep trace, second sweep trace, three scan line, connecting line and control module, this gate drivers has the first scanning end, this first sweep trace is coupled between first switch and the second switch, the other end of this first switch is coupled to this first scanning end, this second sweep trace is coupled between the 3rd switch and the 4th switch, the other end of the 3rd switch is coupled to this first scanning end, one end of this three scan line is coupled to this first scanning end, this connecting line is coupled to this second switch, the other end of the 4th switch, this connecting line output logic low-voltage, it is characterized in that this liquid crystal panel drive method comprises: the output scanning signal is to this first switch, one end of the 3rd switch and this three scan line; The output logic low-voltage is to the other end of this second switch, the 4th switch; Output first controls signal to the 4th control end that controls signal to described first switch to the, four switches, with the conducting of controlling described first switch to the, four switches with close; Wherein, described first switch cuts out in all the other times in 0 to 1/3rd period conducting of the high level time slot of described sweep signal; Described second switch was closed in 0 to 1/3rd period of the high level time slot of described sweep signal, in all the other time conductings; Described the 3rd switch cuts out in all the other times in 1/3rd to 2/3rds periods conducting of the high level time slot of described sweep signal; Described the 4th switch cut out in 1/3rd to 2/3rds periods of the high level time slot of described sweep signal, in all the other time conductings.
According to described driving method, this first control signal and the 3rd control signal are clock pulse signal, the Cycle Length of this first control signal equals the Cycle Length of the 3rd control signal, and the pulse width of this first control signal equals the pulse width of the 3rd control signal.
According to described driving method, the activation time span of this sweep signal equals the Cycle Length of this first control signal.
According to described driving method, the activation time span of this sweep signal equals three times of pulse width of this first control signal.
Liquid crystal panel of the present invention and driving method are that three sweep traces are classified as one group, switch is set up in front end and rear end at wherein two sweep traces of three sweep traces, utilize unlatching that control signal decides the individual scanning line whether, and cooperate the sweep signal and the logic low-voltage that connecting line is exported of gate drivers, allow same sweep signal can drive in regular turn three sweep traces also can avoid sweep trace because of suspension joint produces uncertain problem phenomenon.The present invention not only can reduce the number of gate drivers, the required fan-out scope of sweep trace in the time of more can reducing panel layout.
Can be further understood by following description of drawings and embodiment detailed description in the advantages and spirit of the present invention.
Description of drawings
Fig. 1 is the synoptic diagram of the liquid crystal panel of the present invention's first embodiment.
Fig. 2 is the drive signal waveform figure of the liquid crystal panel of the present invention's first embodiment.
Fig. 3 is the driving method process flow diagram of the driving liquid crystal panel of the present invention's second embodiment.
Embodiment
Please refer to Fig. 1, Fig. 1 is the synoptic diagram of the liquid crystal panel of the present invention's first embodiment.According to first embodiment, liquid crystal panel 100 of the present invention comprises that a plurality of gate drivers (as gate drivers 110,112), multi-strip scanning line are (as L1～L6), a plurality of switch (as K1～K8), control module (not shown) and connecting line Vgl.In this embodiment, this gate drivers 110,112 has scanning end G1～Gn, (as L1～L3) is one group to per three of sweep trace, wherein any two sweep traces are coupled to the first scanning end G1 as the front end of the first sweep trace L1, the second sweep trace L2 via K switch 1, K2, the rear end of the first sweep trace L1, the second sweep trace L2 is coupled to connecting line Vgl via K switch 2, K4, the end of three scan line L3 is coupled to the first scanning end G1, this connecting line Vgl output logic low-voltage.Control module export respectively first control signal to the 4th control signal (as SK1～SK4) to as described in the control end of first switch to the, four switches, with the conducting of controlling described first switch to the, four switches with close, this control module is integrated in this gate drivers.In this embodiment, (as K1～K4) can be thin film transistor (TFT) to switch, also can be arranged at outside the liquid crystal panel 100, replaces with discrete component.Gate drivers 120,112 can adopt COG (Chip on glass) technology, gate drivers 110,112 is pressed on the liquid crystal panel 100, also can adopt COA (Chip on Array) technology, gate drivers 120,112 directly is integrated in the liquid crystal panel 100.
In this embodiment, (as L1～L3) is one group to per three of the sweep trace of liquid crystal panel 100, corresponding to one scan end (as the first scanning end G1), in other words, the gate drivers 110 that is present embodiment holds each sweep signal of output can drive three sweep traces respectively from each scanning, only need the gate drivers of original 1/3rd quantity can drive whole liquid crystal panel 100, in addition, if the frequency of operation of liquid crystal panel is 60Hz, then the driving frequency of the gate drivers of liquid crystal panel 100 only is 20Hz, significantly reduces the driving frequency of gate drivers.Next please refer to Fig. 1, control module is exported the first control signal SK1, the second control signal SK2, the 3rd control signal SK3 and the 4th control signal SK4, this first K switch 1 is controlled by this first control signal SK1, this second switch K2 is controlled by this second control signal SK2, the 3rd K switch 3 is controlled by the 3rd control signal SK3, and the 4th K switch 4 is controlled by the 4th control signal SK4.
Please see figures.1.and.2 simultaneously, Fig. 2 is the drive signal waveform figure of the liquid crystal panel of the present invention's first embodiment.110 of gate drivers scan end G1 via first and scan the first sweep trace L1, second sweep trace L2 and the three scan line L3, and adjust the time of first to three scan line L1～L3 unlatching via the activation time of first to fourth control signal SK1～SK4.Wherein, this first control signal SK1 and this second control signal SK2 are anti-phase, and the 3rd control signal SK3 and the 4th control signal SK4 are anti-phase.When this first scanning end G1 was in the high level time slot, described first K switch 1 was closed in all the other times in 0 to 1/3rd period conducting of described high level time slot; Described second switch K2 closed in 0 to 1/3rd period of described high level time slot, in all the other time conductings; Described the 3rd K switch 3 is closed in all the other times in 1/3rd to 2/3rds periods conducting of described high level time slot; Described the 4th K switch 4 was closed in 1/3rd to 2/3rds periods of described high level time slot, in all the other time conductings.In other words, as gate drivers 110 output scanning signal SG1 to the first scanning end G1, in T1 in the time period, the first control signal SK1 activation and the second control signal SK2 anergy, the 3rd control signal SK3 anergy and the 4th control signal SK4 activation, then the first sweep trace LI activation is to open corresponding pixel (as 11,12), the second sweep trace L2 then conducting to connecting line Vgl, connecting line Vgl can export a logic low-voltage to close pixel on the second sweep trace L2 (as 13,14), avoid the second sweep trace L2 suspension joint whereby, because three scan line L3 is coupled to the first scanning end G1, this moment, three scan line was in wrong towards state.As gate drivers 110 output scanning signal SG1 to the first scanning end G1, in T2 in the time period, the first control signal SK1 anergy and the second control signal SK2 activation, the 3rd control signal SK3 activation and the 4th control signal SK2 anergy, then the second sweep trace L2 activation is to open corresponding pixel (as 13,14), the first sweep trace L1 then conducting to connecting line Vgl, connecting line Vgl can export a logic low-voltage to close the pixel (as 11,12) on the first sweep trace L1, avoid the first sweep trace L1 suspension joint whereby, this moment, three scan line also was in wrong towards state.As gate drivers 110 output scanning signal SG1 to the first scanning end G1, in T3 in the time period, the first control signal SK1 and the 3rd control signal SK3 anergy, the second control signal SK2 and the 4th control signal SK4 activation, the first sweep trace LI then, the second sweep trace L2 conducting is to connecting line Vgl, connecting line Vgl can export a logic low-voltage to close the first sweep trace LI, pixel on the second sweep trace L2 is (as 11,12,13,14), avoid the first sweep trace LI whereby, the second sweep trace L2 suspension joint, this moment, three scan line L3 opened corresponding pixel (as 15,16).
In addition, the first control signal SK1 and the 3rd control signal SK3 are clock pulse signal, the Cycle Length of this first control signal SK1 equals the Cycle Length of the 3rd control signal SK3, the pulse width T 1 of this first control signal SK1 equals the pulse width T 2 of the 3rd control signal SK3, the activation time span T of this sweep signal SG1 equals the Cycle Length of this first control signal SK1, and the activation time span T of this sweep signal SG1 equals three times of pulse width T 1 of this first control signal SK1.It is three sweep traces of may command that present embodiment only need utilize the one scan signal, one-period at first three branch of sweep signal SG1 activation is opened a sweep trace (as LI), open next bar sweep trace (as L2) in the middle period of sweep signal SG1 activation, open the 3rd sweep trace (as L3) in the back three/one-period of sweep signal SG1 activation.In like manner, the circuit framework of the 4th to the 6th sweep trace L4～L6 and type of drive are then as above-mentioned first to three scan line L1～L3, main difference only is that the 4th to the 6th sweep trace L4～L6 is corresponding to the second scanning end G2, have in the present technique field and to know that usually the knowledgeable should know the remaining circuit structure and the start details of liquid crystal panel 100 after via exposure of the present invention easily by inference, do not add tired stating at this.
Please refer to Fig. 3, Fig. 3 is the driving method process flow diagram of the driving liquid crystal panel of the present invention's second embodiment.This embodiment provides a kind of driving method of liquid crystal panel, this liquid crystal panel comprises gate drivers, first sweep trace, second sweep trace, three scan line, connecting line and control module, this gate drivers has the first scanning end, this first sweep trace is coupled between first switch and the second switch, the other end of this first switch is coupled to this first scanning end, this second sweep trace is coupled between the 3rd switch and the 4th switch, the other end of the 3rd switch is coupled to this first scanning end, one end of this three scan line is coupled to this first scanning end, this connecting line is coupled to this second switch, the other end of the 4th switch, this connecting line output logic low-voltage, this liquid crystal panel drive method is described as follows: in same scan period, this driving method comprises step S110, and the output scanning signal is to this first switch, one end of the 3rd switch and this three scan line.At step S120, the output logic low-voltage is to the other end of this second switch, the 4th switch.At step S130, output first controls signal to the 4th control end that controls signal to described first switch to the, four switches, with the conducting of controlling described first switch to the, four switches with close.Wherein, described first switch cuts out in all the other times in 0 to 1/3rd period conducting of the high level time slot of described sweep signal; Described second switch was closed in 0 to 1/3rd period of the high level time slot of described sweep signal, in all the other time conductings; Described the 3rd switch cuts out in all the other times in 1/3rd to 2/3rds periods conducting of the high level time slot of described sweep signal; Described the 4th switch cut out in 1/3rd to 2/3rds periods of the high level time slot of described sweep signal, in all the other time conductings.This first control signal and this second control signal are anti-phase in this driving method, and the 3rd control signal and the 4th control signal are anti-phase.
According to described driving method, this first control signal and the 3rd control signal are clock pulse signal, the Cycle Length of this first control signal equals the Cycle Length of the 3rd control signal, and the pulse width of this first control signal equals the pulse width of the 3rd control signal.The activation time span of this sweep signal equals the Cycle Length of this first control signal.The activation time span of this sweep signal equals three times of pulse width of this first control signal.All the other details as for this driving method have been included among above-mentioned first embodiment, so do not add tired stating at this.
Liquid crystal panel of the present invention and driving method are that three sweep traces are classified as one group, switch is set up in front end and rear end at wherein any two sweep traces of three sweep traces, utilize unlatching that control signal decides the individual scanning line whether, and cooperate the sweep signal of gate drivers and the logic low-voltage that connecting line is exported, allow same sweep signal can drive three sweep traces in regular turn.Liquid crystal panel of the present invention and driving method make same sweep signal drive three sweep traces in regular turn, thereby reduce the number of gate drivers, reduce the frequency of operation of gate drivers, reduce power consumption, increase the configuration space on the liquid crystal panel.
According to the detailed description of above embodiment, hope can be known description feature of the present invention and spirit more, and is not to come the present invention is limited with above-mentioned disclosed embodiment.
Claims (10)
1. liquid crystal panel is characterized in that comprising:
Gate drivers has the first scanning end;
First sweep trace is coupled between first switch and the second switch, and the other end of this first switch is coupled to this first scanning end;
Second sweep trace is coupled between the 3rd switch and the 4th switch, and the other end of the 3rd switch is coupled to this first scanning end;
Three scan line, one end are coupled to this first scanning end;
Connecting line is coupled to the other end of this second switch, the 4th switch, this connecting line output logic low-voltage; And
Control module, this control module are exported first respectively and are controlled signal to the 4th control end that controls signal to described first switch to the, four switches, with the conducting of controlling described first switch to the, four switches with close.
2. liquid crystal panel according to claim 1 is characterized in that: this control module is integrated in this gate drivers.
3. liquid crystal panel according to claim 1 is characterized in that: when this first scanning end was in the high level time slot, described first switch cut out in all the other times in 0 to 1/3rd period conducting of described high level time slot; Described second switch was closed in 0 to 1/3rd period of described high level time slot, in all the other time conductings; Described the 3rd switch cuts out in all the other times in 1/3rd to 2/3rds periods conducting of described high level time slot; Described the 4th switch cut out in 1/3rd to 2/3rds periods of described high level time slot, in all the other time conductings.
4. liquid crystal panel according to claim 1 is characterized in that: this gate drivers also has the second scanning end and the 4th sweep trace, the 5th sweep trace, the 6th sweep trace; The 4th sweep trace is coupled between the 5th switch and the 6th switch, and the other end of the 5th switch is coupled to this second scanning end; The 5th sweep trace is coupled between minion pass and the octavo pass, and the other end that this minion is closed is coupled to this second scanning end; One end of the 6th sweep trace is coupled to this second scanning end; This connecting line is coupled to the other end of the 6th switch, this octavo pass.
5. liquid crystal panel according to claim 4, it is characterized in that: described control module is exported first respectively and is controlled signal to the 4th and control signal to the control end that described the 5th switch to the octavo is closed, to control the conducting that described the 5th switch to the octavo closes and to close.
6. liquid crystal panel according to claim 5 is characterized in that: when this second scanning end was in the high level time slot, described the 5th switch cut out in all the other times in 0 to 1/3rd period conducting of described high level time slot; Described the 6th switch cut out in 0 to 1/3rd period of described high level time slot, in all the other time conductings; Described minion is closed 1/3rd to 2/3rds periods conducting at described high level time slot, closes in all the other times; Described octavo is closed and is closed in 1/3rd to 2/3rds periods of described high level time slot, in all the other time conductings.
7. the driving method of a liquid crystal panel, this liquid crystal panel comprises gate drivers, first sweep trace, second sweep trace, three scan line, connecting line and control module, this gate drivers has the first scanning end, this first sweep trace is coupled between first switch and the second switch, the other end of this first switch is coupled to this first scanning end, this second sweep trace is coupled between the 3rd switch and the 4th switch, the other end of the 3rd switch is coupled to this first scanning end, one end of this three scan line is coupled to this first scanning end, this connecting line is coupled to this second switch, the other end of the 4th switch, this connecting line output logic low-voltage is characterized in that this liquid crystal panel drive method comprises:
The output scanning signal is to an end of this first switch, the 3rd switch and this three scan line;
The output logic low-voltage is to the other end of this second switch, the 4th switch;
Output first controls signal to the 4th control end that controls signal to described first switch to the, four switches, with the conducting of controlling described first switch to the, four switches with close;
Wherein, described first switch cuts out in all the other times in 0 to 1/3rd period conducting of the high level time slot of described sweep signal; Described second switch was closed in 0 to 1/3rd period of the high level time slot of described sweep signal, in all the other time conductings; Described the 3rd switch cuts out in all the other times in 1/3rd to 2/3rds periods conducting of the high level time slot of described sweep signal; Described the 4th switch cut out in 1/3rd to 2/3rds periods of the high level time slot of described sweep signal, in all the other time conductings.
8. driving method according to claim 7, it is characterized in that: this first control signal and the 3rd control signal are clock pulse signal, the Cycle Length of this first control signal equals the Cycle Length of the 3rd control signal, and the pulse width of this first control signal equals the pulse width of the 3rd control signal.
9. driving method according to claim 8 is characterized in that: the activation time span of this sweep signal equals the Cycle Length of this first control signal.
10. driving method according to claim 9 is characterized in that: the activation time span of this sweep signal equals three times of pulse width of this first control signal.
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| CN201010524373A CN101976550B (en) | 2010-10-13 | 2010-10-13 | Liquid crystal panel and driving method thereof |
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| CN201010524373A CN101976550B (en) | 2010-10-13 | 2010-10-13 | Liquid crystal panel and driving method thereof |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013120310A1 (en) * | 2012-02-16 | 2013-08-22 | 深圳市华星光电技术有限公司 | Gate drive circuit, drive method, and liquid crystal display system |
| WO2013155683A1 (en) * | 2012-04-16 | 2013-10-24 | 深圳市华星光电技术有限公司 | Liquid crystal display device and driving circuit thereof |
| CN103700354A (en) * | 2013-12-18 | 2014-04-02 | 合肥京东方光电科技有限公司 | Grid electrode driving circuit and display device |
| US20140104148A1 (en) * | 2012-10-11 | 2014-04-17 | Shenzhen China Star Potoelectronics Technology Co., Ltd. | Liquid Crystal Display and the Driving Circuit Thereof |
| CN103956131A (en) * | 2014-04-16 | 2014-07-30 | 京东方科技集团股份有限公司 | Pixel drive circuit, drive method, display panel and display device |
| CN104332147A (en) * | 2014-11-14 | 2015-02-04 | 深圳市华星光电技术有限公司 | Grid drive unit circuit, array substrate and display device |
| WO2016033830A1 (en) * | 2014-09-04 | 2016-03-10 | 深圳市华星光电技术有限公司 | Scanning driving circuit and display panel |
| CN107632474A (en) * | 2017-10-19 | 2018-01-26 | 京东方科技集团股份有限公司 | Display panel and display device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1635567A (en) * | 2004-06-02 | 2005-07-06 | 友达光电股份有限公司 | Flat display device, its drive method and multiplexer used therefor |
| KR20070109031A (en) * | 2006-05-09 | 2007-11-15 | 비오이 하이디스 테크놀로지 주식회사 | Liquid crystal dispaly |
| CN101261376A (en) * | 2007-03-09 | 2008-09-10 | 中华映管股份有限公司 | Display panel, display apparatus and drive method |
| CN101482676A (en) * | 2008-01-11 | 2009-07-15 | 中华映管股份有限公司 | Display panel and its driving method |
| CN101561597A (en) * | 2008-04-14 | 2009-10-21 | 中华映管股份有限公司 | Liquid crystal panel and driving method thereof |
| CN101685594A (en) * | 2008-09-25 | 2010-03-31 | 奇美电子股份有限公司 | Active matrix display panel and driving method thereof |
| CN101710481A (en) * | 2009-11-25 | 2010-05-19 | 福建华映显示科技有限公司 | Driving circuit and scanning method for liquid crystal display |
| JP2010113110A (en) * | 2008-11-06 | 2010-05-20 | Seiko Epson Corp | Signal-distribution circuit, electrooptical device, electronic apparatus, and method for driving signal-distribution circuit |
-
2010
- 2010-10-13 CN CN201010524373A patent/CN101976550B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1635567A (en) * | 2004-06-02 | 2005-07-06 | 友达光电股份有限公司 | Flat display device, its drive method and multiplexer used therefor |
| KR20070109031A (en) * | 2006-05-09 | 2007-11-15 | 비오이 하이디스 테크놀로지 주식회사 | Liquid crystal dispaly |
| CN101261376A (en) * | 2007-03-09 | 2008-09-10 | 中华映管股份有限公司 | Display panel, display apparatus and drive method |
| CN101482676A (en) * | 2008-01-11 | 2009-07-15 | 中华映管股份有限公司 | Display panel and its driving method |
| CN101561597A (en) * | 2008-04-14 | 2009-10-21 | 中华映管股份有限公司 | Liquid crystal panel and driving method thereof |
| CN101685594A (en) * | 2008-09-25 | 2010-03-31 | 奇美电子股份有限公司 | Active matrix display panel and driving method thereof |
| JP2010113110A (en) * | 2008-11-06 | 2010-05-20 | Seiko Epson Corp | Signal-distribution circuit, electrooptical device, electronic apparatus, and method for driving signal-distribution circuit |
| CN101710481A (en) * | 2009-11-25 | 2010-05-19 | 福建华映显示科技有限公司 | Driving circuit and scanning method for liquid crystal display |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013120310A1 (en) * | 2012-02-16 | 2013-08-22 | 深圳市华星光电技术有限公司 | Gate drive circuit, drive method, and liquid crystal display system |
| WO2013155683A1 (en) * | 2012-04-16 | 2013-10-24 | 深圳市华星光电技术有限公司 | Liquid crystal display device and driving circuit thereof |
| US20140104148A1 (en) * | 2012-10-11 | 2014-04-17 | Shenzhen China Star Potoelectronics Technology Co., Ltd. | Liquid Crystal Display and the Driving Circuit Thereof |
| CN103700354A (en) * | 2013-12-18 | 2014-04-02 | 合肥京东方光电科技有限公司 | Grid electrode driving circuit and display device |
| US10152939B2 (en) | 2013-12-18 | 2018-12-11 | Boe Technology Group Co., Ltd. | Gate driving circuit, method for driving the same, and display device |
| US20150302785A1 (en) * | 2014-04-16 | 2015-10-22 | Boe Technology Group Co, Ltd. | Pixel driving circuit, driving method, display panel, and display device |
| CN103956131B (en) * | 2014-04-16 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of pixel-driving circuit and driving method, display floater, display device |
| US9613555B2 (en) * | 2014-04-16 | 2017-04-04 | Boe Technology Group Co., Ltd. | Pixel driving circuit including signal splitting circuits, driving method, display panel, and display device |
| CN103956131A (en) * | 2014-04-16 | 2014-07-30 | 京东方科技集团股份有限公司 | Pixel drive circuit, drive method, display panel and display device |
| WO2016033830A1 (en) * | 2014-09-04 | 2016-03-10 | 深圳市华星光电技术有限公司 | Scanning driving circuit and display panel |
| CN104332147A (en) * | 2014-11-14 | 2015-02-04 | 深圳市华星光电技术有限公司 | Grid drive unit circuit, array substrate and display device |
| WO2016074297A1 (en) * | 2014-11-14 | 2016-05-19 | 深圳市华星光电技术有限公司 | Gate driving unit circuit, array substrate and display device |
| CN104332147B (en) * | 2014-11-14 | 2016-08-17 | 深圳市华星光电技术有限公司 | Gate drive unit circuit, array base palte and display device |
| US9685132B2 (en) | 2014-11-14 | 2017-06-20 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Gate driving circuit unit, array substrate, and display device |
| CN107632474A (en) * | 2017-10-19 | 2018-01-26 | 京东方科技集团股份有限公司 | Display panel and display device |
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