CN101976098A - NIOS-based embedded acquisition system - Google Patents

NIOS-based embedded acquisition system Download PDF

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CN101976098A
CN101976098A CN 201010502377 CN201010502377A CN101976098A CN 101976098 A CN101976098 A CN 101976098A CN 201010502377 CN201010502377 CN 201010502377 CN 201010502377 A CN201010502377 A CN 201010502377A CN 101976098 A CN101976098 A CN 101976098A
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nios
embedded
acquisition system
acquisition
fpga
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杨旻
葛承鑫
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Sichuan Tuopu Measurement & Control Technology Co Ltd
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Sichuan Tuopu Measurement & Control Technology Co Ltd
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Abstract

The invention discloses a NIOS-based embedded acquisition system, which relates to an intelligent acquisition system. The functions of the NIOS-based embedded acquisition system can be realized through the following steps: (1) based on a system on chip (SOC) technology and using the programmable characteristic of a field programmable gata array (FPGA), replacing a special embedded processor chip by embedding a NIOS embedded processor in the FPGA; (2) realizing the functions of acquisition control, data storage, LAN/USB/RS232 communication interfaces and peripheral control circuits in the same FPGA; (3) integrating the NIOS embedded processor with the acquisition control, the data storage, the LAN/USB/RS232 communication interfaces and the peripheral control circuits so as to form a final SOPC system; and (4) storing the acquired data by a large-capacity nonvolatile storage medium-NAND FLASH so as to realize fast data access. The system is an intelligent instrument which can improve the reliability of the acquisition system, reduce the power consumption and save the cost.

Description

Embedded acquisition system based on NIOS
Technical field
The present invention relates to the digital test fields of measurement, be specifically related to intelligent acquisition system.
Background technology
Along with development of semiconductor, more and more equipments possesses " intellectuality ", and present acquisition system has been the intelligent acquisition system that collector, instrument and processor combine together, has surpassed traditional automatic tester table and exclusive data acquisition system, therefore, obtained development at a high speed.And the realization means of embedded system this just " intelligence ".Embedded system refers generally to non-PC system, it be with common micromachine system and special-purpose large-scale, minicomputer system comparatively speaking.It is application-centered, based on computer technology, the dedicated computer system of application system to comprehensive requirements such as function, reliability, cost, volume and power consumptions can be reduced, be adapted to software and hardware, be the organic combination of hardware and software, and show with the form of hardware.
Along with of the development of embedded acquisition system to high-speed, low-power consumption, low-voltage and networking, system is more and more higher to the requirement of circuit, simultaneously, because the raising of IC design and craft technical merit, the integrated circuit scale is increasing, and complexity is more and more higher, and total system can be integrated on the chip, thus, the notion of SOC (System On Chip SOC (system on a chip)) arises.
Adopt the primary study direction that becomes current domestic and international each acquisition system research institute of the embedded acquisition system of SOC (System On Chip SOC (system on a chip)) technology.
Summary of the invention
The purpose of this invention is to provide a kind of embedded acquisition system based on NIOS.The present invention be a kind ofly can improve the acquisition system reliability, reduce power consumption, cost-effective Artificial Intelligence Instrument, the present invention is the sophisticated equipment of successful Application SOC technology in the acquisition system field.
Embedded acquisition system based on NIOS of the present invention, realize the function of embedded data acquisition system by following steps:
(1) based on the SOC technology, utilize the programmable features of FPGA, adopt an embedded NIOS flush bonding processor instead of dedicated flush bonding processor chip in FPGA;
(2) in a slice FPGA, realize the function of acquisition controlling, data storage, LAN/USB/RS232 communication interface and peripheral control circuit;
(3) the NIOS flush bonding processor is incorporated into acquisition controlling, data storage, LAN/USB/RS232 communication interface and peripheral control circuit, become an independence, special-purpose, programmable embedded acquisition system chip, form final SOPC system;
(4) employing high capacity non-volatile memory medium---NAND FLASH carries out the storage of image data, realizes fast data access.
Technical scheme main points of the present invention: the present invention is based on the SOC technology, utilize the programmable features of FPGA, employing is an embedded flush bonding processor NIOS in FPGA, simultaneously, this flush bonding processor is incorporated into acquisition controlling, data storage, LAN/USB/RS232 communication interface and peripheral control circuit, become an independence, special-purpose, programmable embedded acquisition system chip, form final SOPC system.Compare with the embedded acquisition system that a plurality of control chips of traditional employing are formed, all there is bigger advantage in this system at aspects such as cost, power consumption, volume, reliabilities.
Advanced at present intelligent data acquisition equipment has generally all adopted the flush bonding processor technology, the acquisition system design proposal that promptly adopts flush bonding processor to combine with traditional collector, data storage management technology.Traditional collector is finished functions such as data acquisition, data storage, special-purpose flush bonding processor is as the control core of acquisition system, finish the multiple-tasks such as control, data analysis and data transmission to collector, system has certain detection certainly, corrects ability certainly, is convenient to safeguard.Flush bonding processor is the key link of design, is " brain " of total system, has often determined what kind of function is system can realize, and the reliability and stability of total system.
The acquisition system that this framework of a large amount of employings has been arranged has in the market all obtained using widely in the every field of data acquisition, and its technology maturity and reliability have obtained the checking in market.But, the development has no limits for technology, continuous development along with chip technology, the particularly proposition of SOC (SystemOn Chip SOC (system on a chip)), the flush bonding processor of special use and traditional acquisition control system are integrated in the chip, no longer have been fantasies thereby further reduce hopes such as equipment volume, saving cost, reduction power consumption, raising system reliability.
The present invention is based on the embedded acquisition system of NIOS, total system only can realize the complex work that legacy equipment needs a plurality of special integrated circuits to finish with a slice FPGA, the embedded NIOS flush bonding processor of this FPGA, substitute all functions of flush bonding processor in traditional embedded acquisition system, in addition, utilize the programmable features of FPGA, it can also realize many peripheral functions such as acquisition controlling, data memory interface, communication interface, thereby realizes SOPC (System On a Programmable Chip) system.Adopt the product of this technical design, excellent performance is all arranged at aspects such as equipment volume, cost, power consumption, reliabilities, can predict, this by adopting the SOPC technology to realize that the product of high-performance, high integration, subminiaturization, high reliability and programmability will be embedded from now on acquisition system development in future direction.
SOC, combines closely until the design of device treatment mechanism, model algorithm, chip structure, each level circuit from the angle of total system, finishes the function of total system on single (or a few) chip.The design of SOC is the main description means of systemic-function and structure based on IP kernel with different levels hardware description language, carries out by means of the eda tool that with the computing machine is platform.Studies show that, compare,, thereby can under same technology condition, realize more high performance system index because the SOC design can be comprehensively and the various situations of the total system of giving overall consideration to the system that IC forms.The SOC technology has also promoted the development of software and hardware coordinate design and Computer System Design robotization greatly.
SOPC be ALTERA company put forward a kind of flexibly, SOC solution efficiently.It is integrated into the functional module that system designs such as processor, storer, I/O mouth, LVDS, CDR need on the PLD device, is configured to a programmable SOC (system on a chip).It is a programmable system, has the design flexible mode, can reduce, extendible, scalable and possess the function of software and hardware at system programmable.In the programming device, also have the high-speed RAM resource, utilize IP Core resource abundant on the market, the user can constitute various system.ALTERA puts into PLD with the soft nuclear of flush bonding processor, this soft nuclear is exactly NIOS, it only accounts for chip internal a part of logical block seldom, cost is very low, large-scale PLD has abundant logical resource, except the resource that the NIOS embedded system is used, also have enough resources to be used to realize other additional logic, the formation integrated level is higher, the SOC of more complex functions.
The Nios flush bonding processor has 32 instruction set, and each cycle can be carried out an instruction, and the highest execution speed can reach 200MIPS.The Nios processor also has some configurable perimeter interfaces, and they comprise SRAM and ROM on UART, parallel I/O, Timer, SPI, the sheet, control with the interface of outer SRAM of sheet and FLASH.The NIOS processor has the sophisticated software development kit, comprises compiler, Integrated Development Environment, JTAG debugger, real time operating system (RTOS) and ICP/IP protocol stack.SOPC Builder system development tool during the enough Altera Quartus II of deviser's energy develop software is created special-purpose processor system at an easy rate, and can add the quantity of Nios II processor core according to the demand of system.Use Nios II SDK (Software Development Kit) can be Nios II system constructing software, promptly one-touch automatic generation is applicable to the special-purpose C/C++ running environment of system hardware.Nios II Integrated Development Environment (IDE) provides many software templates, has simplified the project setting.In addition, Nios II development kit comprises two third party's real time operating systems (RTOS)---MicroC/OS-II (Micrium), NucleusPlus (ATI/Mentor) and the ICP/IP protocol stack that uses for network application.
The embedded acquisition system based on NIOS that adopts this SOPC technology to realize, the deviser can select to satisfy the preferred plan of performance and cost, and can not influence existing software input according to the variation change CPU of system requirements.
In addition, characteristics of the present invention and advance also are embodied in the following aspects:
The vast capacity storage
Novel intelligent acquisition system needs long-time continual acquisition capacity, and this just requires equipment to have jumbo storage space, and the data of storage do not lose after power down yet, to realize the reproduction to historical data.The Nand-flash storer be the flash internal memory-kind, it is inner to adopt non-linear macroelement pattern, for the realization of solid-state large-capacity internal memory provides cheap effective solution.The Nand-flash storer has advantages such as capacity is big, and writing speed is fast, is applicable to the storage of mass data, thereby has in the industry cycle obtained application more and more widely, at present, has been widely used in such as in the products such as USB flash disk, SD card.The embedded acquisition system based on NIOS of my company design adopts Nand-flash as storage medium, the maximum 8GB that supports of its capacity, and maximum 2048 sections of hop count support all substantially exceeds other like products from indexs such as the memory capacity of single hop and total hop counts.
Networking design
LAN is the most frequently used networking mode.Ethernet uses twisted-pair feeder as transmission medium.Do not having under the situation of relaying, can cover 200 meters scope farthest.The most universal ethernet type message transmission rate is 100Mb/s, and the standard of renewal is then supported the speed of 1000Mb/s and 10000Mb/s.These characteristics of LAN make it all be in a leading position at aspects such as connection speed, connection distance and networking modes.
The novel intelligent acquisition system of the present invention's development, when supporting USB, RS232, RS485 interface, also support LAN interface, making it is not only a collecting device that can only closely be connected with PC, by present widely used Ethernet, can be connected to any PC terminal in the network.And then, by INTERNET, can effectively control it at any old place in the world, the real thing of accomplishing joins the world.The proposition of Internet of Things also makes the novel intelligent acquisition system of supporting LAN interface in future development, and more wide application prospect is arranged.
Description of drawings
Fig. 1 is a system architecture synoptic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing and with illustrated embodiments the present invention is done detailed explanation.
Consult Fig. 1,, realize the function of embedded data acquisition system by following steps based on the embedded acquisition system of NIOS:
(1) based on the SOC technology, utilize the programmable features of FPGA, adopt an embedded NIOS flush bonding processor instead of dedicated flush bonding processor chip in FPGA;
(2) in a slice FPGA, realize the function of acquisition controlling, data storage, LAN/USB/RS232 communication interface and peripheral control circuit;
(3) the NIOS flush bonding processor is incorporated into acquisition controlling, data storage, LAN/USB/RS232 communication interface and peripheral control circuit, become an independence, special-purpose, programmable embedded acquisition system chip, form final SOPC system;
(4) employing high capacity non-volatile memory medium---NAND FLASH carries out the storage of image data, realizes fast data access.
In the described SOC technology of (one) step, be in design process, from the angle of total system, treatment mechanism, model algorithm, chip structure, each level circuit, design until device is combined closely, and finishes the function of total system at least on single or two chips.
Utilize the programmable features of FPGA in (one) step, be configured to a programmable SOC (system on a chip), this system is a programmable system, has the design flexible mode, can reduce, extendible, scalable and possess the function of software and hardware at system programmable.
Data storage adopts novel nonvolatile memory as data storage medium in (two) step, possesses the high-speed high capacity data storage capacities.
The integrated multiple communication interface of the present invention satisfies the demand that main frame connects under the various conditions.
Quartus II is the efficient tool of carrying out the SOPC system design, uses it can design whole application system fast.It provides the ability of utilizing PLD to carry out 1,000,000 gate logics designs, wherein integrated be used on the Altera device, designing, comprehensively, all instruments of compiling, checking.
We use the SOPC Builder instrument that is integrated among the QuartusII to dispose generation " SOC (system on a chip) ".SOPC Builder is the definition and the customization instrument of powerful " on a sheet " system based on graphical interfaces, and it can finish the SOPC design of customization at short notice.We select IP module, memories, peripheral interface and processor according to the needs of using from SOPC Builder storehouse, and configuration generates the SOPC system of a high integration.According to needs of the present invention, we choose following modules and form SOC (system on a chip):
Nios?32-bit?CPU、EPCS?CONTROLLER、LANINTERFACE、CommunicationUART、debugging?UART、DDR2CONTROLLER、Timer、Button?PIO、User?PIO、LED?PIO、DMA、SPI、Avalon?Tri-State?Bridge。In addition, the IP kernel that also needs to design voluntarily has: AD acquisition control module, NAND FLASH controller.
SOPC Builder produces the work that some essential arbitrated logics come above each parts in the coherent system automatically simultaneously, and we are made as 80Mhz with the frequency of operation of system.
After having customized the hardware of " on the sheet " system, SOPC Builder also provides a software development environment---NIOS IDE for we write the software code of controlling these " on the sheet " hardware, and this software environment comprises the driving of language header file, peripheral interface and the kernel of real time operating system.This environment is very easy to the exploitation of software.
Each Nios II program comprises an application project, optionally storehouse engineering and a plate support package engineering.The form of carrying out with being connected (Executable And Linked Format File---file .elf) that becomes an energy in Nios II processing, to move Nios II program compilation.
Nios II C/C++ application project comprises the set of the source code of forming an executable .elf file.The feature of a typical application is that a source file comprises main ()---principal function.Application project comprises the source code of invoked function among libraries and the BSP.
The storehouse engineering is the set of the source code in the library file (.a).Usually comprise reusable, general function in the library file, these functions can be shared by a plurality of application project.Such as, mathematical function library.The storehouse engineering does not have main () function.
Nios II BSP engineering is the special storehouse that comprises the particular system support code.BSP provides the software runtime environment of customization for the processor of SOPCBuilder system.Nios II EDS provides corresponding instrument can revise the behavior of setting with control BSP.Use " system library " to refer to BSP in Nios II IDE and the Nios II IDE development process document.
BSP comprises following ingredient:
Hardware abstraction layer (HAL), Newlib C java standard library, device drives, optional software package, optional real time operating system (RTOS).HAL provides a non-thread, the C/C++ running environment of class UNIX.HAL can provide general I/O equipment, allows the function programming of user newlib C java standard library to visit hardware, as printf ().Use HAL can minimize (or elimination) and control peripheral hardware and and peripheral communication by the register of direct access hardware.Newlib is the application for embedded system, and the realization of increasing income that the java standard library of C is simplified.Comprise the set of the function that some are commonly used, as printf (), malloc () and open () etc.Hardware device of each device drives management.HAL is that in the SOPC Builder system each needs driver of device instanceization of driver.In Nios II software development environment, device drives has following attribute:
A device drives is to be associated with a specific SOPC Builder equipment.Driver has some the compiling that can influence driver is set, and these settings are included in being provided with of BSP.Software package is that the user can select to join in the BSP engineering, and the source code of additional function is provided.Such as the Nich that uses among the present invention
Figure BSA00000297387200071
The ICP/IP protocol stack.Nios II IDE and Nios II IDE design cycle document use " component software " to refer to software package.In Nios II software development environment, software package does not have related with specific hardware.Software be surrounded by some be provided with can influence its compiling, these settings. be included in being provided with of BSP.In Nios II software development environment, software package is different with the storehouse engineering, and software package is the part of BSP engineering, is not an independent storehouse engineering.
Nios II EDS comprises third-party u C/OS-II, based on HAL, has realized a simple real time operating system, and in the present invention, we select to join among the BSP.Other operating system can obtain from third-party software vendor if desired.
System realizes
Below we provide some specific implementations of native system.We analyze separated into two parts and introduce, and these two parts are respectively: 1. the acquisition control module of using VHDL to write, be used to control the collection sequential of ADC, and simultaneously, this module is communicated by letter with the NIOS flush bonding processor by the AVALON bus interface.In gatherer process, by dma mode image data directly is transferred to internal memory, be then written among the NAND FLASH.2. the SPI interface that uses c language compilation program to dispose by SOPC Builder reads the parameter among the E2PROM.
1. acquisition control module
The acquisition control module of using VHDL to write is used to produce the ADC timing control signal.Simultaneously, deposit the image data that gets access in FIFO.By the AVALON bus interface of inside modules, flush bonding processor can read the image data among the FIFO.In the actual acquisition process, in order to reduce the software overhead of NIOS, improve data rate, adopt dma mode that the image data among the acquisition control module FIFO is directly sent to internal memory, and then dump among the NAND FLASH.
2.SPI the programming of interface
The various parameters of acquisition system all leave among the outside EEPROM, and Nios is by SPI interface accessing EEPROM.We put the SPI interface by the SOPC Builder among the Quartus II for the Nios caryogamy.SPI is a kind of bus interface of simple, standard, is widely used in the embedded system.By SOPCBuilder configuration SPI interface, we can be made as it main equipment also can be made as slave unit, and in our application, it is set to slave unit.
Above embodiment is more preferably embodiment a kind of of the present invention, the common variation that those skilled in the art carry out in the technical program scope and replace and should be included in protection scope of the present invention.

Claims (4)

1. based on the embedded acquisition system of NIOS, it is characterized in that, realize the function of embedded data acquisition system by following steps:
(1) based on the SOC technology, utilize the programmable features of FPGA, adopt an embedded NIOS flush bonding processor instead of dedicated flush bonding processor chip in FPGA;
(2) in a slice FPGA, realize the function of acquisition controlling, data storage, LAN/USB/RS232 communication interface and peripheral control circuit;
(3) the NIOS flush bonding processor is incorporated into acquisition controlling, data storage, LAN/USB/RS232 communication interface and peripheral control circuit, become an independence, special-purpose, programmable embedded acquisition system chip, form final SOPC system;
(4) employing high capacity non-volatile memory medium---NAND FLASH carries out the storage of image data, realizes fast data access.
2. the embedded acquisition system based on NIOS as claimed in claim 1, it is characterized in that, in the described SOC technology of (one) step, be in design process, angle from total system, treatment mechanism, model algorithm, chip structure, each level circuit, combine closely until the design of device, on single or two chips, finish the function of total system at least.
3. the embedded acquisition system based on NIOS as claimed in claim 1 is characterized in that, utilizes the programmable features of FPGA in (one) step, is configured to a programmable SOC (system on a chip).
4. the embedded acquisition system based on NIOS as claimed in claim 1 is characterized in that data storage adopts novel nonvolatile memory as data storage medium in (two) step.
CN 201010502377 2010-10-11 2010-10-11 NIOS-based embedded acquisition system Pending CN101976098A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103383710A (en) * 2013-07-05 2013-11-06 燕山大学 Circuit board based on SOPC analog brain waves and method for constructing brain dynamic model
CN103592912A (en) * 2013-10-30 2014-02-19 北京宇航系统工程研究所 Distributed power measurement and control system applied to heavy carrier rocket
CN105468569A (en) * 2015-11-17 2016-04-06 上海新储集成电路有限公司 Embedded system with high-capacity nonvolatile memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499134A (en) * 2009-03-13 2009-08-05 重庆大学 Iris recognition method and system based on field programmable gate array
CN101504716A (en) * 2009-03-13 2009-08-12 重庆大学 QR two-dimension bar code recognition method and system based on field programmable gate array
CN101795019A (en) * 2010-01-19 2010-08-04 东南大学 Soft core based merging unit of photoelectric current transformers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499134A (en) * 2009-03-13 2009-08-05 重庆大学 Iris recognition method and system based on field programmable gate array
CN101504716A (en) * 2009-03-13 2009-08-12 重庆大学 QR two-dimension bar code recognition method and system based on field programmable gate array
CN101795019A (en) * 2010-01-19 2010-08-04 东南大学 Soft core based merging unit of photoelectric current transformers

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103383710A (en) * 2013-07-05 2013-11-06 燕山大学 Circuit board based on SOPC analog brain waves and method for constructing brain dynamic model
CN103592912A (en) * 2013-10-30 2014-02-19 北京宇航系统工程研究所 Distributed power measurement and control system applied to heavy carrier rocket
CN103592912B (en) * 2013-10-30 2015-10-21 北京宇航系统工程研究所 A kind of distributed-power TT&C system being applied to heavy launcher
CN105468569A (en) * 2015-11-17 2016-04-06 上海新储集成电路有限公司 Embedded system with high-capacity nonvolatile memory

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Application publication date: 20110216