CN101969331B - Digital frequency selecting method for solving resource consumption - Google Patents
Digital frequency selecting method for solving resource consumption Download PDFInfo
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Abstract
The invention discloses a digital frequency selecting method for solving resource consumption. The method comprises the following steps of: connecting an FPGA digital frequency selection sub-module in a downlink formed by a downlink lower frequency converter, a downlink ADC, a downlink DAC and a downlink upper frequency converter and an uplink formed by an uplink lower frequency converter, an uplink ADC, an uplink DAC and an uplink upper frequency converter; performing digital multi-frequency selection processing on AD output of the downlink and the uplink; returning a processing result as DA input to the downlink and the uplink; performing down-sampling, filtering and up-sampling on digital signals in sequence in an internal processing process of the FPGA digital frequency selection sub-module. By adopting the digital frequency selection mode based on multi clock domains, the number of channels sharing the same group of filters is over the down-sampling rate R under determined down sampling rate R, so the occupied resource required by the digital frequency selection module can be effectively reduced, and the cost for a frequency selector can be reduced.
Description
Technical field
The present invention relates to the frequency-selecting method in a kind of communication technical field, particularly relate to a kind of digital frequency-selecting method that solves resource consumption.
Background technology
Frequency-selecting method commonly used be the simulation frequency-selecting substantially in the present communication system of China, and the simulation frequency-selecting mainly has following problem: the one,, debugging work is difficult to, productibility is poor, the engineering debug inconvenience; The 2nd,, the isolation difficulty of up-downgoing is done, easily self-excitation; The 3rd,, the GSM repeater of simulation frequency-selecting is difficult to satisfy European standard; The 4th,, can not accomplish time slot A GC (each time slot being carried out a kind of technology of automatic gain control), the covering efficient of the repeater of GSM is reduced greatly.
At present, the published patent No. is the multichannel frequency-selecting digital signal processing method that the patent document of ZL200920012632.4 has been introduced a kind of GSM numeral multiselect frequency repeater and adopted, and it comprises: up link, down link, first duplexer module, the second duplexer module and control unit; Described up link comprises up low noise amplification module, up the first analog frequency mixing module, up analog-to-digital conversion module, upstream digital channel frequency-selecting module, up D/A converter module, up the second analog frequency mixing module and up power amplifier module; Described down link comprises descending low noise amplification module, descending the first analog frequency mixing module, descending analog-to-digital conversion module, descending digital channel frequency-selecting module, descending D/A converter module, descending the second analog frequency mixing module and descending power amplifier module; The port of described up analog-to-digital conversion module, upstream digital channel frequency-selecting module, up D/A converter module, descending analog-to-digital conversion module, descending digital channel frequency-selecting module and descending D/A converter module connects the port of control unit.Donor antenna receives the base station down signal, after the first duplexer module send descending low noise amplification module to amplify, be down-converted to intermediate-freuqncy signal by descending the first analog frequency mixing module, after descending analog-to-digital conversion module conversion, enter descending digital channel frequency-selecting module again and finish the frequency-selecting function, the frequency-selecting signal is after descending D/A converter module is changed, upconvert to radiofrequency signal through descending the second analog frequency mixing module again, after descending power amplifier module amplifies, be sent to cable and distribution system by the second duplexer module, by retransmitting antenna to area of coverage radiation.Retransmitting antenna receiving mobile upward signal, after the second duplexer module is served upward signal capable low noise amplification module amplification, be down-converted to analog if signal by up the first analog frequency mixing module, after up analog-to-digital conversion module conversion, enter upstream digital channel frequency-selecting module again and finish the digital frequency-selecting function, the frequency-selecting signal is after up D/A converter module is changed, upconvert to radiofrequency signal through up the second analog frequency mixing module again, after amplifying, up power amplifier module is sent to donor antenna by the first duplexer module, send to the base station through donor antenna again, the channel of intermediate frequency is selected, filtering need to realize with software.
In the digital frequency-selecting repeater, resource consumption and system delay are two large core index.Repeater General Requirements time-delay must be less than 10us.Based on the digital frequency-selecting of multi-sampling rate filter bank technology, the size of its time-delay is mainly determined by the group time-delay of FIR filter.In general, sample rate reduces manyly, and under the equal Out-of-band rejection index, the required resource of digital frequency-selecting is fewer, but corresponding time-delay is also larger.For the digital frequency-selecting device of repeater, reduce sampling frequency R mainly affects resource consumption from two aspects: at first, namely reach equal Out-of-band rejection with less FIR number of taps; Secondly, one group of filter of a plurality of channel sharings.And for the FIR filter of determining the tap amount, its group time-delay is determined by the sample rate of sampling point, in other words, is determined by reduce sampling frequency R.In existing method, under the reduce sampling frequency R that determines, the channel quantity that shares one group of filter mostly is half of reduce sampling frequency R most.
Summary of the invention
The object of the invention is to overcome the deficiency of prior art, a kind of digital frequency-selecting method that solves resource consumption is provided, it is the digital frequency-selecting mode that adopts based on multi-clock zone, so that under the reduce sampling frequency R that determines, the channel quantity that shares one group of filter surpasses reduce sampling frequency R, and only be subject to the maximum clock that system can reach, can satisfy with lower cost the technical requirement of repeater.
The technical solution adopted for the present invention to solve the technical problems is: a kind of digital frequency-selecting method that solves resource consumption, be FPGA digital frequency-selecting submodule is connected to the down link that is made of descending low-converter, descending ADC, descending DAC, descending upconverter and the up link that consisted of by up low-converter, up ADC, up DAC, up upconverter in, digital multiselect is carried out in the AD output of down link and up link frequently process, and input returns to down link and up link as DA with result;
The up low noise module output signal of up link enters up low-converter and is transformed to intermediate-freuqncy signal, intermediate-freuqncy signal enters up ADC and is with the logical sampling of owing, data after the sampling enter FPGA digital frequency-selecting submodule and carry out digital multiselect and frequently process, process rear the input as DA and be sent to up DAC generation intermediate-freuqncy signal, intermediate-freuqncy signal is exported after up upconverter is transformed to radiofrequency signal;
The descending low noise module output signal of down link enters descending low-converter and is transformed to intermediate-freuqncy signal, intermediate-freuqncy signal enters descending ADC and is with the logical sampling of owing, data after the sampling enter FPGA digital frequency-selecting submodule and carry out digital multiselect and frequently process, process rear the input as DA and be sent to descending DAC generation intermediate-freuqncy signal, intermediate-freuqncy signal is exported after descending upconverter is transformed to radiofrequency signal;
FPGA digital frequency-selecting submodule is in internal processes, sequentially, adopt three clock zones digital signal to be carried out the processing of down-sampled, filtering and liter sampling: in the first clock zone, to be with frequency mixer, first integrator group and decimator signal to be carried out sequential processes; In the second clock territory, be to use mixer, the first differentiator group, the FIR filter, the second differentiator group and splitter carry out sequential processes to signal; In the 3rd clock zone, be with rising sampler, second integral device group and complex mixer signal to be carried out sequential processes.
Described FPGA digital frequency-selecting submodule for predefined number of channel K, reduce sampling frequency R and multiple e, is that the output with 4K decimator is input in the mixer in internal processes, by mixer 4K road signal is merged into one road signal;
Wherein,
When 4K=R, mixer adopts identical work clock with decimator, and wherein mixer has R input;
When 4K＜R, if mixer adopts identical work clock with decimator, then adopt the mixer that R input arranged, wherein input zero padding for R-4K; If the clock of mixer is e times of decimator, then employing has the eR (eR＞=4K) mixer of individual input, wherein eR-4K input zero padding;
When 4K＞R, the clock that makes mixer be decimator e doubly so that eR＞=4K; At this moment, adopt the mixer that eR input arranged, wherein eR-4K input zero padding.
Described FPGA digital frequency-selecting submodule is in internal processes, wherein: frequency mixer, first integrator group are operated under the identical clock; Mixer, the first differentiator group, the FIR filter, the second differentiator group is operated under the identical clock with splitter; Second integral device group is operated under the identical clock with complex mixer.
Described FPGA digital frequency-selecting submodule is in internal processes, selected mixer, the first differentiator group, FIR filter, the second differentiator group and splitter all have the shift register group of called after Dg, the pipeline series of this shift register group is P, equals the input number of mixer.
Described FPGA digital frequency-selecting submodule is in internal processes, in three selected clock zones, be used for the work clock in second clock territory of filtering for the work clock that is used for the first down-sampled clock zone with the several times of the work clock that rises the 3rd clock zone of sampling.
A kind of digital frequency-selecting method that solves resource consumption of the present invention, the data of AD output enter FPGA digital frequency-selecting submodule, carry out digital multiselect by FPGA digital frequency-selecting submodule and frequently process, and its processing procedure is:
Digital frequency-selecting device for K choosing (number of channel is K) adopts 2K digital mixer, and channel to be selected is moved zero-frequency; Rear up-downgoing channel center frequency is consistent if AD owes to sample, and then adopts K digital mixer, and each digital mixer produces respectively I and Q two paths of signals, and the up-downgoing channel produces 4K road signal altogether;
Each frequency mixer needs two-way to be respectively sin and cos signal as carrier frequency, and the generation of sin and cos signal is based on direct digital frequency synthesis technology (DDS);
The 4K road signal of digital mixer output is sent into respectively the first integrator group of down-conversion, and the first integrator group of each down-conversion is made of the integrator of several cascades;
The decimator that the output of each first integrator group is R by a reduction of speed rate respectively, reduction of speed rate are the operation that the decimator of R is finished one of every R sample value output;
The signal of 4K decimator output is input to mixer, and mixer is merged into one road signal with 4K road signal; Merging process can run into following three kinds of situations:
(1) when 4K=R, mixer adopts identical work clock with decimator, and wherein mixer has R input;
(2) when 4K＜R,
If 1. mixer adopts identical work clock with decimator, then adopt the mixer that R input arranged, wherein R-4K input zero padding;
If 2. the clock of mixer be decimator e doubly, adopt then eR arranged that (mixer of individual input of eR＞=4K) is wherein inputted zero padding for eR-4K;
(3) when 4K＞R, the clock that makes mixer be decimator e doubly so that eR＞=4K; At this moment, adopt the mixer that eR input arranged, wherein eR-4K input zero padding.
Mixer, the first differentiator group, FIR filter, the second differentiator group and splitter are operated under the identical clock; Mixer, the first differentiator group, FIR filter, the second differentiator group and splitter all have the shift register group of called after Dg, and the pipeline series of this shift register group is P, equal the input number of combiner;
The output signal of mixer is input to the first differentiator group, and the first differentiator group is made of the differentiator of several cascades;
The output of the first differentiator group is connected to the input of FIR filter;
The output of FIR filter is connected to the input of the second differentiator group, and the second differentiator group is made of the differentiator of several cascades;
The output of the second differentiator group is connected with the input of splitter;
Splitter becomes the output of P road with signal decomposition, obtains 4K effectively output after screening;
The 4K of splitter effectively output signal is defeated by respectively 4K and rises sampler, 4K raising speed rate be R rise sampler in the middle of per two data, insert R-1 zero;
The individual output that rises sampler of 4K is connected respectively to the input of second integral device group;
The output of 4K second integral device group is connected respectively to 2K complex mixer, and namely per 2 second integral device groups connect a complex mixer;
Complex mixer produces both positive and negative output, the positive output addition that all are up, the negative output addition that all are up, the positive output addition that all are descending, the negative output addition that all are descending;
4 output signals of 4 adder generations are given the DA transducer.
The invention has the beneficial effects as follows, owing to adopted the digital frequency-selecting mode based on multi-clock zone, so that under the reduce sampling frequency R that determines, the channel quantity that shares one group of filter surpasses reduce sampling frequency R, and only be subject to the maximum clock that system can reach, can effectively solve the problem that productivity of the prior art is poor, coverage rate is low.
Compared with prior art of the present invention, have following advantage: the one,, share one group of filter channel quantity is significantly improved, can effectively reduce resource consumption; The 2nd,, the channel of intermediate frequency is selected, filtering realizes that with work clock cost advantage is obvious; The 3rd,, product operation stability and reliability are high, and later maintenance is convenient.
Below in conjunction with drawings and Examples the present invention is described in further detail; But a kind of digital frequency-selecting method that solves resource consumption of the present invention is not limited to embodiment.
Description of drawings
Fig. 1 is the schematic diagram of the selected digital frequency-selecting device of realization the inventive method;
Fig. 2 is the schematic diagram of the selected FPGA digital frequency-selecting submodule of realization the inventive method;
Fig. 3 is the schematic diagram of realizing the frequency mixer in the selected FPGA digital frequency-selecting submodule of the inventive method;
Fig. 4 is the schematic diagram of realizing the Direct Digital Frequency Synthesizers (DDS) in the selected FPGA digital frequency-selecting submodule of the inventive method;
Fig. 5 is the schematic diagram of realizing the integrator group in the selected FPGA digital frequency-selecting submodule of the inventive method;
Fig. 6 is the schematic diagram of realizing the integrator of the integrator group in the selected FPGA digital frequency-selecting submodule of the inventive method;
Fig. 7 is the schematic diagram of realizing the Dg register group in the selected FPGA digital frequency-selecting submodule of the inventive method;
Fig. 8 is the schematic diagram of realizing the differentiator group in the selected FPGA digital frequency-selecting submodule of the inventive method;
Fig. 9 is the schematic diagram of realizing the differentiator of the differentiator group in the selected FPGA digital frequency-selecting submodule of the inventive method;
Figure 10 is the schematic diagram of realizing the FIR filter in the selected FPGA digital frequency-selecting submodule of the inventive method;
Figure 11 is the schematic diagram of realizing the decimator in the selected FPGA digital frequency-selecting submodule of the inventive method;
Figure 12 is the schematic diagram that rises sampler of realizing in the selected FPGA digital frequency-selecting submodule of the inventive method;
Figure 13 is the schematic diagram of realizing the complex mixer in the selected FPGA digital frequency-selecting submodule of the inventive method.
Embodiment
Embodiment, shown in accompanying drawing, a kind of digital frequency-selecting method that solves resource consumption of the present invention, be to adopt as shown in Figure 1 digital frequency-selecting device to realize that digital multiselect processes frequently, this digital frequency-selecting device comprises descending low-converter 11, descending ADC12, descending DAC13, descending upconverter 14, descending local oscillator 15, FPGA digital frequency-selecting submodule 3, up low-converter 21, up ADC22, up DAC23, up upconverter 24, up local oscillator 25, power management submodule 10, monitoring submodule 20 and Clock management submodule 30.
The input of descending low-converter 11 is connected to the low noise module of down link, the output of descending low-converter 11 is connected to the input of descending ADC12, the output of descending ADC12 is connected to the input of FPGA digital frequency-selecting submodule 3, the output of FPGA digital frequency-selecting submodule 3 is connected to the input of descending DAC13, the output of descending DAC13 is connected to the input of descending upconverter 14, the output of descending upconverter 14 is connected to the power amplifier module of down link, and descending local oscillator 15 is connected with descending upconverter 14 with descending low-converter 11 respectively; The input of up low-converter 21 is connected to the low noise module of up link, the output of up low-converter 21 is connected to the input of up ADC22, the output of up ADC22 is connected to the input of FPGA digital frequency-selecting submodule 3, the output of FPGA digital frequency-selecting submodule 3 is connected to the input of up DAC23, the output of up DAC23 is connected to the input of up upconverter 24, the output of up upconverter 24 is connected to the power amplifier module of up link, and up local oscillator 25 is connected with up upconverter 24 with up low-converter 21 respectively; Power management submodule 10 is connected to that the normal operation for modules provides power supply in up link and the down link; Monitoring submodule 20 is connected in up link and the down link carries out the initialization setting to modules, the operating state of supervisory control system; Clock management submodule 30 is connected with FPGA digital frequency-selecting submodule 3, descending ADC12, descending DAC13, up ADC22 and up DAC23 respectively, and Clock management submodule 30 is to FPGA digital frequency-selecting submodule 3, descending ADC12, descending DAC13, up ADC22 and up DAC23 clock signal.
A kind of digital frequency-selecting method that solves resource consumption of the present invention, to adopt as shown in Figure 2 FPGA digital frequency-selecting submodule 3 to realize that digital multiselect processes frequently, this FPGA digital frequency-selecting submodule 3 comprises the individual frequency mixer 301 of 2K (K channel), a 4K first integrator group 302, a 4K decimator 303, a mixer 304, one first differentiator group 305, one FIR filter, 306, one second differentiator groups 307, a splitter 308, individual sampler 309, a 4K second integral device group 310, a 2K complex mixer 311 and four adders 312 of rising of 4K.
Up link and the descending AD output that connects the road are connected to respectively 2K frequency mixer 301; The output of 2K frequency mixer 301 is connected to respectively the input of 4K first integrator group 302, i.e. the output of 1 frequency mixer 301 is divided into two the tunnel and connects two first integrator groups 302; The output of 4K first integrator group 302 respectively correspondence connects 4K decimator 303, i.e. the output of each first integrator group 302 connects a decimator 303; The output of 4K decimator 303 is connected to a mixer 304; The output of mixer 304 connects the input of the first differentiator group 305; The output of differentiator group 305 connects the input of FIR filter 306; The output of FIR filter 306 connects the input of the second differentiator group 307; The output of the second differentiator group 307 connects the input of splitter 308; The output of splitter 308 connects respectively 4K input that rises sampler 309; The output that 4K rises sampler 309 connects respectively the input of 4K second integral device group 310, i.e. each output that rises sampler 309 connects a second integral device group 310; The output of 4K second integral device group 310 connects respectively the input of 2K complex mixer 311, i.e. the output of per two second integral device groups 310 connects a complex mixer 311; The output of 2K complex mixer 311 is connected to respectively the input of four adders 312,312 pairs of all up positive output additions of an adder, 312 pairs of all up negative output additions of another adder, 312 pairs of all descending positive output additions of another adder, 312 pairs of all descending negative output additions of another adder.
A kind of digital frequency-selecting method that solves resource consumption of the present invention, be FPGA digital frequency-selecting submodule 3 is connected to the down link that is made of descending low-converter 11, descending ADC12, descending DAC13, descending upconverter 14 and the up link that consisted of by up low-converter 21, up ADC22, up DAC23, up upconverter 24 in, digital multiselect is carried out in the AD output of down link and up link frequently process, and input returns to down link and up link as DA with result;
The up low noise module output signal of up link enters up low-converter 11 and is transformed to intermediate-freuqncy signal, intermediate-freuqncy signal enters up ADC12 and is with the logical sampling of owing, data after the sampling enter FPGA digital frequency-selecting submodule 3 and carry out digital multiselect and frequently process, process rear the input as DA and be sent to up DAC13 generation intermediate-freuqncy signal, intermediate-freuqncy signal is exported after up upconverter 14 is transformed to radiofrequency signal;
The descending low noise module output signal of down link enters descending low-converter 21 and is transformed to intermediate-freuqncy signal, intermediate-freuqncy signal enters descending ADC22 and is with the logical sampling of owing, data after the sampling enter FPGA digital frequency-selecting submodule 3 and carry out digital multiselect and frequently process, process rear the input as DA and be sent to descending DAC23 generation intermediate-freuqncy signal, intermediate-freuqncy signal is exported after descending upconverter 24 is transformed to radiofrequency signal;
FPGA digital frequency-selecting submodule 3 is in internal processes, sequentially, adopt three clock zones digital signal to be carried out the processing of down-sampled, filtering and liter sampling: in the first clock zone, to be to carry out sequential processes with frequency mixer 301, first integrator group 302 and 303 pairs of signals of decimator; In the second clock territory, be that FIR filter 306, the second differentiator groups 307 and 308 pairs of signals of splitter carry out sequential processes with mixer 304, the first differentiator groups 305; In the 3rd clock zone, be to carry out sequential processes with rising sampler 309, second integral device group 310 and 311 pairs of signals of complex mixer.
Described FPGA digital frequency-selecting submodule 3 for predefined number of channel K, reduce sampling frequency R and multiple e, is that the output with 4K decimator is input in the mixer 304 in internal processes, by mixer 304 4K road signal is merged into one road signal;
Wherein,
When 4K=R, mixer adopts identical work clock with decimator, and wherein mixer has R input;
When 4K＜R, if mixer adopts identical work clock with decimator, then adopt the mixer that R input arranged, wherein input zero padding for R-4K; If the clock of mixer is e times of decimator, then employing has the eR (eR＞=4K) mixer of individual input, wherein eR-4K input zero padding;
When 4K＞R, the clock that makes mixer be decimator e doubly so that eR＞=4K; At this moment, adopt the mixer that eR input arranged, wherein eR-4K input zero padding.
Described FPGA digital frequency-selecting submodule 3 is in internal processes, wherein: frequency mixer 301, first integrator group 302 are operated under the identical clock; Mixer 304, the first differentiator groups 305, FIR filter 306, the second differentiator groups 307 are operated under the identical clock with splitter 308; Second integral device group 310 is operated under the identical clock with complex mixer 311.
Described FPGA digital frequency-selecting submodule 3 is in internal processes, selected mixer 304, the first differentiator group 305, FIR filter 306, the second differentiator group 307 and splitter 308 all have the shift register group of called after Dg, the pipeline series of this shift register group is P, equals the input number of mixer.
Alternatively, described FPGA digital frequency-selecting submodule 3 is in internal processes, in three selected clock zones, the work clock that is used for the second clock territory of filtering can be for the work clock that is used for the first down-sampled clock zone with the several times of the work clock that rises the 3rd clock zone of sampling.
A kind of digital frequency-selecting method that solves resource consumption of the present invention, the data of AD output enter FPGA digital frequency-selecting submodule 3, carry out digital multiselect by FPGA digital frequency-selecting submodule 3 and frequently process, and its processing procedure is:
Digital frequency-selecting device for K choosing (number of channel is K) adopts 2K digital mixer 301, and channel to be selected is moved zero-frequency; Rear up-downgoing channel center frequency is consistent if AD owes to sample, and then adopts K digital mixer 301, and each digital mixer 301 produces respectively I and Q two paths of signals, and the up-downgoing channel produces 4K road signal altogether;
Each frequency mixer 301 needs two-way to be respectively sin and cos signal as carrier frequency, and the generation of sin and cos signal is based on direct digital frequency synthesis technology (DDS);
The 4K road signal of digital mixer 301 outputs is sent into respectively the first integrator group 302 of down-conversion, and the first integrator group 302 of each down-conversion is made of the integrator of several cascades;
The decimator 303 that the output of each first integrator group 302 is R by a reduction of speed rate respectively, reduction of speed rate are the operation that the decimator 303 of R is finished one of every R sample value output;
The signal of 4K decimator 303 outputs is input to mixer 304, and mixer 304 is merged into one road signal with 4K road signal; Merging process can run into following three kinds of situations:
(1) when 4K=R, mixer adopts identical work clock with decimator, and wherein mixer has R input;
(2) when 4K＜R,
If 1. mixer adopts identical work clock with decimator, then adopt the mixer that R input arranged, wherein R-4K input zero padding;
If 2. the clock of mixer be decimator e doubly, adopt then eR arranged that (mixer of individual input of eR＞=4K) is wherein inputted zero padding for eR-4K;
(3) when 4K＞R, the clock that makes mixer be decimator e doubly so that eR＞=4K; At this moment, adopt the mixer that eR input arranged, wherein eR-4K input zero padding.
Mixer 304, the first differentiator group 305, FIR filter 306, the second differentiator group 307 and splitter 308 are operated under the identical clock; Mixer 304, the first differentiator group 305, FIR filter 306, the second differentiator group 307 and splitter 308 all have the shift register group of called after Dg, and the pipeline series of this shift register group is P, equal the input number of combiner;
The output signal of mixer 304 is input to the first differentiator group 305, the first differentiator groups 305 and is made of the differentiator of several cascades;
The output of the first differentiator group 305 is connected to the input of FIR filter 306;
The output of FIR filter 306 is connected to the input of the second differentiator group 307, and the second differentiator group 307 is made of the differentiator of several cascades;
The output of the second differentiator group 307 is connected with the input of splitter 308;
Splitter 308 becomes the output of P road with signal decomposition, obtains 4K effectively output after screening;
The 4K of splitter 308 effectively output signal is defeated by respectively 4K and rises sampler 309,4K raising speed rate be R rise sampler 309 in the middle of per two data, insert R-1 zero;
The individual output that rises sampler 309 of 4K is connected respectively to the input of second integral device group 310;
The output of 4K second integral device group 310 is connected respectively to 2K complex mixer 311, and namely per 2 second integral device groups connect a complex mixer;
Complex mixer 31 1 produces both positive and negative output, the positive output addition that all are up, the negative output addition that all are up, the positive output addition that all are descending, the negative output addition that all are descending;
4 output signals of 4 adder 312 generations are given the DA transducer.
Here the GSM digital frequency-selecting device take one 16 choosing illustrates the digital frequency-selecting method that the present invention proposes as example, for satisfying delay requirement, makes that the AD converter sample rate is 81.92Mbps, and reduce sampling frequency R is that the number of taps of 32, FIR filter is 23; Because K=16, so 4K=64 then is 4K＞R; The work clock of this seasonal mixer, the first differentiator group, FIR filter, the second differentiator group and splitter is 163.84, and namely the work clock of clock zone 2 is 2 times of clock zone 1 work clock; Because eR=4K, 64 road signals that 16 choosings generate only need share one group of mixer, the first differentiator group, FIR filter, the second differentiator group and splitter, have namely saved another group mixer, the first differentiator group, FIR filter, the second differentiator group and splitter that prior art need to adopt; Therefore under the constant condition of the time delay that keeps determining, the present invention can effectively reduce resource consumption.
Above-described embodiment only is used for further specifying a kind of digital frequency-selecting method that solves resource consumption of the present invention; but the present invention is not limited to embodiment; every foundation technical spirit of the present invention all falls in the protection range of technical solution of the present invention any simple modification, equivalent variations and modification that above embodiment does.
Claims (6)
1. digital frequency-selecting method that solves resource consumption, it is characterized in that: be FPGA digital frequency-selecting submodule is connected to the down link that is made of descending low-converter, descending ADC, descending DAC, descending upconverter and the up link that consisted of by up low-converter, up ADC, up DAC, up upconverter in, digital multiselect is carried out in the AD output of down link and up link frequently process, and input returns to down link and up link as DA with result;
The up low noise module output signal of up link enters up low-converter and is transformed to intermediate-freuqncy signal, intermediate-freuqncy signal enters up ADC and is with the logical sampling of owing, data after the sampling enter FPGA digital frequency-selecting submodule and carry out digital multiselect and frequently process, process rear the input as DA and be sent to up DAC generation intermediate-freuqncy signal, intermediate-freuqncy signal is exported after up upconverter is transformed to radiofrequency signal;
The descending low noise module output signal of down link enters descending low-converter and is transformed to intermediate-freuqncy signal, intermediate-freuqncy signal enters descending ADC and is with the logical sampling of owing, data after the sampling enter FPGA digital frequency-selecting submodule and carry out digital multiselect and frequently process, process rear the input as DA and be sent to descending DAC generation intermediate-freuqncy signal, intermediate-freuqncy signal is exported after descending upconverter is transformed to radiofrequency signal;
FPGA digital frequency-selecting submodule is in internal processes, sequentially, adopt three clock zones digital signal to be carried out the processing of down-sampled, filtering and liter sampling: in the first clock zone, to be with frequency mixer, first integrator group and decimator signal to be carried out sequential processes; In the second clock territory, be to use mixer, the first differentiator group, the FIR filter, the second differentiator group and splitter carry out sequential processes to signal; In the 3rd clock zone, be with rising sampler, second integral device group and complex mixer signal to be carried out sequential processes.
2. digital frequency-selecting method according to claim 1, it is characterized in that: described FPGA digital frequency-selecting submodule is in internal processes, for predefined number of channel K, reduce sampling frequency R and multiple e, be that output with 4K decimator is input in the mixer, by mixer 4K road signal be merged into one road signal;
Wherein,
When 4K=R, mixer adopts identical work clock with decimator, and wherein mixer has R input;
When 4K＜R, if mixer adopts identical work clock with decimator, then adopt the mixer that R input arranged, wherein input zero padding for R-4K; If the clock of mixer is e times of decimator, then adopt the mixer that eR input arranged, wherein eR 〉=4K, wherein eR-4K input zero padding;
As 4K〉during R, the clock that makes mixer be decimator e doubly so that eR 〉=4K; At this moment, adopt the mixer that eR input arranged, wherein eR-4K input zero padding.
3. digital frequency-selecting method according to claim 1, it is characterized in that: described FPGA digital frequency-selecting submodule is in internal processes, wherein: frequency mixer, first integrator group are operated under the identical clock; Mixer, the first differentiator group, the FIR filter, the second differentiator group is operated under the identical clock with splitter; Second integral device group is operated under the identical clock with complex mixer.
4. according to claim 1 and 2 or 3 described digital frequency-selecting methods, it is characterized in that: described FPGA digital frequency-selecting submodule is in internal processes, selected mixer, the first differentiator group, FIR filter, the second differentiator group and splitter all have the shift register group of called after Dg, the pipeline series of this shift register group is P, equals the input number of mixer.
5. according to claim 1 or 3 described digital frequency-selecting methods, it is characterized in that: described FPGA digital frequency-selecting submodule is in internal processes, in three selected clock zones, be used for the work clock in second clock territory of filtering for the work clock that is used for the first down-sampled clock zone with the several times of the work clock that rises the 3rd clock zone of sampling.
6. digital frequency-selecting method according to claim 4, it is characterized in that: described FPGA digital frequency-selecting submodule is in internal processes, in three selected clock zones, be used for the work clock in second clock territory of filtering for the work clock that is used for the first down-sampled clock zone with the several times of the work clock that rises the 3rd clock zone of sampling.
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