CN101969049B - method for manufacturing top region of poly-crystal word line of flash memory device - Google Patents
method for manufacturing top region of poly-crystal word line of flash memory device Download PDFInfo
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- CN101969049B CN101969049B CN200910055433A CN200910055433A CN101969049B CN 101969049 B CN101969049 B CN 101969049B CN 200910055433 A CN200910055433 A CN 200910055433A CN 200910055433 A CN200910055433 A CN 200910055433A CN 101969049 B CN101969049 B CN 101969049B
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Abstract
The invention discloses a method for manufacturing a top region of poly-crystal word lines of a flash memory device, which is suitable for manufacturing the poly-crystal word lines of the flash memory device and a connected duo-diode structure. The manufacturing method comprises the following steps of: forming an N well, a deep layer N well and a P well on a P-type silicon substrate; forming a STI (Shallow Trench Isolation) on the P-type silicon substrate; forming the poly-crystal word lines on the STI, wherein the top ends of the odd poly-crystal word lines are in a Christmas tree shape and are connected with the duo-diode structure via metal layers through contact holes of upper layers; through ion implantation, sequentially forming a P-type doping region, a P-type source electrode region, a P-type drain electrode region and an N-type grid electrode region between the P-type source electrode region and the N well in the STI to form the duo-diode structure; and forming the contact holes of the upper layers for the odd poly-crystal word lines, the P-type source electrode region, the N-type grid electrode region and the P-type drain electrode region, wherein the odd poly-crystal word lines and the P-type source electrode region are respectively connected with the same metal layer through the contact holes of the upper layers. The method ensures that the manufactured flash memory device has better reliability at an application client.
Description
Technical field
The present invention relates to semiconductor fabrication, the manufacture method of the polycrystalline word line apex zone of particularly a kind of flush memory device (flash).
Background technology
Flush memory device is a kind of as memory device, is widely used.In flush memory device, need carry out etching to polycrystalline, form some word lines (WL, Word Line) layers, and the top of this polycrystalline word line is arranged in the Christmas tree shape, to connect the layer metal interconnection on contact hole and upper strata.In flush memory device manufacturing process; In order to deflect from last part technology to the charging damage that produces in the ion etching process of metal; Need be connected on the device silicon substrate through double diode structure (DD, Double Diode) the positions of odd wordlines polycrystalline in the polycrystalline WL layer apex zone.
Fig. 1 is for the cross-sectional view of the odd number polycrystalline word line apex zone (double diode that comprises polycrystalline word line and connection thereof) of prior art flush memory device, and is as shown in the figure, comprising:
Step 1, on P type device silicon substrate 101, form two traps, promptly form N trap and P trap;
In this step, the N trap of formation is made up of deep layer N trap and N trap, and junction depth is darker than the junction depth of formed P trap, such as dark more than one times; The NP knot that forms like this can bear higher voltage;
Step 2, on P type device silicon substrate 101, form shallow-trench isolation (STI) 102;
Step 3, formation odd number polycrystalline word line, wherein odd number polycrystalline word line top becomes the Christmas tree shape, to be connected with the double diode structure through the metal level of contact hole through the upper strata;
Step 4, inject through ion and successively to form P type source area 103 and P type drain region 105, N type gate regions 104, form the double diode structure;
Step 5, odd number polycrystalline word line, P type source area 103, N type gate regions 104 and P type drain region 105 formed contact holes after, wherein odd number polycrystalline word line is connected with same metal level 107 through contact hole respectively with P type source area 103;
In this step, odd number polycrystalline word line has been connected with the double diode structure through the metal level of contact hole through the upper strata.
In Fig. 1, show through contact hole 106 and metal level 107 interconnection on the odd number polycrystalline word line that STI 102 forms with P type source area 103.
In this structure, the zone of double diode is the PN junction of P type source area 103 and the formation of N trap, and the NP knot of N trap and 101 formation of P type device device silicon substrate.
Different with odd number polycrystalline word line, the even number polycrystalline word line of flush memory device is not connected with the double diode structure.
Though the double diode structure that odd number polycrystalline word line is connected has very great help to the ion dam age that alleviates in the flush memory device manufacturing process; But; The flush memory device of making like this is when using, because double diode zone PN junction is more shallow in the odd number polycrystalline word line, easy formation punctures; Leakage current occurs, thereby the voltage that causes being added on the coupled odd number polycrystalline word line that connects descends.Particularly, under the normal condition, on the polycrystalline word line, apply 10V voltage through peripheral circuit, because the existence of polycrystalline resistance, the pressure drop on the top of this polycrystalline word line is about 9.5V, and this time, flush memory device can operate as normal.But because the existence of the leakage current of double diode structure; Pressure drop meeting on the top of the coupled odd number polycrystalline word line that connects is reduced to 7～8 volts greatly, and even number polycrystalline word line is not owing to be connected with double diode, so its top pressure drop still remains on about 9.5 volts; Like this; Pressure drop on odd number polycrystalline word line and the even number polycrystalline word line does not match, and causes flush memory device in application end, for example when the storage data, is easy to occur losing efficacy.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of polycrystalline word line apex zone of flush memory device, this method can guarantee that the flush memory device of manufacturing has better reliability in application end.
For achieving the above object, the technical scheme of the embodiment of the invention specifically is achieved in that
A kind of manufacture method of polycrystalline word line apex zone of flush memory device is applicable to the making of double diode structure of polycrystalline word line and the connection of flush memory device, comprising:
On P type silicon substrate, form N trap, deep layer N trap and P trap;
On P type silicon substrate, form the shallow trench isolation STI;
On STI, form the polycrystalline word line, wherein odd number polycrystalline word line top becomes the Christmas tree shape, and the contact hole through the upper strata is connected with the double diode structure through metal level;
In STI, inject, successively between P type source area and N trap, form P type light doping section, P type source area and P type drain region and N type gate regions, constitute the double diode structure through ion;
Behind odd number polycrystalline word line, P type source area, N type gate regions and formation upper strata, P type drain region contact hole, wherein odd number polycrystalline word line is connected with same metal level through the upper strata contact hole respectively with P type source area.
The dopant of said P type light doping section is boron or boron fluoride.
It is 15～25 kilo electron volts that the ion of said P type light doping section injects the energy that adopts, and dosage is 1.5～2.5 * 103 atoms/every square centimeter, does not vertically have the angle of inclination and injects.
The ion of said P type light doping section injects that the peripheral cmos circuit that is with flush memory device adopts the ion of lightly doped drain LDD technology to inject to carry out simultaneously.
Visible by technique scheme; The present invention is at the apex zone of the Christmas tree shape of the odd number polycrystalline word line of making flush memory device; The double diode structure that comprises odd number polycrystalline word line and connection thereof; The ion that carries out when adopting lightly doped drain (LDD) technology with the flush memory device peripheral circuit injects, and between P type source area and N trap, forms P type light doping section, makes that the PN junction junction depth in the double diode structure is deepened.Like this; In application end; Comprise data storage, wipe and read, when applying voltage for the flush memory device of manufacturing, just can not occur not causing the pressure drop on the odd number polycrystalline word line to descend owing to the leakage current of double diode structure; Thereby the operating voltage of operating voltage and even number polycrystalline word line of odd number polycrystalline word line that makes flush memory device is identical or be more or less the same, and guarantees that the flush memory device of manufacturing has better reliability performance in application end.
Description of drawings
Fig. 1 is the cross-sectional view of the odd number polycrystalline word line apex zone (double diode that comprises polycrystalline word line and connection thereof) of prior art flush memory device;
Fig. 2 is the method flow diagram of the odd number polycrystalline word line apex zone of manufacturing flush memory device provided by the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is done further explain.
Can learn from background technology, because the apex zone of the odd number polycrystalline word line of flush memory device is connected with the double diode structure, and be prone to leakage current in this double diode structure, thereby cause being added in the voltage decline on the coupled odd number polycrystalline word line that connects.Therefore,, when for example flush memory device being carried out the storage of data, need apply a higher voltage to the polycrystalline word line in application end, could with realize the operation of design in advance.But, the existence of the leakage current of double diode structure because the voltage of even number polycrystalline word line not have and voltage descends, thus act on this moment the pressure drop of even number polycrystalline word line will be higher in the magnitude of voltage of design in advance, thereby the inefficacy of excessively storing appears.
The double diode structure that the odd number polycrystalline word line apex zone of flush memory device is connected can produce leakage current when application end applies voltage reason is: because the effect that is of this double diode structure is the electric charge that in the processing procedure process, prevents to produce in the back segment ion etching process charging damage to grid, source-drain electrode layer; Therefore can export on the silicon substrate through this double diode structure as long as guarantee the electric charge that produces in the back segment ion etching process; So what the PN junction junction depth of this double diode structure was made in background technology is all superficial; This can cause when application end applies voltage to flush memory device; The PN junction of this double diode structure is easy to breakdown (voltage that applies generally all is higher than the puncture voltage of this PN junction), causes the leakage current generating of this double diode structure.
Therefore; The present invention increases the PN junction junction depth of the double diode structure that the odd number polycrystalline word line apex zone of flush memory device is connected; The mode that adopts be with double diode structural region that odd number polycrystalline word line is connected in the additional P of injection type alloy, P type alloy can be boron or boron fluoride.
Fig. 2 is the method flow diagram of the odd number polycrystalline word line apex zone of manufacturing flush memory device provided by the invention, and this zone comprises the double diode structure of odd number polycrystalline word line and connection thereof, and its concrete steps are:
In this step, the N trap of formation is made up of deep layer N trap and N trap, and junction depth is darker than the junction depth of formed P trap, such as dark more than one times;
In above-mentioned steps, how to form STI and how to form the polycrystalline word line and can adopt existing techniques in realizing, no longer tired here stating;
In this step, the P type alloy that P type light doping section ion injects can be boron or boron fluoride, and when injecting boron, the energy of employing is 15～25 electron-volts, and dosage is 1.5～2.5 * 10
3Atom/every square centimeter, no angle of inclination is vertically injected;
Like this, just can deepen P type source area 103 and the PN junction that the N trap forms, improve puncture voltage, prevent leakage current to occur in the application end of flush memory device.
In this step, odd number polycrystalline word line has been connected with the double diode structure through the metal level of contact hole through the upper strata.
Can find out that the present invention compares prior art, in step 204, increase and gently mixed up injection, between P type source area 103 and N trap, form P type light doping section.On concrete the realization, when execution in step 204, carry out simultaneously with the ion implantation technology of the lightly doped drain (LDD) in the peripheral circuit CMOS zone of flush memory device, just adopt LDD technology to carry out the process that ion injects and carry out simultaneously with peripheral circuit CMOS.The condition that ion injects and P type the alloy all ion implantation technology with the peripheral circuit region CMOS of flush memory device are identical, thereby avoid making again a light shield, save fabrication steps, the saving cost.
More than lift preferred embodiment; The object of the invention, technical scheme and advantage have been carried out further explain, and institute it should be understood that the above is merely preferred embodiment of the present invention; Not in order to restriction the present invention; All within spirit of the present invention and principle, any modification of being done, be equal to replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. the manufacture method of the polycrystalline word line apex zone of a flush memory device is applicable to the making of double diode structure of polycrystalline word line and the connection of flush memory device, and said polycrystalline word line is for to carry out etching to polycrystalline, and some word lines of formation comprise:
On P type silicon substrate, form N trap, deep layer N trap and P trap;
On P type silicon substrate, form the shallow trench isolation STI;
Form the polycrystalline word line, wherein odd number polycrystalline word line is connected with the double diode structure through metal level through the contact hole on upper strata;
Inject through ion, successively between P type source area and N trap, form P type light doping section, P type source area and P type drain region and N type gate regions, constitute the double diode structure;
Behind odd number polycrystalline word line, P type source area, N type gate regions and formation upper strata, P type drain region contact hole, wherein odd number polycrystalline word line is connected with same metal level through the upper strata contact hole respectively with P type source area.
2. the method for claim 1 is characterized in that, the dopant of said P type light doping section is boron or boron fluoride.
3. according to claim 1 or claim 2 method is characterized in that, it is 15～25 kilo electron volts that the ion of said P type light doping section injects the energy that adopts, and dosage is 1.5～2.5 * 10
3Atom/every square centimeter does not vertically have the angle of inclination and injects.
4. according to claim 1 or claim 2 method is characterized in that, the ion of said P type light doping section injects that the peripheral cmos circuit that is with flush memory device adopts the ion of lightly doped drain LDD technology to inject to carry out simultaneously.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910055433A CN101969049B (en) | 2009-07-27 | 2009-07-27 | method for manufacturing top region of poly-crystal word line of flash memory device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910055433A CN101969049B (en) | 2009-07-27 | 2009-07-27 | method for manufacturing top region of poly-crystal word line of flash memory device |
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| CN101969049A CN101969049A (en) | 2011-02-09 |
| CN101969049B true CN101969049B (en) | 2012-09-26 |
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| CN113130500B (en) * | 2019-12-31 | 2023-11-07 | 无锡华润微电子有限公司 | Semiconductor device and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5679591A (en) * | 1996-12-16 | 1997-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd | Method of making raised-bitline contactless trenched flash memory cell |
| CN1420566A (en) * | 2001-11-15 | 2003-05-28 | 力旺电子股份有限公司 | Non-volatile semiconductor storage unit structure and mfg. method thereof |
| CN1453877A (en) * | 2002-04-24 | 2003-11-05 | 力旺电子股份有限公司 | Monocrystalline/polycrystalline flash memory unit structure and array with low operation voltage |
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- 2009-07-27 CN CN200910055433A patent/CN101969049B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5679591A (en) * | 1996-12-16 | 1997-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd | Method of making raised-bitline contactless trenched flash memory cell |
| CN1420566A (en) * | 2001-11-15 | 2003-05-28 | 力旺电子股份有限公司 | Non-volatile semiconductor storage unit structure and mfg. method thereof |
| CN1453877A (en) * | 2002-04-24 | 2003-11-05 | 力旺电子股份有限公司 | Monocrystalline/polycrystalline flash memory unit structure and array with low operation voltage |
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Effective date of registration: 20121116 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
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