CN101963727A - FFS (Fringe Field Switching) type TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array substrate and manufacturing method thereof - Google Patents
FFS (Fringe Field Switching) type TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array substrate and manufacturing method thereof Download PDFInfo
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- CN101963727A CN101963727A CN2009100898292A CN200910089829A CN101963727A CN 101963727 A CN101963727 A CN 101963727A CN 2009100898292 A CN2009100898292 A CN 2009100898292A CN 200910089829 A CN200910089829 A CN 200910089829A CN 101963727 A CN101963727 A CN 101963727A
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Abstract
The invention discloses an FFS (Fringe Field Switching) type TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array substrate and a manufacturing method thereof. The method comprises the following steps of: (1) sequentially depositing a first transparent conductive film, a source drain metal film and a doped semiconductor film on a transparent substrate, and forming a graph comprising a source electrode, a drain electrode, a data line and a pixel electrode through a first composition technology; (2) depositing a semiconductor film and forming a graph comprising a doped semiconductor layer, a TFT channel and a semiconductor layer through a second composition technology; (3) depositing an insulating film and a grid metal film and forming a graph comprising a connecting hole, a grid line, a grid electrode and a public electrode wire through a third composition technology; and (4) depositing a second transparent conductive film and forming a graph comprising a common electrode through a fourth composition technology. The array substrate can be finished preparation through four composition technologies, and compared with the prior art, the invention has the advantages of simplified process steps, short process time, high production efficiency, low production cost, and the like.
Description
Technical field
The present invention relates to a kind of LCD and manufacture method thereof, especially a kind of FFS type TFT-LCD array base palte and manufacture method thereof.
Background technology
Thin-film transistor LCD device (Thin Film Transistor Liquid Crystal Display is called for short TFT-LCD) is a kind of main panel display apparatus (Flat Panel Display abbreviates FPD as).
According to the direction of an electric field that drives liquid crystal, TFT-LCD is divided into vertical electric field type and horizontal electric field type.Wherein, vertical electric field type TFT-LCD need form pixel electrode at array base palte, forms public electrode at color membrane substrates; Yet horizontal electric field type TFT-LCD need form pixel electrode and public electrode simultaneously at array base palte.Therefore, during the array base palte of production technique electric field type TFT-LCD, need extra increase once to form the mask process of public electrode.Vertical electric field type TFT-LCD comprises: twisted-nematic (TwistNematic abbreviates TN as) type TFT-LCD; Horizontal electric field type TFT-LCD comprises: boundary electric field switches (Fringe Field Switching abbreviates FFS as) type TFT-LCD, and copline is switched (In-PlaneSwitching abbreviates IPS as) type TFT-LCD.Horizontal electric field type TFT-LCD, especially FFS type TFT-LCD have wide viewing angle, aperture opening ratio advantages of higher, are widely used in field of liquid crystal.
Fig. 1 is the floor map of existing FFS type TFT-LCD array base palte.As shown in Figure 1, array base palte (Array Substrate) comprising: grid line 1, data line 2, thin film transistor (TFT) (Thin FirmTransistor abbreviates TFT as) 3, pixel electrode 4, public electrode 50 and public electrode wire 5.Grid line 1 is horizontally installed on the transparency carrier, and data line 2 vertically is arranged on the transparency carrier, and grid line 1 is provided with TFT3 with the infall of data line 2.TFT3 is the active switch element.Pixel electrode 4 is a gap electrode.Public electrode 50 is positioned at the below of pixel electrode 4, and most of overlapping, and public electrode 50 and pixel electrode are formed for driving the electric field of liquid crystal.Public electrode wire 5 is connected with public electrode 50.What deserves to be mentioned is that among Fig. 1, Reference numeral " 50 " indication is not to be the slit of strip, but the tabular public electrode of the below of slit.
Fig. 2 a be the A-A of Fig. 1 to sectional view, show the cross-section structure of array base palte.Shown in Fig. 2 a, array base palte specifically also comprises: transparency carrier 11, public electrode 50, gate electrode 12, gate insulation layer 13, semiconductor layer 14, doping semiconductor layer 15, source electrode 16, drain electrode 17, passivation layer 18.Gate electrode 12 is one-body molded with grid line 1, and source electrode 16 is one-body molded with data line 2, and drain electrode 17 generally is connected by passivation layer via hole 180 (via hole) with pixel electrode 4.When importing Continuity signal in the grid line 1, active layer (semiconductor layer 14 and doping semiconductor layer 15) conduction, the data-signal of data line 2 can arrive drain electrodes 17 through TFT raceway groove (channel) 19 from source electrode 16, finally input to pixel electrode 4.Pixel electrode 4 obtains behind the signal being formed for driving the electric field that liquid crystal rotates with tabular public electrode 50.Because pixel electrode 4 has slit 49, therefore form horizontal component of electric field with public electrode 50.
Fig. 2 b is the sectional view in data line zone in the PAD zone of existing FFS type TFT-LCD array base palte; Fig. 2 c is the sectional view of grid region in the PAD zone of existing FFS type TFT-LCD array base palte.The PAD zone is crimp region, is with grid line, data line and the public electrode wire equisignal line zone with the lead-in wire crimping of the drive circuit board of outside.The PAD zone is arranged on one of them or adjacent two limits on 4 limits of array base palte.In order to go between and the signal wire electrical connection, the signal wire top in PAD zone must not have insulation course to cover.As can be seen, the data line 2 in PAD zone and grid line 1 top all offer connecting hole 181,182 from Fig. 2 b and 2c, and data line 2 is connected with the 8th electrically conducting transparent portion 45 with the 7th electrically conducting transparent portion 44 by connecting hole 181,182 respectively with grid line 1.The 7th electrically conducting transparent portion 44 and the 8th electrically conducting transparent portion 45 form when forming pixel electrode by the etching transparent conductive film simultaneously, therefore can conduct electricity.The structure that forms when 140 and 150 among Fig. 2 b is etching doping semiconductor layer 15 and semiconductor layer 14 does not influence the communication of data line 2.So outside lead directly can be welded in the 7th electrically conducting transparent portion 44 and the 8th electrically conducting transparent portion 45, the realization array base palte is connected with drive circuit board.In like manner, the public electrode wire top offers connecting hole too, is used for being connected with outside lead-in wire, and its structure is identical substantially with Fig. 2 c, and figure slightly.
At present, FFS type TFT-LCD array base palte is to form structure graph by composition technology repeatedly to finish, technology such as comprise mask exposure, development, etching each time in the composition technology again respectively and peel off, wherein etching technics comprises dry etching and wet etching, so the number of times of composition technology can be weighed the complicated and simple degree of making the TFT-LCD array base palte, the number of times that reduces composition technology just means the reduction of manufacturing cost.Six composition technologies of prior art comprise: public electrode composition, grid line and gate electrode composition, active layer composition, source electrode/drain electrode composition, via hole composition and pixel electrode composition.
Disclose in a large number in the prior art, reduce manufacturing cost by reducing composition technology number of times, and the technical literature of enhancing productivity by the simplification of technology.Wherein, comparatively leading technology is: by the method for five composition technology manufacturing FFS type TFT-LCD array base paltes.This method comprises:
The manufacture method of this traditional FFS type TFT-LCD array base palte is deposited, in following defective:
1, need 5 composition technologies, cost is higher, and the market competitiveness is low;
2, in the above-mentioned steps 3, in order to form TFT raceway groove, source electrode and drain electrode, need carry out twice etching to whole base plate, generally adopt wet etching to carry out, be about to substrate immersion in etching liquid, etch away the part that is not covered and can be corroded by this etching liquid by photoresist.The TFT raceway groove needs strict control etching parameters during by wet etching, carries out with the method for controlling etching time usually.But because fabrication error exists, the TFT raceway groove takes place by overetch (Over Etch) through regular meeting.For the TFT raceway groove that array base palte is significant, this overetch can produce very important defective, can cause that the TFT raceway groove broadens or directly destroys the TFT raceway groove, and the overall performance and the product percent of pass of LCD produced great negative effect.
Summary of the invention
The purpose of this invention is to provide a kind of TFT-LCD array base palte and manufacture method thereof,, reduce cost, improve the market competitiveness by 4 composition technology manufacturing array substrates.
Another object of the present invention provides a kind of TFT-LCD array base palte and manufacture method thereof, can avoid raceway groove by overetch.
For achieving the above object, the invention provides a kind of manufacture method of FFS type TFT-LCD array base palte, described array base palte comprises public electrode zone, public electrode wire zone, gate electrode zone, data line zone, semiconductor layer zone, the data line zone in source electrode zone, drain electrode zone, grid region, pixel electrode area, PAD zone and the grid region in PAD zone comprise:
Step 1: on transparency carrier, deposit first transparent conductive film, source leakage metallic film and doped semiconductor films successively, comprise source electrode, drain electrode, data line and pattern of pixel electrodes by the formation of the first composition technology;
Step 2: the deposited semiconductor film forms the figure that comprises doping semiconductor layer, TFT raceway groove and semiconductor layer by the second composition technology;
Step 3: deposit insulation film and grid metallic film, form the figure that comprises connecting hole, grid line, gate electrode and public electrode wire by the 3rd composition technology;
For achieving the above object, the present invention also provides a kind of TFT-LCD array base palte that obtains by the manufacture method of above-mentioned FFS type TFT-LCD array base palte.
As shown from the above technical solution, FFS type TFT-LCD array base palte of the present invention and manufacture method thereof have following advantage:
1, the present invention compares the method for existing 6 times or 5 times composition technology manufacturing array substrates, can adopt 4 composition technologies both can prepare and finish, advantage such as have that processing step is simplified, the process time is short, production efficiency is high and production cost is low.
2, the present invention form the TFT raceway groove method compared with prior art, owing to need not the TFT channel region of etching semiconductor layer, can not produce the problem of overetch, the TFT channel region can very accurately design, the performance of LCD can be protected, and yields improves.
Description of drawings
Fig. 1 is the floor map of existing FFS type TFT-LCD array base palte;
Fig. 2 a is that the A-A of Fig. 1 is to sectional view;
Fig. 2 b is the sectional view in data line zone in the PAD zone of existing FFS type TFT-LCD array base palte;
Fig. 2 c is the sectional view of grid region in the PAD zone of existing FFS type TFT-LCD array base palte;
Fig. 3 is the floor map of FFS type TFT-LCD array base palte of the present invention;
Fig. 4 a be among Fig. 3 A1-A1 to sectional view;
Fig. 4 b is the sectional view in the data line zone in the PAD zone of FFS type TFT-LCD array base palte of the present invention;
Fig. 4 c is the sectional view of the grid region in the PAD zone of FFS type TFT-LCD array base palte of the present invention;
Fig. 5 is the sectional view after metallic film and doped semiconductor films are leaked in deposit transparent conductive film, source on the transparency carrier;
Fig. 6 a-Fig. 6 c has been for after having applied photoresist on the structure of Fig. 5, and photoresist has been carried out sectional view after exposure and the development treatment;
Fig. 7 a-Fig. 7 c is for having carried out the sectional view behind first etching technics to the structure of Fig. 6 a-Fig. 6 c;
Fig. 8 a-Fig. 8 c is for having carried out cineration technics sectional view afterwards to the photoresist among Fig. 7 a-Fig. 7 c;
Fig. 9 a-Fig. 9 c is for having carried out the sectional view behind second etching technics to the structure of Fig. 8 a-Fig. 8 c;
Figure 10 a-Figure 10 c is for having peeled off the sectional view behind the residue photoresist on the structure of Fig. 9 a-Fig. 9 c;
Figure 11 a-Figure 11 c is for having deposited the sectional view behind the semiconductive thin film on the structure of Figure 10 a-Figure 10 c;
Figure 12 a-Figure 12 c for apply photoresist on the structure of Figure 11 a-Figure 11 c and expose and development treatment after sectional view;
Figure 13 a-Figure 13 c is for carrying out the sectional view behind the 3rd etching technics to the structure of Figure 12 a-Figure 12 c;
Figure 14 a-Figure 14 c is the sectional view behind deposition insulation film and grid metallic film on the structure of Figure 13 a-Figure 13 c;
Figure 15 a-Figure 15 c on the structure of Figure 14 a-Figure 14 c, applied expose behind the photoresist and developing process after sectional view;
Figure 16 a-Figure 16 c is for to carry out the sectional view behind the etching technics the 4th time to the structure of Figure 15 a-Figure 15 c;
Figure 17 a-Figure 17 c is for carrying out the sectional view of cineration technics behind the photoresist to Figure 16 a-Figure 16 c;
Figure 18 a-Figure 18 c is for carrying out the sectional view behind the 5th etching technics to the structure of Figure 17 a-Figure 17 c;
Figure 19 a-Figure 19 c is the sectional view behind deposition second transparent conductive film on the structure in Figure 18 a-Figure 18 c;
Figure 20 a-Figure 20 c exposes behind the photoresist and development treatment sectional view afterwards for having applied on the structure to Figure 19 a-Figure 19 c;
Figure 21 a-Figure 21 c is for having carried out the sectional view behind the 6th etching technics to the structure among Figure 20 a-Figure 20 c.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Need to prove:
1, in for example " X is arranged on the Y " described in the present invention or " X is provided with Y " " on " generally comprised X and contacted with Y, and X is positioned at the meaning of the top of Y, as shown in drawings, transparency carrier is defined as is arranged at below among the present invention;
2, the alleged composition technology of the present invention comprises technologies such as photoresist coating, mask, exposure, development, etching, photoresist lift off, and photoresist is example with the positive photoresist;
3, " so-and-so zone " described in the present invention is the zone that so-and-so figure shines upon on transparency carrier, promptly should the zone and so-and-so figure be of similar shape, grid region for example, be the zone of the mapping of figure on transparency carrier of grid line, also can be understood as the zone that the grid line figure will be set on the transparency carrier.
Fig. 3 is the floor map of FFS type TFT-LCD array base palte of the present invention, and what reflected is the structure of a pixel cell.As shown in Figure 3, present embodiment TFT-LCD array base palte mainly comprises grid line 1 ', data line 2 ', TFT 3 ', pixel electrode 4 ', public electrode 50 ' and public electrode wire 5 '.Orthogonal grid line 1 ' and data line 2 ' have defined pixel cell, TFT3 ' and pixel electrode 4 ' are formed in the pixel cell, pixel electrode 4 ' is positioned at public electrode 50 ' below, public electrode 50 ' is a gap electrode, grid line 1 ' is used for providing start signal to TFT3 ', data line 2 ' is used for providing data-signal to pixel electrode 4 ', and public electrode wire 5 ' provides common electric voltage to public electrode 50 '.TFT3 ' is the active switch element.Among Fig. 3, Reference numeral " 4 ' " indication is not the strip slit, but the tabular pixel electrode of slit below.
Fig. 4 a be among Fig. 3 A1-A1 to sectional view, main reflection be the structure of TFT3 '.Shown in Fig. 4 a, TFT-LCD array base palte of the present invention comprises: transparency carrier 21, the first electrically conducting transparent portion 41, the second electrically conducting transparent portion 42, source electrode 26, drain electrode 27, doping semiconductor layer 25, semiconductor layer 24, gate insulation layer 23 and gate electrode 22.Wherein, the first electrically conducting transparent portion 41, the second electrically conducting transparent portion 42 and pixel electrode 4 ' are arranged on the transparency carrier 21, and the first electrically conducting transparent portion 41 is not connected with the second electrically conducting transparent portion 42 and pixel electrode 4 '; The first electrically conducting transparent portion 41 is provided with source electrode 26; The second electrically conducting transparent portion 42 forms with pixel electrode 4 ' one, and the second electrically conducting transparent portion 42 is provided with drain electrode 27; Be respectively arranged with doping semiconductor layer 25 on source electrode 26 and the drain electrode 27; The doping semiconductor layer 25 of both sides is provided with semiconductor layer 24, and the part that semiconductor layer 24 covers on the transparency carrier 21 forms TFT raceway groove 29; Gate insulation layer 23 is arranged on the said structure figure and covers whole transparency carrier 21; Gate insulation layer 23 is provided with grid motor 22, grid line 1 ', public electrode 50 ' and public electrode wire 5 ', and public electrode 50 ' is connected with public electrode wire 5 '; Gate electrode 22 is arranged at the top of TFT raceway groove 29; Public electrode 50 ' is arranged at the top of pixel electrode 4 ', and is most of overlapping with pixel electrode 4 '.
Fig. 4 b is the sectional view in the data line zone in the PAD zone of FFS type TFT-LCD array base palte of the present invention; Shown in Fig. 4 b, be provided with the 3rd electrically conducting transparent portion 43, data line 2 ', gate insulation layer 23 and the 4th electrically conducting transparent portion 51 successively at transparency carrier 21; Wherein, etched connecting hole 230, the four electrically conducting transparent portions 51 on the gate insulation layer 23 and be connected with data line 2 ' by connecting hole 230, the lead-in wire of external drive circuit plate can be received in the 4th electrically conducting transparent portion 51 the data-signal special delivery is arrived in the data line 2 '.
Fig. 4 c is the sectional view of the grid region in the PAD zone of FFS type TFT-LCD array base palte of the present invention; Shown in Fig. 4 c, on transparency carrier 21, be disposed with gate insulation layer 23, the 5th electrically conducting transparent portion 52 and grid line 1 '.The lead-in wire of external drive circuit plate can be received in the 5th electrically conducting transparent portion 52 the signal special delivery is arrived in the grid line 1 '.
Technique scheme of the present invention is a kind of top gate electrode structure, from Fig. 4 a as can be seen, TFT raceway groove of the present invention is not through over etching, the film thickness of its thickness and deposition is suitable, therefore also take place with regard to the problem that can not produce TFT raceway groove overetch in the prior art, the TFT channel region can very accurately design, and the performance of LCD can be protected, and yields improves.
The following describes the manufacture method of a kind of FFS type TFT-LCD array base palte of the present invention.
The manufacture method of a kind of FFS type of the present invention TFT-LCD array base palte comprises the steps:
Step 1: on transparency carrier, deposit first transparent conductive film, source leakage metallic film and doped semiconductor films successively, comprise source electrode, drain electrode, data line and pattern of pixel electrodes by the formation of the first composition technology;
Step 2: the deposited semiconductor film forms the figure that comprises doping semiconductor layer, TFT raceway groove and semiconductor layer by the second composition technology;
Step 3: deposit insulation film and grid metallic film, form the figure that comprises connecting hole, grid line, gate electrode and public electrode wire by the 3rd composition technology;
The present invention compares the method for existing 6 times or 5 times composition technology manufacturing array substrates, can adopt 4 composition technologies both can prepare and finish, advantage such as have that processing step is simplified, the process time is short, production efficiency is high and production cost is low.
Describe the manufacture method of FFS type TFT-LCD array base palte of the present invention in detail according to sequence of process steps below in conjunction with accompanying drawing Fig. 5-Figure 21 c.
Fig. 5 is the sectional view after metallic film and doped semiconductor films are leaked in deposit transparent conductive film, source on the transparency carrier.As shown in Figure 5, at first adopt plasma reinforced chemical vapour deposition (PECVD), magnetron sputtering, thermal evaporation or other film build method, metallic film 200 and doped semiconductor films 300 are leaked in deposit transparent conductive film 100, source successively on transparency carrier 21 (as glass substrate or quartz base plate).It can be the single thin film that metals such as molybdenum, aluminium, aluminium neodymium alloy, tungsten, chromium, copper form that metallic film 200 is leaked in the source, also can be the multilayer film that above metallic multilayer deposition forms.Transparent conductive film 100 can be ITO, IZO etc.
Fig. 6 a-Fig. 6 c has been for after having applied photoresist on the structure of Fig. 5, and photoresist has been carried out sectional view after exposure and the development treatment.Fig. 6 a is the sectional view of pixel cell, and Fig. 6 b is the sectional view in the data line zone in PAD zone, and Fig. 6 c is the sectional view of the grid region in PAD zone.Shown in Fig. 6 a-Fig. 6 c, coating one deck photoresist 1000 on doped semiconductor films 300, by two accent (dual tone) mask plate (partly transferring mask plate or tone mask plate) photoresist 1000 is exposed and development treatment, make the photoresist 1000 in data line zone 20, source electrode zone 260 and drain electrode zone 270 have the first thickness H, the photoresist 1000 of pixel electrode area 40 has second thickness h, the described first thickness H is greater than second thickness h, and grid region 10 waits all the other zones not have photoresist.
Fig. 7 a-Fig. 7 c is for having carried out the sectional view behind first etching technics to the structure of Fig. 6 a-Fig. 6 c.Shown in Fig. 7 a-Fig. 7 c, leak metallic film 200 and transparent conductive film 100 by all the other regional doped semiconductor films 300, source that first etching technics etches away outside pixel electrode area 40, data line zone 20, source electrode zone 260 and the drain electrode zone 270 fully, metallic film 200 and transparent conductive film 100 are leaked in the doped semiconductor films 300, the source that promptly etch away the zone that does not cover photoresist 1000.Be specially, pass through SF
6, HCl, Cl
2, gas such as He carries out etching to doped semiconductor films 300 (n+a-Si:H); The etching agent that potpourri by phosphoric acid and nitric acid makes leaks metallic film 200 to the source and carries out etching; By etching agents such as sulfuric acid or superoxide transparent conductive film 100 (ITO or IZO) is carried out etching.As shown in Fig. 7 b, the data line zone in PAD zone has formed the figure of the 3rd electrically conducting transparent portion 43 and data line 2 ' after the etching.Shown in Fig. 7 c, the grid region in PAD zone, only remaining transparency carrier 21. after the etching
In the first above-mentioned etching technics, if when adopting the Mo to carry out dry etching or Mo/Al/Mo to leak metallic film 200 as the source, metallic film 200 is leaked in doped semiconductor films 300 and source can carry out continuous dry etching, and advantage is accurately to control the etching degree.Certainly, also can carry out the scheme that dry etching connects wet etching.This lithographic method can be selected according to the material that metallic film is leaked in the source.
Fig. 8 a-Fig. 8 c is for having carried out cineration technics sectional view afterwards to the photoresist among Fig. 7 a-Fig. 7 c.Shown in Fig. 8 a-Fig. 8 c, removed the photoresist 1000 of the second thickness h degree by the cineration technics of photoresist, expose the doped semiconductor films 300 of pixel electrode area 40, remaining photoresist 1000 also correspondingly attenuation the second thickness h degree.
Fig. 9 a-Fig. 9 c is for having carried out the sectional view behind second etching technics to the structure of Fig. 8 a-Fig. 8 c.Shown in Fig. 9 a-Fig. 9 c, metallic film 200 is leaked in the doped semiconductor films 300, the source that etch away pixel electrode area 40 by second etching technics fully, the first electrically conducting transparent portion 41, the second electrically conducting transparent portion 42 have been formed, pixel electrode 4 ', source electrode 26 and drain electrode 27.
Figure 10 a-Figure 10 c is for having peeled off the sectional view behind the residue photoresist on the structure of Fig. 9 a-Fig. 9 c.
So far, finished the first composition technology by Fig. 5 to Figure 10 c.
Figure 11 a-Figure 11 c is for having deposited the sectional view behind the semiconductive thin film on the structure of Figure 10 a-Figure 10 c.Usually can adopt PECVD or other film build method, deposition layer of semiconductor film 400.After this deposition, in data line zone 20, source electrode zone 260 and drain electrode zone 270, semiconductive thin film 400 is deposited on the doped semiconductor films 300, be deposited on the pixel electrode 40 at pixel electrode area 40 semiconductive thin films 400, (comprise TFT channel region 290 and grid region 10) in other zone, semiconductive thin film 400 is deposited on the transparency carrier 21.
Figure 12 a-Figure 12 c for apply photoresist on the structure of Figure 11 a-Figure 11 c and expose and development treatment after sectional view.Apply photoresist 2000 earlier on semiconductive thin film 400, by common mask plate, photoresist 2000 is exposed and development treatment then, make photoresist 2000 cover on the semiconductor regions 240, other zone does not have the residue photoresist.Shown in Figure 12 a-Figure 12 c, semiconductor regions 240 comprises TFT channel region 290 and all or part of source electrode zone 260 and drain electrode zone 270.
Figure 13 a-Figure 13 c is for carrying out the sectional view behind the 3rd etching technics to the structure of Figure 12 a-Figure 12 c.Shown in Figure 13 a-Figure 13 c, etch away semiconductive thin film 400 and the doped semiconductor films 300 that does not have photoresist to cover by etching agent, formed the figure of semiconductor layer 24 and doped semiconductor 25.Among Figure 13 a, semiconductor layer 24 is formed in the source electrode zone 260 and drain electrode zone 270 of TFT channel region 290 and part.The semiconductor layer 24 that is positioned on the TFT channel region 290 has formed TFT raceway groove 29.Among Figure 13 b, only be left the 3rd electrically conducting transparent portion 43 and data line 2 ' on the transparency carrier 21 in the data line zone in PAD zone; The grid region in PAD zone only remains transparency carrier 21 among Figure 11 c.Then, peeled off the photoresist shown in Figure 12 a.
So far, finished the second composition technology by Figure 11 a to Figure 13 c.The present invention has formed the TFT raceway groove by in the first and second composition technologies.The method that the present invention forms the TFT raceway groove compared with prior art, owing to need not the TFT channel region of etching semiconductor layer, can not produce the problem of overetch, the TFT channel region can very accurately design, the performance of LCD can be protected, and yields improves.
Figure 14 a-Figure 14 c is the sectional view behind deposition insulation film and grid metallic film on the structure of Figure 13 a-Figure 13 c.Shown in Figure 14 a-Figure 14 c, adopt PECVD or other film build method deposition one deck insulation film at whole transparency carrier 21, form gate insulation layer 23, continue deposition grid metallic film 500 then.Insulation film can adopt the single thin film of SiNx, SiOx or SiOxNy, or the multilayer film of above-mentioned material multilayer deposition formation.Grid metallic film 500 can be the single thin film that metals such as molybdenum, aluminium, aluminium neodymium alloy, tungsten, chromium, copper form, and also can be the multilayer film that above metallic multilayer deposition forms.
Figure 15 a-Figure 15 c on the structure of Figure 14 a-Figure 14 c, applied expose behind the photoresist and developing process after sectional view.On grid metallic film 500, apply photoresist 3000 earlier, transfer mask plate that photoresist 3000 is exposed and development treatment by second pair, make the photoresist 3000 of described gate electrode zone 220, grid region 10 and public electrode wire zone (not shown) have the 3rd thickness H ', the data line zone 20 in PAD zone does not have residue photoresist 3000, other regional photoresist 3000 has the 4th thickness h ', described the 3rd thickness H ' is greater than the 4th thickness h '.Gate electrode zone 220 comprises whole TFT channel regions 290 and all or part of source electrode zone 260 and drain electrode zone 270.
Figure 16 a-Figure 16 c is for to carry out the sectional view behind the etching technics the 4th time to the structure of Figure 15 a-Figure 15 c.Shown in Figure 16 a-Figure 16 c, respectively the grid metallic film 500 and the gate insulation layer 23 in the data line zone 20 in PAD zone are carried out etching by the 4th etching technics, expose data line 2 '.
Figure 17 a-Figure 17 c is for carrying out the sectional view of cineration technics behind the photoresist to Figure 16 a-Figure 16 c.Shown in Figure 17 a-Figure 17 c, photoresist 3000 is carried out cineration technics, removes the 4th thickness h ' photoresist, behind cineration technics, except gate electrode zone 220, grid region 10 and public electrode wire zone, other regional grid metallic films 500 expose.
Figure 18 a-Figure 18 c is for carrying out the sectional view behind the 5th etching technics to the structure of Figure 17 a-Figure 17 c.Shown in Figure 18 a-Figure 18 c, etch away the grid metallic film 500 that does not have photoresist 3000 to cover by etching agent, formed gate electrode 22, and the figure of grid line 1 ' and public electrode wire 5 '.Peel off remaining photoresist then.
So far, finished the 3rd composition technology by Figure 14 a to Figure 18 c.
Figure 19 a-Figure 19 c is the sectional view behind deposition second transparent conductive film on the structure in Figure 18 a-Figure 18 c.Shown in Figure 19 a-Figure 19 c, having deposited second transparent conductive film, 600, the second transparent conductive films 600 can be ITO or IZO etc.
Figure 20 a-Figure 20 c exposes behind the photoresist and development treatment sectional view afterwards for having applied on the structure to Figure 19 a-Figure 19 c.Shown in Figure 20 a-Figure 20 c, apply one deck photoresist 4000, by common mask plate photoresist 4000 exposure and development treatment have been carried out, make residue one deck photoresist 4000 on the grid region in the data line zone in public electrode wire zone, public electrode zone, PAD zone and PAD zone, the no photoresist covering in other zone.
Figure 21 a-Figure 21 c is for having carried out the sectional view behind the 6th etching technics to the structure among Figure 20 a-Figure 20 c.Shown in Figure 20 a-Figure 20 c, to the zone outside the grid region in the data line zone in public electrode wire zone, public electrode zone, PAD zone and PAD zone, promptly second transparency conducting layer 600 in the zone that is not covered by photoresist has carried out etching, has formed public electrode 50 '.The figure of the 4th electrically conducting transparent portion 51 and the 5th electrically conducting transparent portion 52, and public electrode and public electrode wire formed be connected.The public electrode zone is most of overlapping with pixel electrode area 40, and the public electrode zone has the figure of slit.
So far, finished the 4th composition technology, obtained FFS type TFT-LCD array base palte of the present invention by Figure 19 a to Figure 21 c.
FFS type TFT-LCD array base palte of the present invention, compare the method for existing 6 times or 5 times composition technology manufacturing array substrates, can adopt the preparation of 4 composition technologies to finish, advantage such as have that processing step is simplified, the process time is short, production efficiency is high and production cost is low.
It should be noted that at last: above embodiment is only in order to technical scheme of the present invention to be described but not limit it, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, and these modifications or be equal to replacement and also can not make amended technical scheme break away from the spirit and scope of technical solution of the present invention.
Claims (11)
1. the manufacture method of a FFS type TFT-LCD array base palte, described array base palte comprises public electrode zone, public electrode wire zone, gate electrode zone, grid region, data line zone, semiconductor layer zone, the grid region in source electrode zone, drain electrode zone, pixel electrode area PAD zone and the data line zone in PAD zone, it is characterized in that, comprising:
Step 1: on transparency carrier, deposit first transparent conductive film, source leakage metallic film and doped semiconductor films successively, comprise source electrode, drain electrode, data line and pattern of pixel electrodes by the formation of the first composition technology;
Step 2: the deposited semiconductor film forms the figure that comprises doping semiconductor layer, TFT raceway groove and semiconductor layer by the second composition technology;
Step 3: deposit insulation film and grid metallic film, form the figure that comprises connecting hole, grid line, gate electrode and public electrode wire by the 3rd composition technology;
Step 4, deposition second transparent conductive film form the figure that comprises public electrode by the 4th composition technology.
2. according to the manufacture method of the FFS type TFT-LCD array base palte of claim 1, it is characterized in that described step 1 specifically comprises:
Transparency carrier is provided;
On described transparency carrier, deposit first transparent conductive film, source leakage metallic film and doped semiconductor films successively;
On doped semiconductor films, apply photoresist;
Transfer mask plate that described photoresist is exposed and development treatment by first pair, make the photoresist in described data line zone, source electrode zone and drain electrode zone have first thickness, the photoresist of described pixel electrode area has second thickness, described first thickness is greater than second thickness, and there is not photoresist in all the other zones;
Etch away described all the other regional doped semiconductor films, source leakage metallic film and transparent conductive film fully by first etching technics;
Remove the photoresist of second thickness by cineration technics, expose the doped semiconductor films of described pixel electrode area;
Metallic film is leaked in the doped semiconductor films and the source that etch away described pixel electrode area by second etching technics fully;
Peel off the residue photoresist.
3. according to the manufacture method of the FFS type TFT-LCD array base palte of claim 1, it is characterized in that described step 2 specifically comprises:
The deposited semiconductor film;
On described semiconductive thin film, apply photoresist;
By mask plate described photoresist is exposed and development treatment, only keep photoresist in described semiconductor layer zone;
Etch away the semiconductive thin film that exposes by the 3rd etching technics;
Peel off the residue photoresist.
4. according to the manufacture method of the FFS type TFT-LCD array base palte of claim 1, it is characterized in that described step 3 specifically comprises:
Deposition insulation film and grid metallic film;
On described grid metallic film, apply photoresist;
Transfer mask plate that photoresist is exposed and development treatment by second pair, make the photoresist in described gate electrode zone, grid region and public electrode wire zone have the 3rd thickness, the data line zone in PAD zone does not have the residue photoresist, other regional photoresist has the 4th thickness, and described the 3rd thickness is greater than the 4th thickness;
Respectively the grid metallic film and the gate insulation layer in the data line zone in PAD zone are carried out etching by the 4th etching technics;
Photoresist is carried out cineration technics, remove the photoresist of the 4th thickness, behind cineration technics, except gate electrode zone, grid region and public electrode wire zone, other regional grid metallic films expose;
By the 5th etching technics, etch away the grid metallic film that exposes;
Peel off the residue photoresist.
5. according to the manufacture method of the FFS type TFT-LCD array base palte of claim 1, it is characterized in that described step 4 specifically comprises:
Deposit second transparent conductive film;
On described second transparent conductive film, apply photoresist;
By common mask plate photoresist has been carried out exposure and development treatment, made to remain photoresist, the no photoresist covering in other zone on the grid region in the data line zone in public electrode wire zone, public electrode zone, PAD zone and PAD zone;
Etch away described second transparent conductive film in described other zone fully by the 6th etching technics;
Peel off the residue photoresist.
6. the manufacture method of FFS type TFT-LCD array base palte according to claim 1 is characterized in that described insulation film is the single thin film of SiNx, SiOx or SiOxNy, or the multilayer film of these material multilayer deposition formation.
7. the manufacture method of FFS type TFT-LCD array base palte according to claim 1, it is characterized in that, metallic film is leaked in described source or the grid metallic film is the single thin film of molybdenum, aluminium, aluminium neodymium alloy, tungsten, chromium, copper formation, or is the multilayer film that above metallic multilayer deposition forms.
8. the manufacture method of FFS type TFT-LCD array base palte according to claim 2 is characterized in that, the etching agent that the potpourri by phosphoric acid and nitric acid makes leaks metallic film to the source and carries out etching;
9. the manufacture method of FFS type TFT-LCD array base palte according to claim 2 is characterized in that, by sulfuric acid or superoxide first transparent conductive film is carried out etching.
10. the manufacture method of TFT-LCD array base palte according to claim 7 is characterized in that, when described source leakage metallic film is Mo or Mo/Al/Mo, described doped semiconductor films and described source leakage metallic film is carried out twice dry etching continuously.
11. TFT-LCD array base palte that obtains by manufacture method as arbitrary described FFS type TFT-LCD array base palte among the claim 1-10.
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| CN2009100898292A CN101963727B (en) | 2009-07-24 | 2009-07-24 | FFS (Fringe Field Switching) type TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array substrate and manufacturing method thereof |
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| CN2009100898292A CN101963727B (en) | 2009-07-24 | 2009-07-24 | FFS (Fringe Field Switching) type TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array substrate and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2015004903A (en) * | 2013-06-24 | 2015-01-08 | 三菱電機株式会社 | Active matrix substrate and manufacturing method of the same |
| WO2019210850A1 (en) * | 2018-05-02 | 2019-11-07 | 京东方科技集团股份有限公司 | Pixel structure and manufacturing method therefor, array substrate, and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20000027776A (en) * | 1998-10-29 | 2000-05-15 | 김영환 | Method for manufacturing lcd |
| JP3420135B2 (en) * | 1999-10-26 | 2003-06-23 | 日本電気株式会社 | Active matrix substrate manufacturing method |
| KR101421166B1 (en) * | 2007-03-02 | 2014-07-18 | 엘지디스플레이 주식회사 | Method of fabricating liquid crystal display device |
| JP2008310210A (en) * | 2007-06-18 | 2008-12-25 | Epson Imaging Devices Corp | In-plane switching display device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2015004903A (en) * | 2013-06-24 | 2015-01-08 | 三菱電機株式会社 | Active matrix substrate and manufacturing method of the same |
| WO2019210850A1 (en) * | 2018-05-02 | 2019-11-07 | 京东方科技集团股份有限公司 | Pixel structure and manufacturing method therefor, array substrate, and display device |
| US11581339B2 (en) | 2018-05-02 | 2023-02-14 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Pixel structure and manufacturing method therefor, array substrate, and display device |
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