CN1019628B - Digital binary to ternary converter circuit - Google Patents
Digital binary to ternary converter circuitInfo
- Publication number
- CN1019628B CN1019628B CN 90108463 CN90108463A CN1019628B CN 1019628 B CN1019628 B CN 1019628B CN 90108463 CN90108463 CN 90108463 CN 90108463 A CN90108463 A CN 90108463A CN 1019628 B CN1019628 B CN 1019628B
- Authority
- CN
- China
- Prior art keywords
- signal
- ternary
- mentioned
- binary
- pcm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/0823—Multistate logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/16—Conversion to or from representation by pulses the pulses having three levels
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
- H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Dc Digital Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
- Logic Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
A digital binary to ternary converter circuit e.g. for the low frequency output of a PCM multiplexer/demultiplexer is described. A three level output signal is provided by inverting one of a pair of binary inputs via transistor TR1. A pair of transistor switches (TR2, TR3) biased almost to saturation provide high speed conversion of the inverted and non-inverted binary input, to an output ternary signal.
Description
The present invention relates to a kind of PCM(pulse code modulation) the multiplex communication transmission system, in detail, relate to a kind of can be many circuit that digital binary signal are combined into corresponding ternary signal.The invention still further relates to one, to combine the foregoing circuit multichannel compound.Signal separator.
Multichannel PCM system is widely used in message transmission, as between telephone exchange.In exemplary systems, a plurality of low frequencies (as megabit per second) PCM signal carries out the compound back of multichannel to be transmitted as a high-frequency signal.Give an example, the PCM signal of 16 2 megabit per seconds carries out the signal that multichannel can form one 34 megabit per second after compound.2 megabit per seconds that wherein have more are for insertion frame alignment word in signal, thereby guarantee that signal correctly separates in follow-up Signal Separation operation.Also may comprise a plurality of service bits in the above-mentioned multichannel reset signal.Also comprise in such system from a distant station and receive the signal of 34,000,000 frame/seconds and the device that many signals that it is separated into 2 megabit per seconds is carried out local transmission.
Typical PCM multichannel compound/demultiplexer in, what the high and low frequency signal that mentions above adopted all is the ternary form.But for the convenience on the signal processing, these are combined into separated signal and must be handled with binary form.Like this, at the output of low frequency and high-frequency circuit, these binary signals must be changed back corresponding ternary signal again.This especially low frequency end one side at signal multichannel recombiner/demultiplexer can have problems, because the there has a large amount of ternary output signal etc. to be converted.Select for use ternary signal to be because it is lower to the requirement of frequency band, and can reduce the loss effect on the long transmission line; Then must be handled with binary mode by compound or separated signal, doing like this is to get up conveniently for signal processing.
Conventional binary to ternary converter circuit all needs a converter that links to each other with the binary system PCM signal of input.When a large amount of PCM signals was handled together, this just required a complexity and quite expensive structure.
Purpose of the present invention is eliminated exactly and is overcome above-mentioned shortcoming in other words.
Comprise according to digital binary to ternary converter circuit provided by the invention: first inverting input and second non-inverting input, second input imported first and second binary digital signals in use respectively; First, second transistor that links to each other with above-mentioned first, second input respectively, each transistor all is biased to like this, be that input end is not on-state when having binary zero, be logical state when there is binary one in input end, thus produce with the above-mentioned corresponding direct impulse of first binary signal and with the above-mentioned corresponding reverse impulse of second binary signal; And thereby above-mentioned forward and reverse impulse made up the device that a trit word output signal is provided.
The present invention also provide a kind of pulse code modulation PCM multiplexed/demultiplexing circuit, comprise; Receive the device of high frequency ternary signal; From above-mentioned high-frequency signal, take out the device of a plurality of low frequency ternary signals; Be used to receive the device of a plurality of low frequency ternary signals; Be used to draw a device, and before the compound or Signal Separation ternary signal that receives converted to the input converter of corresponding binary signal in multichannel and after the compound or Signal Separation binary signal is converted to the output translator of corresponding ternary signal in multichannel corresponding to the high frequency ternary signal of above-mentioned a plurality of low frequency signals that receive; It is characterized in that: each above-mentioned output translator comprises the one the second two inputs, and each input is sent into a corresponding binary system PCM signal in use; One in inverter and the above-mentioned input links to each other; First and second transistor switches link to each other with above-mentioned first and second inputs respectively, are used to produce respectively and above-mentioned corresponding forward of the first and second PCM signals and reverse impulse stream; And be provided with and above-mentioned forward and reverse impulse stream made up and form the device of a corresponding ternary digital output PCM signal.
Below in conjunction with accompanying drawing one embodiment of the present of invention are described.
Fig. 1. be PCM multichannel compound/the quite abstract schematic diagram of demultiplexing circuit.
Fig. 2. show circuit among Fig. 1 through the compound output/pattern of the input of multichannel.
Fig. 3. be multichannel among Fig. 1 compound/binary to ternary converter circuit that uses in the demultiplexing circuit.
With reference to Fig. 1, the multichannel among the figure is compound/and demultiplexing circuit is configured to receive the signal of 34 megabit per seconds and the corresponding signal that it is separated into many 2 megabit per seconds is transmitted again from a distant station.This circuit also can receive the signal of a plurality of 2 megabit per seconds and such signal is combined into the signal that is up to 34 megabit per seconds passes to first journey station.This multichannel is compound/and it is PCM ternary form that the input and output signal of demultiplexing circuit adopts, and reason is that this form is lower than the transmission signals of corresponding binary signal.For for purpose of brevity, compound this process of multichannel is not described in detail, because it is the inverse process of the Signal Separation process that describes below generally speaking.
Illustrated among Fig. 2 input (or output) 34 megabit per seconds signal a word or be a frame.The frame that 48 megabit per seconds that a frame alignment word leads are arranged in the frame of each 34 megabit per second.The front of the frame of each 8 megabit per second has corresponding 8 megabit per second frame alignment word again, combine in the frame of each 8 megabit per second through multichannel compound with 4 the 2 corresponding trits of megabit per second signal.It should be noted that 8 megabit per seconds are not definite signal bit rates, because also must stay surplus inserts 8 megabit per seconds in signal alignment word.Can also comprise some management data positions in the signal.Not shown for the sake of brevity these data bit of Fig. 2.
See Fig. 1 again, the ternary PCM input signal of sending into 34 megabit per seconds of circuit input end I/P converts corresponding binary signal to by a ternary to binary conversion circuit 21 earlier, this binary signal is resolved into the signal of 8 megabit per seconds earlier by demultiplexer 22, resolved into the signal of 2 megabit per seconds again by demultiplexer 23.The binary signal of these 2 megabit per seconds converts corresponding ternary signal to by binary to ternary transducer 24 again and transmits.
The binary to ternary converter circuit that uses in multichannel recombiner/demultiplexer among Fig. 1 shown in Figure 3.This circuit has first, second two inputs, and each input all receives a binary signal from a HDB3 circuit (not shown).One of them input (IP2) links to each other with an inverter (TR1), and like this, this circuit input end just can play the effect of inverting input.Another circuit input end is nonphase-inverting.These two not anti-phase links to each other with TR3 with transistor switch TR2 respectively with inverting input, and each among these two transistor T R2 and the TR3 is by corresponding resistance R 1, R2, diode D
1, D
2, D
3, D
4Setovered, made conducting when binary one is sent into circuit input end, not conducting when binary zero is added on the input.Like this, in response to the binary signal that is added on the circuit input end, transistor T R2 will produce corresponding postiive gain pulse, and transistor T R3 will produce corresponding negative gain pulse.In typical case, transistor T R2 and TR3 are biased to like this, i.e. they will be in saturation condition during conducting.It should be noted that between the data bit of these two PCM binary signals and can not overlap.Next, the collector electrode of two transistor T R2 and TR3 output added to give be combined to form one, oppositely and the ternary stream of pulsess of 03 kinds of data bit compositions, lead to into capacitor C again and export this stream of pulses by forward.Thereby the value of collector resistance R3 and R4 will be adjusted the balance of guaranteeing between forward and the reverse impulse.Diode D5 and D6 can provide voltage protection for circuit output end.
In circuit shown in Figure 3, can also load onto the corresponding resistance R 5 of impedance of an impedance and inverted transistors TR1, thereby the coupling between the circuit input end is provided.
Now, through after the correct adjustment, the circuit among Fig. 3 just can carry out binary to ternary have been changed at the high frequency output of PCM multiplexer/demultiplexer.Should be noted that though top description is carried out according to the PCM signal, the technology among the present invention is not limit this specific transmission mode, is applicable to digital signals format yet.
Claims (2)
1, a kind of pulse code modulation (pcm) multiplexed/demultiplexing circuit, comprising: the device that receives the high frequency ternary signal; From above-mentioned high-frequency signal, take out the device of a plurality of low frequency ternary signals; Be used to receive the device of a plurality of low frequency ternary signals; Be used to draw a device, and before the compound or Signal Separation ternary signal that receives converted to the input converter of corresponding binary signal in multichannel and after the compound or Signal Separation binary signal is converted to the output translator of corresponding ternary signal in multichannel corresponding to the high frequency ternary signal of above-mentioned a plurality of low frequency signals that receive; It is characterized in that: each above-mentioned output translator comprises the first and second two inputs, and each input is sent into a corresponding binary system PCM signal in use; One in inverter and the above-mentioned input links to each other; First and second transistor switches link to each other with above-mentioned first and second inputs respectively, be used to produce respectively and above-mentioned corresponding forward of the first and second PCM signals and reverse impulse stream, and above-mentioned forward and reverse impulse stream do not made up and form the device of a corresponding ternary digital output PCM signal.
2, multichannel as claimed in claim 1 compound/signal multiplexing circuit, it is characterized in that: the first and second above-mentioned transistors are biased to like this, are saturation condition when promptly being in conducting state.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8923577A GB2237482B (en) | 1989-10-19 | 1989-10-19 | Digital binary to ternary converter circuit |
| GB8923577.4 | 1989-10-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1051109A CN1051109A (en) | 1991-05-01 |
| CN1019628B true CN1019628B (en) | 1992-12-23 |
Family
ID=10664838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 90108463 Expired CN1019628B (en) | 1989-10-19 | 1990-10-17 | Digital binary to ternary converter circuit |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN1019628B (en) |
| ES (1) | ES2024925A6 (en) |
| GB (1) | GB2237482B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6545213B2 (en) * | 2017-03-17 | 2019-07-17 | アンリツ株式会社 | Ternary signal generator and ternary signal generation method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1023621A (en) * | 1962-11-15 | 1966-03-23 | British Telecomm Res Ltd | Improvements in or relating to electrical signalling systems |
| US3588330A (en) * | 1967-12-21 | 1971-06-28 | John H Clark | Facsimile signal modification reducing the information channel bandwidth |
| JPS63222519A (en) * | 1987-03-12 | 1988-09-16 | Fujitsu Ltd | B8zs/b6zs coding circuit |
-
1989
- 1989-10-19 GB GB8923577A patent/GB2237482B/en not_active Expired - Fee Related
-
1990
- 1990-10-17 CN CN 90108463 patent/CN1019628B/en not_active Expired
- 1990-10-19 ES ES9002647A patent/ES2024925A6/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| GB8923577D0 (en) | 1989-12-06 |
| CN1051109A (en) | 1991-05-01 |
| ES2024925A6 (en) | 1992-03-01 |
| GB2237482A (en) | 1991-05-01 |
| GB2237482B (en) | 1993-11-17 |
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| C06 | Publication | ||
| PB01 | Publication | ||
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| C13 | Decision | ||
| GR02 | Examined patent application | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C53 | Correction of patent for invention or patent application | ||
| CB02 | Change of applicant information |
Address after: Quebec Applicant after: Northern Electric Communication Co., Ltd. Address before: London, England Applicant before: Standard Telephone Cables Public Ltd. Co. |
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| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: STANDARD TELEPHONES AND CABLES PUBLIC CO., LTD. TO: NORTHERN TELECOM LTD. |
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| C15 | Extension of patent right duration from 15 to 20 years for appl. with date before 31.12.1992 and still valid on 11.12.2001 (patent law change 1993) | ||
| OR01 | Other related matters | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |