CN101957744A - Hardware multithreading control method for microprocessor and device thereof - Google Patents

Abstract

A hardware multi-thread control method and device for a microprocessor relate to the field of microprocessor architecture. The control method proposed by the present invention includes the following steps: multi-thread instruction fetching, multi-thread decoding, multi-thread execution, multi-thread memory access, and multi-thread write-back. The simulation device proposed by the present invention includes: a hardware multi-thread instruction fetching device, a hardware multi-thread decoding device, a hardware multi-thread execution device, a hardware multi-thread memory access device, a hardware multi-thread write-back device, a hardware multi-thread Thread register set, a multi-thread control device. In addition, the present invention is aimed at software multi-thread programs, which can be executed by processor hardware multi-threads, effectively hides memory access delays during execution, omits the preservation and restoration of thread-related information during thread switching, and reduces the overhead of thread switching; Pipeline technology is adopted, so that n threads can be executed in parallel within the original execution time of one thread; through hardware multi-threading, the risk of data correlation brought by deep pipelining is effectively avoided, the design complexity of the system is reduced, and the hardware is improved. system performance.

Description

A hardware multi-thread control method and device for a microprocessor

Technical field:

The invention relates to the field of microprocessor architecture, in particular to a hardware multi-thread control method and a device thereof.

background knowledge:

In order to further improve the performance of microprocessors, a variety of novel architectures have been proposed, such as multi-core, multi-thread, stream processing, PIM, reconfigurable, polymorphic, etc. These new architectures propose solutions to the problems in the development of microprocessors from different angles. Affected by the characteristics of software programs and the physical limitations of hardware technology, the development of future architecture is no longer able to obtain a substantial improvement in system performance just by increasing the main frequency. The development trend of architecture technology is obvious. Multi-thread and multi-core have become two key technical directions. In various fields, processors with multi-thread or multi-core features emerge in an endless stream. Pipeline technology is an important feature that distinguishes RISC processors from CISC processors. The use of deep pipeline technology will greatly reduce the performance of the pipeline during instruction correlation and instruction jump. Based on the RISC architecture, the present invention adopts deep pipeline technology to realize multi-hardware thread execution, effectively avoids the performance reduction caused by instruction correlation, and improves the performance of the microprocessor through multi-threading.

Patent published on July 16, 2008: CN101221493A, title: "Multithreaded Execution in Parallel Processors", inventor: D. Bernstein, etc. The invention discloses a parallel hardware multi-thread processor. The processor contains a general-purpose processor that coordinates system functions and supports multiple hardware threads and multiple microengines. The processor also includes a memory control system having a first memory controller and a second memory controller, the first memory controller classifying memory accesses according to whether the memory access is directed to an even bank or an odd bank, and a second memory controller The controller optimizes memory accesses based on whether the memory access is a read or write access.

Patent published on 2007-8-22: CN101021801, title: "Multiple data transmission method based on message queue between multiple pipeline processes", inventor: Xue Qingtong, etc. This patent discloses a method for mass data transmission based on message queues between pipelined multi-processes. In the business processing flow of billing products, the sequence of a bill is at least divided into formatting, ordering (or sorting), weight sorting, price approval, and warehousing. The billing method adopts single-step and overall submission. The combined mechanism is configured to automatically assign tasks in different environments using different message queue types, load balance management, distribute bills to different message queues, and deploy in a custom way according to business logic. The billing system realized by the method of the invention transmits a large amount of bill data between processes, all through the message queue, and the processing process can be realized in the memory without system IO overhead, and the speed is greatly improved. The processing efficiency of the system using the pipeline parallel processing technology scheme based on the message queue is obviously improved. The processing speed ranks among the best among billing manufacturers at home and abroad.

Patent published on January 25, 2006: CN1725176, title: "Method and Device for Multithreaded Pipeline Instruction Decoder", inventor: J·P·Douglas, etc. This patent discloses a method for a multi-threaded pipeline instruction decoder. Using the multi-threaded transmission instruction decoder to time, clear and delay the decoding pipeline instructions in a multi-threaded machine can obtain the best performance and minimum power consumption. An image pipeline image holds thread-identified instruction decode pipeline and instruction decoder valid instruction bits per pipeline stage. Thread ID and valid bits are used to control the timing, flushing, and latency of each pipeline stage in the instruction decoder. A thread instruction can be flushed without conflicting with other thread instructions in the decode pipeline, and in some cases, a thread's instruction can be delayed without conflicting with other thread instructions in the decode pipeline. In the present invention, pipeline stages are only clocked when active instructions need to advance in order to preserve power and minimize latency.

Patent published on September 15, 1999: CN1228557, title: "Multithreaded Instruction Level Parallel Technology for Computer Processors", inventor: Liu Yin, etc. This patent discloses a computer processor multi-thread instruction level parallel technology. The invention relates to a technology applicable to computer processors: multi-thread instruction level parallel technology. The computer processor using this technology can fetch instructions from the threads in the execution state in turn, so that several instructions executed in parallel in the computer processor come from different threads, so there is no "inter-instruction dependency problem" between these instructions. ".

Patent published on June 6, 2007: CN1975663, title: "A device with asymmetric hardware multi-thread support for different threads", inventor: David A. Carat. The patent provides an asymmetric hardware support for a specific class of threads. Preferably, the specific class of threads is a high priority I/O bound thread. In a first aspect, a multithreaded processor includes N sets of registers to support concurrent execution of N threads. At least one register bank is dedicated to a particular class of thread and cannot be used by other threads, even when idle. In a second aspect, a particular class of threads can only fill a limited portion of the cache memory in order to reduce flushing of the cache that might otherwise occur.

Patent published on December 14, 2005: CN1707694, title: "Memory Controller for Multithreaded Pipeline Bus System", inventor: Xu Yunfan, etc. This patent discloses a storage controller for a multi-thread pipeline bus system. In the storage control method of the multi-thread pipeline system, addresses of multiple banks to be accessed in the storage unit are sequentially received from the host. For each of the plurality of banks, it is determined whether or not an address corresponding to the bank is input from the host when a read/write command is output to the memory cell. When the result of the determination indicates that the address corresponding to the bank has been input, a read/write command including any one of open page information and automatic precharge information is output to the memory cell.

Patent published on 1999-10-20: CN1232219, title: "Pipeline Multi-processor System", inventor: Yoshio Koike. This patent discloses a pipelined multiprocessor system, which includes a set of processor units, a set of buffers and a debugging unit. The processor unit is used for pipeline processing data; the buffer holds the input data and the processing results of each processor unit; the buffer and processor unit are sequentially cascaded between data input and output, and the debug unit is used to optionally The processing results of each processor unit are output externally for monitoring during debugging.

Invention content:

The object of the present invention is to design a hardware multi-thread control method for a microprocessor and a corresponding hardware multi-thread control device for the execution of software multi-thread programs.

A hardware multi-thread control method for a microprocessor, characterized in that the method comprises the following steps:

1) The multi-thread instruction fetching step is used to read the instructions of each thread and generate the instruction address of each thread. Specifically, it includes multi-thread instruction address control, multi-thread instruction address cache, and multi-thread instruction fetch.

a) Multi-thread instruction address control, used to generate the instruction address of each thread, when a certain thread is blocked, only the thread instruction address is blocked, and other thread instruction addresses are updated normally;

b) multi-thread instruction address cache, used to store the instruction addresses of n threads;

c) Multi-thread instruction fetch, which is used to symmetrically divide the instruction fetch logic into n-level pipelines, and take out the software thread instructions corresponding to n hardware threads. When a thread is blocked, only the thread fetch is blocked, and other threads fetch instructions normal operation.

2) The multi-thread decoding step is used to decode the instructions of each hardware thread, and prepare the register data required by the multi-thread execution step. It specifically includes multi-threaded decoding, multi-threaded register operand preparation, and data bypass control of decoding components:

a) Multi-thread decoding, which is used to symmetrically divide the decoding logic into n-level pipelines, and complete multi-thread initialization special instruction decoding and conventional instruction decoding. When a certain thread is blocked, only the instruction decoding of this thread is blocked, and the instruction decoding of other threads runs normally. The multi-thread initialization special instruction includes: an opcode field for identifying the instruction, an operand field for operating the destination operand, and an operand field for operating the source operand;

b) Multi-thread register operand preparation, used to generate the address of the register to be read, and read the required operand of the instruction from n register groups;

c) Data bypass control of the decoding component, used to provide the data of the data bypass to a certain pipeline stage of instruction decoding;

3) The multi-thread execution step is used to execute instructions of each thread. Specifically, it includes execution of special instructions for multi-thread initialization, thread number cache, data bypass control of execution components, and execution of multi-thread conventional instructions:

a) execution of multi-thread initialization special instructions for generating a new hardware thread number, and the new hardware thread number corresponds to the software thread executed by the hardware thread;

b) thread number cache, which is used to cache the new hardware thread number generated by the execution of the multi-thread initialization special instruction, so that the position of a certain new hardware thread number generated in the thread number register sequence is the same as that of the hardware thread in the instruction address register sequence , the multi-threaded register sequence of the fetching part, the multi-threaded register sequence of the decoding part, the multi-threaded register sequence of the execution part, the multi-threaded register sequence of the accessing part, and the multi-threaded register sequence of the write-back part are consistent in position;

c) Execution component data bypass control, used to provide data bypassed to a certain pipeline stage of instruction execution;

d) Multi-threaded regular instruction execution, used to symmetrically divide the execution logic into n-level pipelines, and complete the regular instruction execution of n hardware threads. When a thread is blocked, only the thread instruction execution is blocked, and other thread instructions execute normally. .

4) The multi-thread memory access step is used to symmetrically divide the memory access logic into n-level pipelines, write the execution results of each thread into the memory or read the data required by the thread from the memory, and when a thread is blocked, only block This thread data access, other thread data access works normally.

5) The multi-threaded write-back step is used to symmetrically divide the write-back logic into n-level pipelines, and write the execution results of each thread back to the corresponding register group. When a certain thread is blocked, only the thread data write-back is blocked, and other Thread data writeback works normally. Specifically, it includes multi-thread write-back data control and multi-thread write-back register address control:

a) Multi-threaded write-back data control, used for preparation and output of register data to be written back;

b) Multi-threaded write-back register address control, used for preparing and outputting the address of the register to be written back.

A hardware multi-thread control device for a microprocessor, the device supports parallel execution of n hardware threads by adopting pipeline technology. It is characterized in that it includes the following components: hardware multi-thread instruction fetching device, hardware multi-thread decoding device, hardware multi-thread execution device, hardware multi-thread memory access device, hardware multi-thread write-back device, hardware multi-thread register group and multi-thread control device.

1) The hardware multi-thread instruction fetching device includes: an instruction address control device, which is used to generate the instruction address of each thread; the instruction address register sequence, which is used to store the instruction addresses of n threads; the instruction fetch part multi-thread register sequence, used To temporarily store the intermediate results of the n-level pipeline of the instruction fetch logic, each stage of register corresponds to the partial instruction fetch logic output of a hardware thread;

2) the hardware multi-thread decoding device includes: a decoding part multi-thread register sequence, which is used to temporarily store the intermediate results of the n-level pipeline of decoding logic, and each level of register corresponds to the partial decoding logic output of a hardware thread; Road register sequence, used to store the intermediate execution results of the first two instructions of each thread;

3) The hardware multi-thread execution device includes: a multi-thread initialization special instruction execution device, which is used to generate a hardware thread number, which corresponds to the software thread executed by the hardware thread; a thread number register sequence, which is used for buffer generation The hardware thread number; the multi-threaded register sequence of the execution unit is used to temporarily store the intermediate results of the execution logic n-level pipeline, and each level of register corresponds to the output of a part of the execution logic of a hardware thread; the data bypass register sequence is used to store each The intermediate execution results of the first two instructions of the thread;

4) The hardware multi-threaded memory access device includes: a multi-threaded register sequence of the memory access part, which is used to temporarily store the intermediate results of the n-level pipeline of the memory access logic, and each level of register corresponds to the partial memory access logic output of a hardware thread;

5) The hardware multi-thread write-back device includes: a write-back component multi-thread register sequence, which is used to temporarily store the intermediate results of the write-back logic n-level pipeline, and each level of register corresponds to a part of the write-back logic output of a hardware thread;

6) The hardware multi-thread register group includes: a decoder, which decodes according to the register control signal generated by the multi-thread control device and the address signal generated by the hardware multi-thread decoding device or the hardware multi-thread write-back device, and outputs the current Register group enable signal of thread and register address of current operation; multiplexer, according to the register control signal generated by the multi-thread control device, selects the data of the register group of the current thread and outputs it; n register groups , respectively provided to n threads, each independently, the written data comes from the output data of the hardware multi-threaded write-back device, and the read data is sent to the hardware multi-threaded decoding device;

7) The multi-thread control device is used to generate the following control signals: generate an instruction fetch control signal, output to the hardware multi-thread instruction fetch device, generate a decoding control signal, and output to the hardware multi-thread decoding device, Generate an execution control signal, output it to the hardware multi-thread execution device, generate a memory access control signal, output it to the hardware multi-thread memory access device, generate a write-back control signal, output it to the hardware multi-thread write-back device, and generate The register control signal is output to the hardware multi-thread register set.

An advantage of the present invention is that for software multi-thread programs, processor hardware multi-threads can be used to execute, effectively hide memory access delays during execution, save and restore thread-related information when thread switching is omitted, and reduce the cost of thread switching. overhead, thereby improving the execution efficiency of the program and reducing power consumption.

Another advantage of the present invention is that through the use of pipeline technology, n threads can be executed in parallel within the original execution time of one thread, which improves the execution efficiency of the program from the hardware.

Another advantage of the present invention is that the risk of data correlation brought by deep pipelining is effectively avoided through hardware multithreading, the design complexity of the system is reduced, and the execution efficiency of the system is improved.

Description of drawings

Figure 1 is a typical MIPS processor pipeline architecture diagram.

Fig. 2 is a diagram of a hardware multi-thread control device for a microprocessor.

Fig. 3 is a diagram of a hardware multithread instruction fetching device in a hardware multithread device.

Fig. 4 is a diagram of a hardware multi-thread decoding device in a hardware multi-thread device.

Fig. 5 is a diagram of hardware multi-thread execution devices in a hardware multi-thread device.

Fig. 6 is a diagram of a hardware multithread memory access device in a hardware multithread device.

FIG. 7 is a device diagram of hardware multi-thread write-back in a hardware multi-thread device.

FIG. 8 is an explanatory diagram of a hardware multithreading register set in a hardware multithreading device.

Fig. 9 is the encoding format of special instructions for multi-thread initialization.

Fig. 10 is a step diagram of a hardware multi-thread control method for a microprocessor.

Figure 11 is a hardware multi-thread pipeline split and clock diagram.

FIG. 12 is a schematic diagram of hardware multi-thread execution timing.

Detailed ways

The implementation of the present invention will be described in detail below in conjunction with the accompanying drawings.

Figure 1 shows a typical MIPS processor pipeline architecture diagram. The execution of an instruction is divided into five levels of pipelines: fetch (IF), decode (ID), execute (EX), memory access (MEM) and write back (WB). This patent is designed on the basis of this pipeline. Adopt deepened pipeline series to support hardware multi-threaded execution;

Fig. 2 is a schematic diagram of the overall structure of the hardware multi-thread control device used in the microprocessor according to the present invention. Including hardware multi-thread instruction fetching device 201, hardware multi-thread decoding device 202, hardware multi-thread execution device 203, hardware multi-thread access device 204, hardware multi-thread write-back device 205, hardware multi-thread register group 206, multi-thread control Device 207 . Each device supports n hardware threads to execute in parallel, and each device is synchronized.

The hardware multithread instruction fetching device 201, according to the instruction fetch control signal output by the multithread control device 207, completes the update operation of n hardware thread instruction addresses, realizes the storage of instruction addresses, and completes the instruction fetch operation to n hardware threads, and The instruction is output to the hardware multi-thread decoding device 202; the hardware multi-thread decoding device 202, according to the instructions of the n threads output by the hardware multi-thread instruction fetching device 201 and the decoding control signal generated by the multi-thread control device 207, completes n The decoding operation of the hardware thread outputs the operation control information and data information to be operated to the hardware multi-thread execution device 203; the hardware multi-thread execution device 203, according to the operation control information and data information output by the hardware multi-thread decoding device 202, The execution control signal generated by the multi-thread control device 207 completes the instruction execution of n threads, and outputs the data information of the execution result to the hardware multi-thread memory access device 204; the hardware multi-thread memory access device 204 generates according to the multi-thread control device 207 The memory access control signal of n hardware threads is completed, and the data information from the multi-thread execution device 203 is output to the hardware multi-thread write-back device 205; the hardware multi-thread write-back device 205, according to the multi-thread control device The write-back control signal generated by 207 outputs the data information to be written back and the current register address to be written back to the hardware multi-thread register group 206; the hardware multi-thread register group 206, according to the register control signal output by the multi-thread control device 207 Cooperate with the hardware multi-thread decoding device 202 and the hardware multi-thread write-back device 205 to complete the register group read and write operations of n hardware threads; the multi-thread control device 207 controls the execution of each device of the entire hardware multi-thread device, specifically producing the following Control signal: generate instruction fetch control signal and output to hardware multi-thread instruction fetch device 201, generate decoding control signal and output to hardware multi-thread decoding device 202, generate execution control signal and output to hardware multi-thread execution device 203, generate memory access control The signal is output to the hardware multi-thread memory access device 204 , the write-back control signal is generated and output to the hardware multi-thread write-back device 205 , and the register control signal is generated and output to the hardware multi-thread register group 206 .

FIG. 3 is a structural diagram of a hardware multithread instruction fetching device 201 in conjunction with the overall structural diagram of the hardware multithread control device for a microprocessor in FIG. 2 . The hardware multi-thread instruction fetching device 201 includes: an instruction address control device 301 , an instruction address register sequence 302 , and a multi-thread register sequence 303 of an instruction fetching component. The instruction address control device 301 controls to generate the instruction address of each thread, and generates the next instruction address corresponding to the thread executed in the instruction fetch logic IF1 in FIG. In the clock cycle, the instruction address control device 301 generates the address of the next instruction executed by the thread i sequentially, and the address is output to the pc_DFF_1 of the sequence 302 in the next clock cycle t+1, and the value of pc_DFF_n in the t cycle in the t+1 cycle (ie The instruction address currently executed by thread i+1) is taken into the instruction address control device 301 to generate the next instruction address of thread i+1 sequential execution; the instruction address register sequence 302 stores the instruction addresses of n threads, from the pc_DFF_1 register to The pc_DFF_n registers are stored in sequence as: the next instruction address of thread j, thread j-1, ..., thread 1, thread n, thread n-1, ..., thread j+1; fetching parts multi-threaded register sequence 303 temporary storage and retrieval Refers to the intermediate result of logical n-level pipeline, stores the output of part of the instruction-fetch logic IFj (j=1, 2, . The thread number corresponding to the data stored in the register is consistent with the thread number corresponding to the pc_DFF_1 register to the pc_DFF_n register in the instruction address register sequence 302, that is, if the instruction address of thread i is stored in the pc_DFF_k register, then the IF_DFF_k register stores the IFk instruction fetch logic of thread i output.

FIG. 4 is a structural diagram of a hardware multi-thread decoding device 202 in conjunction with the general structural diagram of the hardware multi-thread control device for a microprocessor in FIG. 2 . The hardware multi-thread decoding device 202 includes: a multi-thread register sequence 401 of a decoding component, and a data bypass register sequence 402 of a decoding component. The multi-threaded register sequence 401 of the decoding part temporarily stores the intermediate results of the n-stage pipeline of decoding logic, and stores the output of part of the decoding logic IDj in each stage of registers, and the multi-threaded register sequence 401 of the decoding part stores from the ID_DFF_1 register to the ID_DFF_n register The thread number corresponding to the data is consistent with the thread number corresponding to the IF_DFF_1 register to the IF_DFF_n register in the multi-threaded register sequence 303 of the fetching part, that is, if the IFk fetching logical output of the thread i is stored in the IF_DFF_k register, then the ID_DFF_k register stores the IDk of the thread i Decoding logic output; decoding component data bypass register sequence 402 stores the intermediate execution results of the first two instructions of n threads.

FIG. 5 is a structural diagram of a hardware multi-thread execution device 203 in conjunction with the overall structural diagram of the hardware multi-thread control device for a microprocessor in FIG. 2 . The hardware multi-thread execution device 203 includes: a multi-thread initialization special instruction execution device 501 , a thread number register sequence 502 , an execution unit multi-thread register sequence 503 , and an execution unit data bypass register sequence 504 . Multi-thread initialization special-purpose instruction executive device 501 produces the hardware thread number of multi-thread; Thread number register sequence 502 is n-level register cache, and the thread number of certain hardware thread that will produce is in register sequence 502 position Th_DFF_i and this hardware thread is in instruction address Register sequence (302), fetching part multi-thread register sequence (303), decoding part multi-thread register sequence (401), executing part multi-thread register sequence (503), accessing part multi-thread register sequence (601), writing The positions in the part multi-thread register sequence (701) are consistent; the execution part multi-thread register sequence 503 temporarily stores the intermediate results of the execution logic n-level pipeline, stores the output of part execution logic Ej in each stage register, and executes the part multi-thread register The thread number corresponding to the data stored from the E_DFF_1 register to the E_DFF_n register in the sequence 503 is consistent with the thread number corresponding to the IF_DFF_1 register to the IF_DFF_n register in the multi-threaded register sequence 303 of the instruction fetch unit, that is, if the IFk instruction fetch of the thread i is stored in the IF_DFF_k register logic output, the E_DFF_k register stores the Ek execution logic output of thread i; the execution unit data bypass register sequence 504 stores the intermediate execution results of the first two instructions of n threads.

FIG. 6 is a structural diagram of a hardware multithread memory access device 204 that cooperates with the overall structural diagram of the hardware multithread control device for a microprocessor in FIG. 2 . The hardware multi-thread memory access device 204 includes: a multi-threaded register sequence 601 of the memory access part, which temporarily stores the intermediate results of the n-level pipeline of the memory access logic, stores the output of part of the memory access logic Mj in each stage of registers, and has many memory access parts The thread number corresponding to the data stored from the M_DFF_1 register to the M_DFF_n register in the thread register sequence 601 is consistent with the thread number corresponding to the IF_DFF_1 register to the IF_DFF_n register in the multi-threaded register sequence 303 of the instruction fetching part, that is, if the IFk of the thread i is stored in the IF_DFF_k register Instruction fetch logic output, then the M_DFF_k register stores the Mk execution logic output of thread i.

FIG. 7 is a structural diagram of a hardware multithread write-back device 205 that cooperates with the overall structural diagram of the hardware multithread control device for a microprocessor in FIG. 2 . The hardware multi-threaded write-back device 205 includes: a write-back component multi-thread register sequence 701, which temporarily stores the intermediate results of the write-back logic n-level pipeline, stores part of the output of the write-back logic Wj in each level of registers, and has many write-back components The thread number corresponding to the data stored in the thread register sequence 701 from the W_DFF_1 register to the W_DFF_n register is consistent with the thread number corresponding to the IF_DFF_1 register to the IF_DFF_n register in the multi-threaded register sequence 303 of the instruction fetching part, that is, if the IFk of the thread i is stored in the IF_DFF_k register Fetch logic output, then the W_DFF_k register stores thread i's Wk write-back logic output.

FIG. 8 is a structural diagram of a hardware multithreading register set 206 in conjunction with the overall structural diagram of the hardware multithreading control device for a microprocessor in FIG. 2 . The hardware multi-thread register set 206 includes: a decoder 801 , a multiplexer 802 , and n register sets 803 . The decoder 801 decodes according to the register control signal generated by the multi-thread control device 207 and the address signal generated by the hardware multi-thread decoding device 202 or the hardware multi-thread write-back device 205, and outputs the valid register group Regs_i of the current thread. Can signal and the register address of current operation; Multiplexer 802, according to the register control signal that multi-thread control device 207 produces, selects the data output of a certain register group of current thread; N register groups 803, provide respectively to The n threads are used independently of each other, and the written data comes from the output data of the hardware multi-threaded write-back device 205 , and the read data is sent to the hardware multi-threaded decoding device 202 .

The present invention can realize hardware multi-thread execution on a microprocessor, and completes the mapping from software multi-thread to hardware multi-thread by providing a multi-thread initialization special instruction, and Fig. 9 is the encoding format of the provided hardware multi-thread initialization special instruction . Including: an opcode field 901 for identifying the instruction; an operand field 902 for operating the destination operand, the destination operand can be a register in the register bank corresponding to the hardware thread, and is used to identify the instruction in the initialization phase. Hardware thread number; the operand field 903 for operating the source operand, and the source operand may be a newly generated thread number.

FIG. 10 is a step diagram of a hardware multi-thread control method. The multi-thread instruction fetching step 1001 is used to read the instructions of each thread, and generate the instruction address of each thread. Including multi-thread instruction address control, multi-thread instruction address cache, and multi-thread instruction fetch. The multi-thread decoding step 1002 is used to decode the instructions of each hardware thread, and prepare the register data required by the execution steps. Including multi-thread decoding, multi-thread register operand preparation, data bypass control of decoding components. The multi-thread execution step 1003 is used to execute instructions of each thread. Including multi-thread initialization special instruction execution, thread number cache, execution unit data bypass control, multi-thread conventional instruction execution. The multi-thread memory access step 1004 is used to write the execution result of each thread into the memory or read the data required by the thread from the memory. The multi-thread write-back step 1005 is used to write the execution result of each thread back to the register, including multi-thread write-back data control and multi-thread write-back register address control.

Taking 4 hardware threads as an example (n=4) below, the implementation sequence of the present invention will be described.

Fig. 11 is a schematic diagram of hardware multi-thread pipeline division and clock. Taking 101 instruction fetch logic as an example, in Figure 11, the 101 instruction fetch logic IF is symmetrically divided into 4 stages of pipeline, and the delay of each stage of logic becomes 1/4 of that of a single stage of pipeline, if the clock of the IF logic in Figure 1 The period is T, and the corresponding clock is clk1 in Figure 11. Then the clock of the four hardware threads can be shown as clk2, and the frequency is 4 times that of clk1, so that the four threads of the hardware can run in parallel within the time of executing one thread in a single-stage pipeline. Execute 4 threads.

FIG. 12 is a schematic diagram of hardware multi-thread execution timing. Taking n=4 as an example, #1, #2, #3, and #4 respectively correspond to 4 different hardware threads, and all hardware threads start fetching and executing instructions from the same instruction address. Assuming that execution starts at T1, the hardware Thread #1 executes the first step IF1 of the instruction fetch logic of the first instruction; at T2, hardware thread #1 executes the second step IF2 of the instruction fetch logic of the first instruction, while hardware thread #2 executes the instruction fetch logic of the first instruction The first step IF1 of the fetching logic; and so on, at T5 time, the hardware thread #1 executes the second step ID2 of the decoding logic of the first instruction and the second step IF2 of the fetching logic of the second instruction, the hardware thread #2 Execute the first step ID1 of the decoding logic of the first instruction and the first step IF1 of the instruction fetch logic of the second instruction. Assuming that the first instruction is a special instruction for multi-thread initialization, hardware thread #2 starts to fetch the special instruction for multi-thread initialization at time T2, hardware thread #2 starts to decode the special instruction for multi-thread initialization at time T5, and hardware thread #2 starts at time T6 Execute the special instruction for multi-thread initialization to generate the corresponding hardware thread number 2. At T7, the hardware thread number 2 is passed to the execution and decoding stage of the second and third instructions of hardware thread #2 through data bypass. At T8, the hardware thread # 2. Start to initialize the special instruction write-back logic, and complete the initialization special instruction write-back logic at time T9. The hardware thread number 2 has been calculated by the initialization special instruction at T7, and can be passed to the second and third instruction execution and decoding stages of the hardware thread #2 through data bypass. If the third instruction is a conditional jump instruction, Then it starts to decode the conditional jump instruction at T7 time, and decides whether to jump by judging the hardware thread number from the data bypass, that is, comparing the thread number with 2, for hardware thread #2, its hardware thread number is the same as 2 is equal, jump is realized, for other threads, its hardware thread number is not equal to 2, do not jump, continue to execute sequentially, thereby realizing the separation of each thread, the conditional jump instruction does not have to be only the third instruction, in After the third instruction, it is possible, because the hardware thread number has been calculated at T7, and the conditional jump can be performed through the conditional jump instruction. The descriptions for other situations of thread separation are similar. It can be seen that if the first instruction is a special instruction for multi-thread initialization, then the third instruction or the third instruction can realize thread separation through a conditional jump instruction after the third instruction.

Claims (10)

1. a hardware multi-thread control method for microprocessor, it is characterized in that comprising the following steps: 1) Multithread instruction fetching step (1001), used for instruction reading of each thread, and instruction address generation of each thread; 2) Multi-thread decoding step (1002), used to decode the instructions of each hardware thread, and prepare the register data required by the multi-thread execution step (1003); 3) Multi-thread execution step (1003), for executing each thread instruction; 4) The multi-thread memory access step (1004) is used to symmetrically divide the memory access logic (105) into n-level pipelines. The execution results of each thread are written into the memory or the data required by the thread is read from the memory. When a certain thread When blocked, only the data access of this thread is blocked, and the data access of other threads runs normally; 5) Multi-thread writing back step (1005), for writing the execution results of each thread back to the register bank. 2. The hardware multi-thread control method as claimed in claim 1, characterized in that the multi-thread instruction fetching step (1001) comprises multi-thread instruction address control, multi-thread instruction address cache, and multi-thread instruction fetch; 1) Multi-thread instruction address control, which is used to generate the instruction address of each thread. When a thread is blocked, only the update of the instruction address of this thread is blocked, and the instruction addresses of other threads are updated normally; 2) Multi-thread instruction address cache, used to store the instruction addresses of n threads; 3) Multi-thread instruction fetching, which is used to symmetrically divide the instruction fetch logic (101) into n-level pipelines, and fetch software thread instructions corresponding to n hardware threads. 3. The hardware multi-thread control method as claimed in claim 1, characterized in that the multi-thread decoding step (1002) comprises multi-thread decoding, multi-thread register operand preparation, decoding component data bypass control; 1) Multi-thread decoding, which is used to symmetrically divide the decoding logic (102) into n-level pipelines to complete multi-thread initialization special instruction decoding and regular instruction decoding. When a thread is blocked, only the thread instruction translation is blocked code, other thread instruction decoding runs normally; The multi-thread initialization special instruction includes: opcode domain (901), used to identify the instruction, operand domain (902), used for operating purpose operand, operand domain (903), used for operating source operand ; 2) The multi-thread register operand preparation is used to select the register group corresponding to the thread from n register groups, and read the required operand of the instruction; 3) Data bypass control of the decoding component, which is used to provide data bypassed to a certain pipeline stage of instruction decoding; 4. The hardware multi-thread control method as claimed in claim 1, characterized in that the multi-thread execution step (1003) includes multi-thread initialization special instruction execution, thread number cache, execution component data bypass control, multi-thread conventional instruction execution; 1) Execution of multi-thread initialization special instructions, used to generate a new hardware thread number, the new hardware thread number corresponds to the software thread executed by the hardware thread; 2) thread number cache, for the new hardware thread number cache that described multi-thread initialization special instruction execution produces, makes the position of certain new hardware thread number that produces in the thread number register sequence (502) and this hardware thread at address Pointer register sequence (302), fetching part multi-thread register sequence (303), decoding part multi-thread register sequence (401), execution part multi-thread register sequence (503), memory access part multi-thread register sequence (601), The position in the write-back component multi-thread register sequence (701) is consistent; 3) Execute component data bypass control, which is used to provide data bypassed to a certain pipeline stage of instruction execution; 4) Execution of multi-thread conventional instructions, which is used to symmetrically divide the execution logic (103) into n-level pipelines, and complete the execution of conventional instructions of n hardware threads. When a certain thread is blocked, only the execution of the thread instruction is blocked, and other thread instructions Perform normal operation. 5. The hardware multi-thread control method as claimed in claim 1, characterized in that the multi-thread write-back step (1005) symmetrically divides the write-back logic (105) into n-level pipelines, and when a certain thread is blocked, only this thread is blocked. Thread data is written back, and other thread data is written back to normal operation, and the multi-thread write-back step (1005) includes multi-thread write-back data control, multi-thread write-back register address control; 1) Multi-threaded write-back data control, used for preparation and output of register data to be written back; 2) The multi-threaded write-back register address control is used for the preparation and output of the register address to be written back. 6. A hardware multi-thread control device for a microprocessor, the device supports n hardware threads to execute in parallel by adopting pipeline technology; it is characterized in that the device includes a hardware multi-thread instruction fetching device (201), a hardware multi-thread Decoding device (202), hardware multi-thread execution device (203), hardware multi-thread memory access device (204), hardware multi-thread write-back device (205), hardware multi-thread register group (206), multi-thread control device ( 207); The hardware multi-thread instruction fetching device (201) is used to complete the value fetching operation for n hardware threads, output the instruction to the hardware multi-thread decoding device (202), and control the instruction fetching outputted by the multi-thread control device (207) The signal completes the update operation of the next instruction address of n hardware threads, and realizes the storage of the instruction address; The hardware multi-thread decoding device (202), is used to receive instructions from the n threads of the hardware multi-thread instruction fetching device (201), and decode control signals from the multi-thread control device (207), to complete n hardware threads Decoding operation, outputting the operation control information and data information to be operated to the hardware multi-thread execution device (203); The hardware multi-thread execution device (203) is used to receive the operation control information and data information from the hardware multi-thread decoding device (202), the execution control signal from the multi-thread control device (207), and complete the instruction execution of n threads , output the data information of the execution result to the hardware multi-thread memory access device (204); The hardware multi-thread memory access device (204) is used to complete the memory access operations of n hardware threads; the hardware multi-thread memory access device (204) includes a memory access component multi-thread register sequence (601), which is used for temporary storage access Store the intermediate results of logical n-level pipelines, and each level of registers M_DFF 1 ~ M_DFF n corresponds to the output of a part of the memory access logic M1 ~ Mn of a hardware thread, wherein the input of the memory access logic M1 is the output of the hardware multi-thread execution device (203) With the access control signal that multi-thread control device (207) produces, the output of register M_DFF n is as the output of hardware multi-thread memory access device (204); The hardware multi-thread write-back device (205) is used to output the data information to be written back and the current register address to be written back to the hardware multi-thread register group (206); the hardware multi-thread write-back device (205) includes Write-back component multi-threaded register sequence (701), used to temporarily store the intermediate results of write-back logic n-level pipeline, each level of registers W DFF 1～W_DFF n corresponds to the output of a hardware thread’s part write-back logic W1～Wn, wherein The input of writing back logic W1 is the write-back control signal that the output of hardware multi-thread memory access device (204) and multi-thread control device (207) produce, and the output of register W_DFF n writes back the output of device (205) as hardware multi-thread ; The hardware multi-thread register group (206), according to the register control signal output by the multi-thread control device (207), cooperates with the hardware multi-thread decoding device (202) and the hardware multi-thread write-back device (205), to complete n hardware threads Register bank read and write operations; The multi-thread control device (207) outputs control signals to control the execution of each device of the entire hardware multi-thread device, specifically including the following control signals: generating an instruction fetch control signal and outputting it to the hardware multi-thread instruction fetch device (201), generating translation A code control signal is output to the hardware multi-thread decoding device (202), an execution control signal is generated and output to the hardware multi-thread execution device (203), a memory access control signal is generated and output to the hardware multi-thread memory access device ( 204), generating a write-back control signal to output to the hardware multi-thread write-back device (205), generating a register control signal to output to the hardware multi-thread register set (206). 7. The hardware multi-thread control device according to claim 6, wherein the hardware multi-thread instruction fetching device (201) comprises the following components: 1) the instruction address control device (301), according to the output of the instruction fetch control signal (comprising instruction address control signal and jump address) and pc_DFFn produced by the multi-thread control device (207), generates the next instruction address of the current thread, And send it into the instruction address register sequence (302); 2) instruction address register sequence (302), used to store the instruction addresses of n threads, the instruction address of each thread passes through the instruction address registers pc_DFF1～pc_DFF n in turn; 3) The multi-threaded register sequence (303) of the instruction fetching component is used to temporarily store the intermediate results of the n-stage pipeline of the instruction fetch logic, and each stage of registers IF_DFF 1 ~ IF_DFF n corresponds to the output of part of the instruction fetch logic IF1 ~ IFn of a hardware thread, Wherein the input of the logic IF1 fetching is the output of the instruction address control device (301) and the fetching control signal produced by the multi-thread control device (207), and the output of the register IF_DFF n is the output of the hardware multi-thread fetching device (201). 8. The hardware multi-thread control device according to claim 6, wherein the hardware multi-thread decoding device (202) comprises: 1) The multi-threaded register sequence (401) of the decoding part is used to temporarily store the intermediate results of the n-level pipeline of the decoding logic, and each level of registers ID_DFF 1 ~ ID_DFF n corresponds to the output of part of the decoding logic ID1 ~ IDn of a hardware thread, Wherein the input of the decoding logic ID1 is the output of the hardware multi-thread instruction fetching device (201), the read data of the hardware multi-thread register group (206) and the decoding control signal produced by the multi-thread control device (207), register ID_DFF n The output is the output of the hardware multi-thread decoding device (202); 2) data bypass register sequence (402), for storing the intermediate execution results of the first two instructions of each thread, and the stored data comes from the output data of the hardware multi-thread execution device (203) and the hardware multi-thread memory access device (204) respectively ), the input data of each stage register ID_Bypass_1~ID_Bypass_n-1 of the data bypass register sequence are respectively input to the corresponding decoding logic ID1~IDn-1, and the output data of the register ID_Bypass_n-1 is input to the decoding logic IDn . 9. The hardware multi-thread control device according to claim 6, wherein the hardware multi-thread execution device (203) comprises the following components: 1) Multi-thread initialization dedicated instruction execution device (501), used to generate hardware thread number, and output the generated hardware thread number to the thread number register sequence (502), the hardware thread number corresponds to the software executed by the hardware thread thread; 2) thread number register sequence (502), for the hardware thread number that cache produces, each thread number that is produced by multi-thread initialization special-purpose instruction execution device (501) passes through thread number register Th_DFF1～Th_DFF n successively; 3) The multi-threaded register sequence (503) of the execution unit is used to temporarily store the intermediate results of the execution logic n-level pipeline, and each level of registers E_DFF 1 ~ E_DFF n corresponds to the output of a part of the execution logic E1 ~ En of a hardware thread, wherein the execution logic The input of E1 is the execution control signal that the output of hardware multi-thread decoding device (202) and multi-thread control device (207) produce, the output of register E_DFF n or the output of register Th_DFF n is as hardware multi-thread execution device (203) output; 4) The data bypass register sequence (504), which is used to store the intermediate execution results of the first two instructions of each thread, respectively comes from the output data of the hardware multi-thread execution device (203) and the hardware multi-thread memory access device (204) For output data, the input data of registers E_Bypass_1~E_Bypass_n-1 of each stage of the data bypass register sequence are respectively input to the corresponding execution logic E1~En-1, and the output data of register E_Bypass_n-1 is input to the decoding logic En. 10. The hardware multi-thread control device according to claim 6, characterized in that, the hardware multi-thread register set (206) comprises the following components: 1) Decoder (801), according to the register control signal generated by the multi-thread control device (207) and the address signal generated by the hardware multi-thread decoding device (202) or the hardware multi-thread write-back device (205), to decode code, outputting the register bank enable signal of the current thread and the register address of the current operation; 2) multiplexer (802), selects the data of the register group of current thread according to the register control signal that multi-thread control device (207) produces, and outputs it; 3) n register groups (803), respectively provided to n threads to use, independent of each other, write data from the output data of the hardware multi-thread write-back device (205), and read data to the hardware multi-thread decoding device ( 202).

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