CN101945054B - Dispatching algorithm suitable for feedback two-stage exchange structure - Google Patents

Abstract

The invention discloses dispatching algorithm suitable for feedback two-stage exchange structure, which is suitable for an optional input port i in a fiber-to-the-service-area (FTSA) structure to select a queue head cell of a non-nullVOQ1 (i,r) meeting the condition that a virtual output queue (VOQ)2 (j,r) is null according to the rules of the algorithm and sends the queue head cell to an intermediate port j connected with the input port i in a next time slot, wherein the first non-null VOQ1 (i, r) which meets the condition that VOQ2 (j,r) is null is searched according to a sequence of r= i-2, i-3,..., 0, N-1, N-2,..., i, i-1 and the queue head cell of the VOQ2 (j,r) is forwarded to the optional input port. The dispatching algorithm comprises the following steps of: establishing mapping; filtering information; dispatching priority bitmap algorithm; and finally, reversely mapping a dispatching result into sub-sequence number. The dispatching algorithm ensures that the algorithm complexity of the FTSA structure is reduced from O (N) to O (1) and improves the high-rate exchange capability and expandability of the FTSA.

Description

A kind of dispatching algorithm that is applicable to feedback system two-stage switching fabric

Affiliated technical field

The invention belongs to the internet information transmission technique field.

Background technology

The surge of Internet user's rapid growth and multimedia service stream makes Internet face increasing transfer of data pressure; Though close wavelength-division multiplex technology makes the data transmission rate of single wavelength up to 160Gbps; But the data transmission rate of the exchange rate of relay system in the light territory, this crosses the bottleneck of the low Internet of becoming with regard to making relay system because of exchange rate.In addition, long-term flow monitoring shows that the Internet data flow has self-similarity, and it is sudden that its characteristic feature is that data have.The high speed switching fabric that therefore, can adapt to the self similarity Business Stream just becomes one of core technology of Internet of future generation.

Traditional switching fabric is because reasons such as complexity or speed-up ratio all can't satisfy following switching requirement.In recent years; Feedback system two-stage switching fabric FTSA utilizes input port i and output port i to be positioned at this characteristic of same ply-yarn drill; Crossbar connection mode through a kind of stagger arrangement symmetry characteristic (staggered symmetry) feeds back to input with the state information of middle buffer memory; Input selects a cell to transfer to middle buffer memory based on this feedback information; Underflow (underflow) problem of buffer memory in the middle of the mode of operation of this " shooting the arrow at the target " can effectively reduce, thus extremely excellent delay performance obtained.

But the computation complexity of existing algorithm that is applicable to this structure is higher, and too high algorithm complex makes whole exchange flow process sluggish, has reduced the high speed exchange capacity and the extensibility of FTSA structure.

Detailed introduction to this problem is following:

(1) FTSA structure

FTSA is made up of two-stage crossbar (being designated as XB1 and XB2 respectively) and two-stage VOQ (VirtualOutput Queue) buffering (being designated as VOQ1 and VOQ2 respectively), and (j k) has only 1 cell space to VOQ2, and is as shown in Figure 1 arbitrarily.XB1 and XB2 adopt a kind of special stagger arrangement symmetry connection mode, and its key feature is that then the t+1 time slot must have input port k to link to each other with Centronics port j, and is as shown in Figure 2 if t time slot Centronics port j links to each other with output port k.Be unlikely to cause that under the situation about obscuring, " input port " all refers to the input port of XB1 in the literary composition, " Centronics port " all refers to the input port of XB2, and " output port " all refers to the output port of XB2.

Because input port k and output port k are positioned at same ply-yarn drill; FTSA is by means of this special connection mode; Feed back to input port k after when t, before the trough end buffer status information of Centronics port j being transferred to output port k via XB2; And the t+1 time slot just has input port k to link to each other with Centronics port j, thus input port k can be after the cache information of Centronics port j arrives and the t+1 time slot before beginning during this period of time in the cell forwarding of carrying out " shooting the arrow at the target " of the middle cache information that obtains according to known input-buffer information and feedback dispatch." underflow " problem of buffer memory in the middle of the mode of operation of this " shooting the arrow at the target " can significantly reduce, thus extremely excellent delay performance obtained.In addition, among the FTSA arbitrarily VOQ2 (j, k) buffer memory capacity strategy that 1 cell space only is set has also guaranteed the orderly forwarding of cell.

(2) computation complexity of existing algorithm

The existing algorithm that is applicable to FTSA has three kinds: RR (Round-Robin), EDF (Earliest Departure First) and LQF (Longest QueueFirst).

LQF algorithm performance optimum but complexity is the highest, the computation complexity of search maximum queue is O (logN), might as well establish VOQ1 (i, the maximum queue that r) obtains for searching algorithm, but this formation might not be satisfactory (possible VOQ2 (j, r) non-NULL).Consider comparatively general method, the LQF algorithm among the FTSA needs N all formation of search under worst case, and promptly the computation complexity of LQF is O (N).

The RR algorithm is regarded as and is easy to relatively realize, but regular next formation might not be satisfactory based on Round-Robin equally, so the RR algorithm also need be searched for whole N formation under the worst case.

Crossbar connection mode by shown in Figure 2 can be known; For any input port i; Any Centronics port j that is attached thereto of time slot must link to each other with output port i-2 at next time slot (adding reducing and finally all need promptly coming down to (i-2) mod N of port numbers, same down) to the N delivery.This just means, (i, the cell in r) are forwarded to VOQ2, and (j, r), then this cell needs that (j r) is forwarded after waiting for the i-r-2 time slot at VOQ2 if VOQ1.According to this specific character, the each scheduling of EDF algorithm all selects in the shortest time, to leave the cell of switch, and promptly for any input port i, the EDF algorithm is according to r=i-2; I-3 ..., 0, N-1; N-2 ..., i; First satisfies the sequential search of i-1 VOQ2 (j is that (i r) and with its head of the queue cell transmits empty non-NULL VOQ1 r).Though simulation result shows that the delay performance of EDF algorithm is comparatively outstanding, under the worst case, the EDF algorithm also need be searched for whole N formation, so the computation complexity under the worst case also is O (N).

With respect to the crossbar connection mode of O (1) complexity, in whole exchange flowchart process, the computation complexity at any place is higher than O (1) and all can causes whole exchange flow process sluggish, and then has damaged load balancing structure high speed exchange capacity originally.FTSA is as a kind of scheme that solves out-of-sequence problem of load balancing structure, and its existing three kinds of dispatching algorithms computation complexity under worst case is O (N).The higher dispatching algorithm of this complexity will inevitably reduce the high speed exchange capacity of FTSA, and algorithm complex is relevant with exchange scale N simultaneously certainly will increase the difficulty of expanding the exchange scale, reduces the extensibility of FTSA.

Summary of the invention

The objective of the invention is to solve the existing too high problem of algorithm complex of FTSA structure, create a kind of cell priority algorithm of leaving away the earliest, make computation complexity be reduced to O (1), improve high speed exchange capacity and the extensibility of FTSA from O (N) based on the priority bitmap.

The objective of the invention is to realize through following means.

A kind of dispatching algorithm that is applicable to feedback system two-stage switching fabric; Be applicable to that any input port i selects to satisfy condition VOQ2 (j according to algorithm self rule in the FTSA structure; R) be empty non-NULL VOQ1 (i; R) head of the queue cell, and forward it to the Centronics port j that next time slot links to each other with input port i; Adopt r=i-2, i-3 ..., 0, N-1, N-2 ..., i, first satisfies the sequential search of i-1 VOQ2 (j is that (i r) and with its head of the queue cell transmits empty non-NULL VOQ1 r); May further comprise the steps:

1) at first the buffer status information of the N child queues of any input port is mapped as the priority state data, sets up mapping as follows:

A: (i r) is mapped as the task that priority is i-r-2 to norator formation VOQ1;

B:VOQ1 (i, r) transferring non-dummy status to by dummy status, to be mapped as priority be that the task of i-r-2 is ready;

C:VOQ1 (i, r) transferring dummy status to by non-NULL, to be mapped as priority be that the task of i-r-2 is finished;

2) the middle buffer status information V that at the beginning of each time slot, utilizes feedback to obtain filters priority ready list OSRdyTbl and generates interim priority ready list TmpRdyTbl, generates ready group of TmpRdyGrp of interim priority according to TmpRdyTbl subsequently.

3) according to 2) the ready group of TmpRdyGrp of interim priority and the interim priority ready list TmpRdyTbl that generate, adopt the priority bit nomography to dispatch, and with scheduling result---limit priority is number counter to be mapped as subqueue number.

Adopt the inventive method---based on the cell priority algorithm PB-EDF that leaves away the earliest (Priority Bitmap-based Earliest Departure First) of priority bitmap; At any input port, the N child queues is mapped as N kind priority immobilizes and each unequal task; If certain child queues is arrived for non-dummy status then is regarded as a ready task by idle running; If certain child queues transfers dummy status to by non-NULL, then be regarded as a task termination that is in executing state.According to this mapping ruler, the state of input-buffer can characterize with a priority ready list arbitrarily.At the beginning of each time slot; Utilize the middle buffer status information of feedback that the invalid information that is write down in the priority ready list is filtered; Generate real-time and effective priority state data and also utilize the priority bit nomography to dispatch, at last with the anti-subqueue number of being mapped as of scheduling result.The present invention makes FTSA structure algorithm complexity be reduced to O (1) from O (N), has improved high speed exchange capacity and the extensibility of FTSA.

Description of drawings

Fig. 1 prior art is based on the two-stage switching fabric FTSA structure chart of feedback.

Fig. 2 is the crossbar connection mode sketch map of prior art stagger arrangement symmetry.

Fig. 3 is embodiment of the invention priority ready list OSRdyTbl.

Fig. 4 is embodiment of the invention priority mapping table OSMapTbl.

Fig. 5 is the logical circuitry that the embodiment of the invention generates TmpRdyTbl.

Fig. 6 is the logical circuitry that the embodiment of the invention generates TmpRdyGrp.

Fig. 7 is ready group of TmpRdyGrp of the interim priority of the embodiment of the invention and interim priority ready list TmpRdyTbl.

Fig. 8 is embodiment of the invention priority decision table OSUnMapTbl.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is described further.

The enforcement means can be summarized as three steps:

1. mapping: set up the mapping relations of subqueue and priority, write down the state information of any input-buffer with the priority ready list.

2. filter: utilize the middle buffer status information of feedback to filter the invalid priority in the priority ready list and generate effective priority state data.

3. scheduling: utilize traditional priority level bitmap algorithm to dispatch and with the anti-subqueue number of being mapped to of scheduling result based on 2. result.

Concrete implementation process is following:

(it is example that following explanation is counted N=64 with switching port, and 0 is limit priority, and 63 is lowest priority)

1. mapping

For any input port i, the EDF algorithm is always according to r=i-2, i-3 ..., 0, N-1, N-2 ..., i, first satisfies the sequential search of i-1 VOQ2 (j is that (i r) and with its head of the queue cell transmits empty non-NULL VOQ1 r).Based on this specific character of EDF algorithm, PB-EDF algorithm of the present invention is set up following mapping:

A: (i r) is mapped as the task that priority is i-r-2 to norator formation VOQ1;

B:VOQ1 (i, r) transferring non-dummy status to by dummy status, to be mapped as priority be that the task of i-r-2 is ready;

(i, r) transferring dummy status to by non-NULL, to be mapped as priority be that the task of i-r-2 is finished to C:VOQ1.

Can the buffer status information of any input port be mapped as the priority state data according to this mapping method, specifically use priority ready list OSRdyTbl shown in Figure 3 to represent.

The maintenance regulation of OSRdyTbl is (C language representation) as follows:

When VOQ1 (i, r) by idle running for non-dummy status (task of being equivalent to priority p=i-r-2 is ready):

OSRdyTbl[p＞＞3]|＝OSMapTbl[p&Ox07]；

When VOQ1 (i r) transfers dummy status (being equivalent to the task termination of priority p=i-r-2) to by non-NULL:

OSRdyTbl[p＞＞3]&＝～OSMapTbl[p&0x07]

OSMapTbl is called the priority mapping table, is all fixing form of a size and content, and is as shown in Figure 4.

2. filter

Has higher priority though consider some formation; But possibly should not be scheduled because of the target cache non-NULL; So PB-EDF also need generate the interim priority ready list of real-time and effective TmpRdyTbl and interim ready group of TmpRdyGrp of priority by the middle buffer status information of feeding back with the invalid priority data filter among the priority ready list OSRdyTbl simultaneously.

In addition because the 64bit cache information that feeds back to input port i is tactic according to port 0～63, for ease of calculate can with its order according to priority (i-2, i-3 ..., 0, N-1, N-2 ..., i, V is arranged and be designated as to order i-1) again.As at input port 5, the 64bit of V writes down VOQ2 (j, 3) respectively, VOQ2 (j, 2), and VOQ2 (j, 1), VOQ2 (j, 0), VOQ2 (j, 63), VOQ2 (j, 62) ..., the buffer status information of VOQ2 (j, 4).This permutatation mode by turn of any input port is fixed,, need not extra time loss so can realize through placement-and-routing.

Filter operation comprises the operation of two steps:

A: utilize feedback information V to filter priority ready list OSRdyTbl and generate interim priority ready list TmpRdyTbl, method is following:

TmpRdyTbl[0]＝OSRdyTbl[0]&V[0]；

TmpRdyTbl[1]＝OSRdyTbl[1]&V[1]；

……

TmpRdyTbl[6]＝OSRdyTbl[6]&V[6]；

TmpRdyTbl[7]＝OSRdyTbl[7]&V[7]；

Here V [0]～V [7] is the one group of data that comprises 8bit, and as at input port 5, V [0] comprises VOQ2 (j, 3), VOQ2 (j, 2), VOQ2 (j, 1), VOQ2 (j, 0), VOQ2 (j, 63), VOQ2 (j, 62), VOQ2 (j, 61), the buffer status information of VOQ2 (j, 60).V [1]～V [7] in order.Its logical circuitry is as shown in Figure 5.First bit of " V [0] _ 0 " expression V [0] among the figure, all the other are similar, down together.

B: generate ready group of TmpRdyGrp of interim priority according to interim priority ready list TmpRdyTbl.

TmpRdyTbl [0]～TmpRdyTbl [7] 8 bit separately carry out inclusive-OR operation, and the 8bit operation result of generation is stored in TmpRdyGrp, and its logical circuitry is as shown in Figure 6.

Interim ready group of TmpRdyGrp of priority is as shown in Figure 7 with the relation of interim priority ready list TmpRdyTbl.

3. scheduling

Utilize the priority bit nomography to dispatch according to ready group of TmpRdyGrp of interim priority that 2. generates and interim priority ready list TmpRdyTbl; Might as well establish and dispatch the limit priority that obtains is hp; Its Senior Three position is represented with High3Bit, representes with Low3Bit for its low three, then:

high3Bit＝OSUnMapTbl[OSRdyGrp]；

low3Bit＝OSUnMapTbl[TmpRdyTbl[high3Bit]]；

hp＝(high3Bit＜＜3)+low3Bit；

OSUnMapTbl is called the priority decision table, is all fixing form of a size and content equally.As shown in Figure 8.

The searching route of the existing EDF algorithm of PB-EDF algorithm and FTSA is identical, and the scheduling result of the two is on all four.

The advantage of EDF algorithm PB-EDF based on the priority bit nomography disclosed by the invention has two aspects:

(1): the computation complexity of PB-EDF algorithm is reduced to O (1)

Can know that by last joint narration the workflow of PB-EDF algorithm is following:

A: the invalid priority information that the information V that arrives according to feedback filters among the priority ready list OSRdyTbl generates interim priority ready list TmpRdyTbl.

B:, generate ready group of TmpRdyGrp of interim priority according to interim priority ready list TmpRdyTbl

C: the result according to A and B utilizes the priority bit nomography to dispatch, and with the anti-subqueue number of being mapped as of result.

Above workflow, like Fig. 5 and shown in Figure 6, the switching speed that the A flow process is consuming time to be depended on " with door "; The B flow process depends on the speed of disjunction gate; The C flow process only needs four memory access (comprise reflection and penetrate operation) and limited number of time " bit arithmetic " to accomplish, and it is irrelevant that the computation complexity of visible PB-EDF and switching port are counted N, and its computation complexity is O (1).

Introduce the PB-EDF algorithm and can make FTSA realize O (1) complexity, improved high speed exchange capacity and the autgmentability of FTSA in whole exchange flow process.

(2): the time loss of PB-EDF algorithm depends on the memory access operation of fixed number of times, that is for the exchange scale of confirming, its scheduling time is fixed, and it is irrelevant to dispatch buffer status information and the feedback information with input port consuming time.When definite during slot length, this characteristic of PB-EDF can avoid considering consuming time under the algorithm worst case.

Claims (1)

1. one kind is applicable to the dispatching algorithm of feeding back system two-stage switching fabric; Be applicable to feedback system two-stage switching fabric; Be that any input port i selects to satisfy condition VOQ2 (j according to algorithm self rule in the FTSA structure; R) be empty non-NULL VOQ1 (i, head of the queue cell r), and forward it to the Centronics port j that next time slot links to each other with input port i; Adopt r=i-2, i-3 ..., 0, N-1, N-2 ..., i, first satisfies the sequential search of i-1 VOQ2 (j is that (i r) and with its head of the queue cell transmits empty non-NULL VOQ1 r); May further comprise the steps:

1) at first the buffer status information of the N child queues of any input port is mapped as the priority state data, sets up mapping as follows:

A: (i r) is mapped as the task that priority is i-r-2 to norator formation VOQ1;

B:VOQ1 (i, r) transferring non-dummy status to by dummy status, to be mapped as priority be that the task of i-r-2 is ready;

C:VOQ1 (i, r) transferring dummy status to by non-NULL, to be mapped as priority be that the task of i-r-2 is finished;

2) the middle buffer status information V that at the beginning of each time slot, utilizes feedback to obtain filters priority ready list OSRdyTbl and generates interim priority ready list TmpRdyTbl, generates ready group of TmpRdyGrp of interim priority according to TmpRdyTbl subsequently;

3) according to 2) the ready group of TmpRdyGrp of interim priority and the interim priority ready list TmpRdyTbl that generate, adopt the priority bit nomography to dispatch, and with scheduling result---limit priority is number counter to be mapped as subqueue number.

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