CN101944343A - Liquid crystal display system and pixel delay charging circuit - Google Patents
Liquid crystal display system and pixel delay charging circuit Download PDFInfo
- Publication number
- CN101944343A CN101944343A CN 201010275170 CN201010275170A CN101944343A CN 101944343 A CN101944343 A CN 101944343A CN 201010275170 CN201010275170 CN 201010275170 CN 201010275170 A CN201010275170 A CN 201010275170A CN 101944343 A CN101944343 A CN 101944343A
- Authority
- CN
- China
- Prior art keywords
- liquid crystal
- flip
- data signal
- flop
- latch data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a liquid crystal display system which can solve the problem of uneven liquid crystal panel color. The liquid crystal display system utilizes an output enable signal and a latch data signal which are generated by a pixel delay charging circuit according to one time-sequence control circuit of the liquid crystal display system to generate a new latch data signal to the source electrode driving circuit of the liquid crystal display system. Thus, when the source electrode driving circuit charges an mth-grade scanning on-line pixel, a switch relevant to an (m-1)th-grade scanning on-line pixel is completely turned off.
Description
Technical field
The invention relates to a kind of liquid crystal display systems, refer to a kind of especially in order to improve the liquid crystal display systems of irregular colour.
Background technology
In the prior art, the gate drive circuit of liquid crystal panel system be utilize the output pulse wave in regular turn with sweep trace G1, G2, G3, G4, G5 ... on thin film transistor (TFT) open, source electrode drive circuit can convert corresponding video data to voltage then, the pixel of liquid crystal panel is discharged and recharged the voltage of corresponding GTG.The type of drive of gate drive circuit is after the previous column thin film transistor (TFT) all cuts out, just open the thin film transistor (TFT) of next column, but the situation wrong for fear of charging takes place, (Output Enable, OE) signal is with the interval of the output pulse wave that is used for adjusting gate drive circuit to have designed output enable.Please refer to Fig. 1, Fig. 1 illustrates that the output pulse wave of gate drive circuit is the synoptic diagram of electronegative potential VGL when output enable signal OE activation.
But sweep trace on the liquid crystal panel and non-ideal transmission line, its impedance meeting causes the online output pulse wave of scanning during the output enable signal activation, can't reduce to electronegative potential VGL at once to close the online thin film transistor (TFT) of scanning, form the phenomenon of weak noble potential (weak VGH).Therefore, as source electrode drive circuit output latch data (latch data, when LD) signal charges to the pixel on the m level sweep trace Gm, also can charge to the pixel on the m-1 level sweep trace Gm-1, cause liquid crystal panel to present the situation of irregular colour because of the phenomenon of weak noble potential.Please refer to Fig. 2, Fig. 2 is that explanation is because the phenomenon of weak noble potential causes the wrong synoptic diagram of pixel charging on the liquid crystal panel.As shown in Figure 2, a period of time after the negative edge of latch data LD occurs, source electrode drive circuit begins the pixel on the m level sweep trace Gm is charged.But this moment is because the phenomenon of the weak noble potential of m-1 level sweep trace Gm-1 makes source electrode drive circuit also can cause liquid crystal panel to produce the phenomenon of irregular colour to the charging of the pixel on the m-1 level sweep trace Gm-1.
Summary of the invention
The purpose of this invention is to provide a kind of in order to improve the liquid crystal display systems of irregular colour.This liquid crystal display systems comprises a liquid crystal panel, a gate drive circuit, one source pole driving circuit, a sequential control circuit and a pixel delayed charging circuit.This liquid crystal panel has a plurality of pixels; This gate drive circuit is in order to controlling the output pulse wave of a plurality of output scanning lines, and wherein the output pulse wave of each sweep trace is the open and close that are coupled to the switch of a pixel in order to control; This source electrode drive circuit is in order to convert a video data to a data voltage, according to this data voltage corresponding pixel to be discharged and recharged the voltage of corresponding GTG then; This sequential control circuit is to be coupled to this gate drive circuit, gives this gate drive circuit in order to produce an output enable signal, and a latch data signal; Reaching this pixel delayed charging circuit is to be coupled to this sequential control circuit and this source electrode drive circuit, in order to according to this output enable signal and this latch data signal, produces a new latch data signal and gives this source electrode drive circuit.
Another object of the present invention provides a kind of pixel delayed charging circuit that is applied in order to the liquid crystal display systems that improves irregular colour.This delay charging circuit comprises one first flip-flop, one second flip-flop and a mutual exclusion lock.This first flip-flop is in order to the positive edge of basis from the latch data signal of a sequential control circuit of this liquid crystal display systems, produces one first latch data signal; This second flip-flop is in order to the negative edge of basis from the output enable signal of this sequential control circuit, produces one first output enable signal; Reaching this mutual exclusion lock is to be coupled to this first flip-flop and this second flip-flop, in order to according to this first latch data signal and this first output enable signal, produces the one source pole driving circuit that a new latch data signal is given this liquid crystal display systems.
Provided by the present invention a kind of in order to the liquid crystal display systems that improves irregular colour and be applied to pixel delayed charging circuit in order to the liquid crystal display systems that improves irregular colour, be to utilize this pixel delayed charging circuit to produce a new latch data signal, and the negative edge of this new latch data signal is delayed appearance than the negative edge of a latch data signal.So, guarantee that the thin film transistor (TFT) of a m-1 level sweep trace Gm-1 has all cut out,, therefore can solve the problem of this liquid crystal panel irregular colour just to the charging of the pixel on the m level sweep trace Gm.
Description of drawings
Fig. 1 illustrates that the output pulse wave of gate drive circuit is the synoptic diagram of electronegative potential when the output enable signal activation.
Fig. 2 is that explanation is because the phenomenon of weak noble potential causes the wrong synoptic diagram of pixel charging on the liquid crystal panel.
Fig. 3 is that one embodiment of the invention illustrate the synoptic diagram in order to the liquid crystal display systems that improves irregular colour.
Fig. 4 is the synoptic diagram of the relation between explanation latch data signal, output enable signal, the first latch data signal, first output enable signal and the new latch data signal.
Fig. 5 is the new latch data signal of explanation is delayed charging by pixel a synoptic diagram.
Fig. 6 is that another embodiment of the present invention explanation is applied to the synoptic diagram in order to the pixel delayed charging circuit of the liquid crystal display systems that improves irregular colour.
Fig. 7 is the truth table of explanation mutual exclusion lock.
[primary clustering symbol description]
300 liquid crystal display systemss
302 liquid crystal panels
304 gate drive circuits
306 source electrode drive circuits
308 sequential control circuits
310,600 pixel delayed charging circuits
3102,602 first flip-flops
3104,604 second flip-flops
3106,606 mutual exclusion locks
3022 pixels
3024 switches
CLK frequency input end
The D input end
The Q output terminal
LD latch data signal
The OE output enable signal
The LD1 first latch data signal
OE1 first output enable signal
The new latch data signal of NLD
G1, G2, G3, G4, G5 sweep trace
Gm-1、Gm
The VGL electronegative potential
The VGH noble potential.
?
Embodiment
Please refer to Fig. 3, Fig. 3 is that one embodiment of the invention illustrate the synoptic diagram in order to the liquid crystal display systems 300 that improves irregular colour.Liquid crystal display systems 300 comprises a liquid crystal panel 302, a gate drive circuit 304, one source pole driving circuit 306, a sequential control circuit 308 and a pixel delayed charging circuit 310.Liquid crystal panel 302 has a plurality of pixels 3022; Gate drive circuit 304 be in order to control a plurality of output scanning lines G1, G2 ..., Gm-1, Gm ... the output pulse wave, wherein a plurality of output scanning lines G1, G2 ..., Gm-1, Gm ... in the output pulse wave of each sweep trace be the open and close that are coupled to the switch 3024 of pixel 3022 in order to control, the switch 3024 that wherein is coupled to pixel 3022 is to be a thin film transistor (TFT) (thin film transistor); Source electrode drive circuit 306 is in order to convert a video data to a data voltage, according to data voltage corresponding pixel 3022 to be discharged and recharged the voltage of corresponding GTG then; Sequential control circuit 308 is to be coupled to gate drive circuit 304, give gate drive circuit 304 in order to produce an output enable signal OE, and a latch data signal LD, wherein output enable signal OE is the interval in order to the output pulse wave activation of adjusting one scan line and adjacent scanning lines; Pixel delayed charging circuit 310 is to be coupled to sequential control circuit 308 and source electrode drive circuit 306, in order to output enable signal OE and the latch data signal LD according to sequential control circuit 308, produces a new latch data signal NLD and gives source electrode drive circuit 306.
Pixel delayed charging circuit 310 comprises one first flip-flop 3102, one second flip-flop 3104 and a mutual exclusion lock 3106, and wherein first flip-flop 3102 and second flip-flop 3104 are to be D type flip-flop.Pixel delayed charging circuit 310 is to be coupled to sequential control circuit 308 and source electrode drive circuit 306.When latch data signal LD inputs to first flip-flop 3102, first flip-flop 3102 is in order to the positive edge according to latch data signal LD, produce one first latch data signal LD1, that is when latch data signal LD is logic high potential 1 by logic low potential 0 transition, first flip-flop, 3102 outputs, the first latch data signal LD1 is a logic high potential 1, and it is positive edge when triggering that the state of logic high potential 1 is maintained until next time the latch data signal always, and it is logic low potential 0 that the first latch data signal LD1 just understands transition.In like manner, because second flip-flop 3104 triggers flip-flop for negative edge, so when output enable signal OE is logic low potential 0 by logic high potential 1 transition, second flip-flop, 3104 outputs, one first output enable signal OE1 is a logic high potential 1, that is when output enable signal OE is logic low potential 0 by logic high potential 1 transition, second flip-flop, 3104 outputs, the first output enable signal OE1 is a logic high potential 1, and the state of logic high potential 1 is maintained until when output enable signal OE triggers for negative edge next time always, and it is logic low potential 0 that the first output enable signal OE1 just understands transition.Mutual exclusion lock 3106 is to be coupled to first flip-flop 3102 and second flip-flop 3104, in order to according to the first latch data signal LD1 and the first output enable signal OE1, produces new latch data signal NLD and gives source electrode drive circuit 306.
Please refer to Fig. 4 and Fig. 5, Fig. 4 is the synoptic diagram of the relation between explanation latch data signal LD, output enable signal OE, the first latch data signal LD1, the first output enable signal OE1 and the new latch data signal NLD, and Fig. 5 is that the new latch data signal NLD of explanation allows pixel 3022 delay the synoptic diagram of charging.As shown in Figure 4, because first flip-flop 3102 is to be that positive edge triggers flip-flop, so the first latch data signal LD1 is transformed into logic high potential 1 according to the positive cause logic low potential 0 of latch data signal LD.In like manner, the first output enable signal OE1 is transformed into logic high potential 1 according to the negative cause logic low potential 0 of output enable signal OE.Because new latch data signal NLD is the output signal for mutual exclusion lock 3106, so when two input signals (the first latch data signal LD1 and the first output enable signal OE1) of mutual exclusion lock 3106 are during for opposite logic current potential, new latch data signal NLD is only logic high potential 1.As shown in Figure 5, the negative edge of new latch data signal NLD is delayed appearance than the negative edge of latch data signal LD, so can avoid the weak noble potential of m-1 level sweep trace Gm-1.So, when the negative edge of the new latch data signal NLD of source electrode drive circuit basis begins 3022 chargings of the pixel on the m level sweep trace Gm, can't be to pixel 3022 chargings of m-1 level sweep trace Gm-1.
Please refer to Fig. 6, Fig. 6 is that another embodiment of the present invention explanation is applied to the synoptic diagram in order to the pixel delayed charging circuit 600 of the liquid crystal display systems that improves irregular colour.Pixel delayed charging circuit 600 comprises one first flip-flop 602, one second flip-flop 604 and a mutual exclusion lock 606.Import the frequency input end CLK of first flip-flop 602 from the latch data signal LD of sequential control circuit 308, and the negative output terminal of first flip-flop 602
D couples with input end.Therefore, first flip-flop 602 is that its output terminal Q exports the first latch data signal LD1 for positive edge triggers flip-flop.Input to the negative frequency input end of second flip-flop 604 from the output enable signal OE of sequential control circuit 308
, and the negative output terminal of second flip-flop 604
D couples with input end.Therefore, second flip-flop 604 is that its output terminal Q exports the first output enable signal OE1 for negative edge triggers flip-flop.Please refer to Fig. 7, Fig. 7 is the truth table of explanation mutual exclusion lock 606.And the relation between latch data signal LD, output enable signal OE, the first latch data signal LD1, the first output enable signal OE1 and the new latch data signal NLD please refer to the 4th figure.In addition, pixel delayed charging circuit 600 and pixel delayed charging circuit 310 functions are identical, do not repeat them here.
In sum, provided by the present invention in order to improve the liquid crystal display systems of irregular colour, be to utilize the pixel delayed charging circuit to produce new latch data signal, and the negative edge of new latch data signal is delayed appearance than the negative edge of latch data signal.So, guarantee that the thin film transistor (TFT) of m-1 level sweep trace Gm-1 all has been fully closed,, therefore can solve the problem of liquid crystal panel irregular colour just to the charging of the pixel on the m level sweep trace Gm.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (9)
1. a liquid crystal display systems is characterized in that, comprises:
One liquid crystal panel has a plurality of pixels;
One gate drive circuit, in order to control the output pulse wave of a plurality of output scanning lines, wherein the output pulse wave of each sweep trace is the open and close that are coupled to the switch of a pixel in order to control;
The one source pole driving circuit in order to convert a video data to a data voltage, discharges and recharges corresponding pixel according to this data voltage the voltage of corresponding GTG then;
One sequential control circuit is coupled to this gate drive circuit, gives this gate drive circuit in order to produce an output enable signal, and a latch data signal; And
One pixel delayed charging circuit is coupled to this sequential control circuit and this source electrode drive circuit, in order to according to this output enable signal and this latch data signal, produces a new latch data signal and gives this source electrode drive circuit.
2. liquid crystal display systems according to claim 1 is characterized in that, described pixel delayed charging circuit comprises:
One first flip-flop, the positive edge in order to according to this latch data signal produces one first latch data signal;
One second flip-flop, the negative edge in order to according to this output enable signal produces one first output enable signal; And
One mutual exclusion lock is coupled to this first flip-flop and this second flip-flop, in order to according to this first latch data signal and this first output enable signal, produces this new latch data signal.
3. liquid crystal display systems according to claim 2 is characterized in that: described first flip-flop and this second flip-flop are to be D type flip-flop.
4. liquid crystal display systems according to claim 1 is characterized in that: described output enable signal is the interval in order to the output pulse wave activation of adjusting one scan line and adjacent scanning lines.
5. liquid crystal display systems according to claim 1 is characterized in that: the negative edge of described new latch data signal must be before the positive edge of the output pulse wave of this sweep trace.
6. liquid crystal display systems according to claim 1 is characterized in that: described source electrode drive circuit is according to this data voltage, this new latch data signal and the switch open relevant with this pixel, to this pixel charging.
7. liquid crystal display systems according to claim 1 is characterized in that: the switch that wherein is coupled to this pixel is a thin film transistor (TFT).
8. the pixel delayed charging circuit of a liquid crystal display systems is characterized in that, this delay charging circuit comprises:
One first flip-flop in order to the positive edge of basis from a latch data signal of a sequential control circuit of this liquid crystal display systems, produces one first latch data signal;
One second flip-flop in order to the negative edge of basis from an output enable signal of this sequential control circuit, produces one first output enable signal; And
One mutual exclusion lock is coupled to this first flip-flop and this second flip-flop, in order to according to this first latch data signal and this first output enable signal, produces the one source pole driving circuit that a new latch data signal is given this liquid crystal display systems.
9. pixel delayed charging circuit according to claim 8 is characterized in that: described first flip-flop and this second flip-flop are D type flip-flops.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010275170 CN101944343B (en) | 2010-09-07 | 2010-09-07 | Liquid crystal display system and pixel delay charging circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010275170 CN101944343B (en) | 2010-09-07 | 2010-09-07 | Liquid crystal display system and pixel delay charging circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101944343A true CN101944343A (en) | 2011-01-12 |
| CN101944343B CN101944343B (en) | 2012-09-26 |
Family
ID=43436307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010275170 Expired - Fee Related CN101944343B (en) | 2010-09-07 | 2010-09-07 | Liquid crystal display system and pixel delay charging circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101944343B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110349546A (en) * | 2018-04-04 | 2019-10-18 | 中华映管股份有限公司 | Display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002032048A (en) * | 2000-05-09 | 2002-01-31 | Sharp Corp | Picture display device and electronic apparatus using the same |
| KR20050068324A (en) * | 2003-12-30 | 2005-07-05 | 엘지.필립스 엘시디 주식회사 | Gate driver, liquid crystal display and driving method thereof |
| CN1674441A (en) * | 2004-03-23 | 2005-09-28 | 联咏科技股份有限公司 | Source electrode drive circuit, latch voltage bit quasi converter and high voltage positive and negative device |
-
2010
- 2010-09-07 CN CN 201010275170 patent/CN101944343B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002032048A (en) * | 2000-05-09 | 2002-01-31 | Sharp Corp | Picture display device and electronic apparatus using the same |
| KR20050068324A (en) * | 2003-12-30 | 2005-07-05 | 엘지.필립스 엘시디 주식회사 | Gate driver, liquid crystal display and driving method thereof |
| CN1674441A (en) * | 2004-03-23 | 2005-09-28 | 联咏科技股份有限公司 | Source electrode drive circuit, latch voltage bit quasi converter and high voltage positive and negative device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110349546A (en) * | 2018-04-04 | 2019-10-18 | 中华映管股份有限公司 | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101944343B (en) | 2012-09-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104778928B (en) | A kind of shift register, gate driver circuit, display floater and display device | |
| CN103680386B (en) | For GOA circuit and the display device of flat pannel display | |
| USRE49782E1 (en) | Shift register and driving method thereof gate driving circuit and display apparatus | |
| CN103680451B (en) | For GOA circuit and the display device of liquid crystal display | |
| CN101320171B (en) | LCD and method for improving power-off ghost | |
| CN104700803B (en) | Shifting register, grid drive circuit, display panel and display device | |
| CN107958656B (en) | GOA circuit | |
| EP3086312B1 (en) | Shift register unit, gate drive circuit and display device | |
| CN102651239B (en) | Shift register, driver circuit and display device | |
| CN107154234B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN104409056B (en) | Scanning drive circuit | |
| CN104282282B (en) | Shift register, driving method, gate driving circuit and display device | |
| CN104464628A (en) | Shifting register unit, driving method of shifting register unit, grid drive circuit and display device | |
| CN102522070B (en) | Control circuit for eliminating glittering and shutdown ghosting phenomena of thin film field effect transistor | |
| CN104835442A (en) | Shifting register and drive method thereof, gate drive circuit and display device | |
| CN104517575A (en) | Shifting register and level-transmission gate drive circuit | |
| US20090256832A1 (en) | Method and a device for driving liquid crystal display | |
| CN103514840A (en) | Integrated gate driving circuit and liquid crystal panel | |
| US9703416B2 (en) | Touch circuit, touch panel and display apparatus | |
| CN100514404C (en) | Electric charge sharing apparatus for display panel | |
| CN109559706A (en) | Display driver circuit and display device | |
| JP2018530779A (en) | GOA circuit, driving method thereof, and liquid crystal display | |
| CN104849891A (en) | Liquid crystal display device | |
| CN112053655A (en) | GOA circuit and display panel | |
| CN110782940A (en) | Shift register unit, gate drive circuit, array substrate and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170810 Address after: Third, fourth floor, 1 floor, 6 West Road, Mawei West Road, Mawei District, Fujian, Fuzhou Co-patentee after: Chunghwa Picture Tubes Ltd. Patentee after: CPT DISPLAY TECHNOLOGY (SHENZHEN)CO., LTD. Address before: No. 1 Xingye Road, Mawei science and technology zone, Fujian, Fuzhou Co-patentee before: Chunghwa Picture Tubes Ltd. Patentee before: Fujian Huaying Display Technology Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120926 Termination date: 20190907 |