CN101944315A - Source driver and display employing source driver - Google Patents
Source driver and display employing source driver Download PDFInfo
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- CN101944315A CN101944315A CN2009101402449A CN200910140244A CN101944315A CN 101944315 A CN101944315 A CN 101944315A CN 2009101402449 A CN2009101402449 A CN 2009101402449A CN 200910140244 A CN200910140244 A CN 200910140244A CN 101944315 A CN101944315 A CN 101944315A
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Abstract
The invention discloses a source driver, which comprises a receiver and a channel. The receiver is used for receiving a digital signal at an input node so as to generate a received signal at an output node, and comprises a first switch, a second switch and a voltage-limiting circuit, wherein the first switch selectively connects the output node of the receiver to first reference voltage based on the digital signal; the second switch connects the output node of the receiver to second reference voltage based on the digital signal; the voltage-limiting circuit is coupled between the input node and the output node of the receiver and is used for limiting the voltage level of the input node of the receiver; and the channel generates driving voltage based on the received signal.
Description
Technical field
The present invention relates to forwarder and receiver, especially be applied to the forwarder and the receiver of display.
Background technology
Please refer to Fig. 1, Fig. 1 is known transistors-transistor logic (transistor-transistor logic, TTL) synoptic diagram of interface 100.As shown in Figure 1, TTL interface 100 includes a forwarder 110 and a receiver 120, and wherein receiver 120 receives a digital signal via a single data line L.Yet concerning TTL interface 100, generally speaking this digital signal needs to have the bigger amplitude of oscillation (swing), and electromagnetic interference (EMI) (electronic-magnetic interference EMI) can be therefore comparatively serious, causes its frequency that can operate to be restricted.
But in order to solve the problem of electromagnetic interference (EMI) and operation frequency in the TTL interface 100, (reduced swing differential signaling, RSDS) therefore circuit is suggested in a kind of low-swing differential signal transmission.Fig. 2 is the synoptic diagram of the known circuits 200 of application low-swing differential signal transmission.As shown in Figure 2, circuit 200 includes a forwarder 210 and a receiver 220, and wherein receiver 220 is coupled in forwarder 210 via a pair of single data line.Because circuit 200 is less in the amplitude of oscillation that this is transmitted on to single data line, so but on electromagnetic interference (EMI) and operation frequency, have preferably and show.Yet, current source IS1 in the forwarder 210 and IS2 need provide bigger electric current (about 2 milliamperes) to this on the single data line, thereby cause a large amount of power consumption.Moreover circuit 200 employed single data line numbers are twices of TTL interface, and then have increased cost of manufacture.
Summary of the invention
One of purpose of the present invention is to provide a kind of display that includes time schedule controller and one source pole driver, to address the above problem, wherein but this display has less electromagnetic interference (EMI) and preferable operation frequency, and has lower circuit layout complexity between this time schedule controller and this source electrode driver.
According to one embodiment of the present of invention, disclose a kind of source electrode driver, this source electrode driver includes a receiver and a passage, and this receiver is used for receiving a digital signal to produce a received signal at an output node at an input node.This receiver includes one first switch, a second switch, a pressure limiting circuit.This first switch optionally is connected to first reference voltage with this output node of this receiver based on this digital signal.This second switch optionally is connected to second reference voltage with this output node of this receiver based on this digital signal.This pressure limiting circuit is coupled between this input node and this output node of this receiver, in order to the voltage quasi position of this input node of limiting this receiver.This passage produces driving voltage based on this received signal.
According to another embodiment of the present invention, disclose a kind of display.This display includes time schedule controller and one source pole driver.This time schedule controller receives an input signal and produces a digital signal, and this source electrode driver includes a receiver, be coupled to this output node of this reverser via a single data line, in order to receive this digital signal from this time schedule controller via this single data line.This time schedule controller includes a reverser, one first current source and one second current source.This reverser has an input node that is used for receiving this input signal, and produces this digital signal at an output node.This first current source is supplied first power supply node that one first electric current is given this reverser.This second current source is supplied the second source node that one second electric current is given this reverser.
Description of drawings
Fig. 1 is the synoptic diagram of known transistors-transistor logic interface.
Fig. 2 is the synoptic diagram of known low-swing differential signal circuit.
Fig. 3 is the forwarder of the time schedule controller that is applied to display in one embodiment of the invention and the synoptic diagram of the receiver of the source electrode driver that is applied to display.
Fig. 4 is the synoptic diagram of another embodiment of pressure limiting circuit shown in Figure 3.
Fig. 5 is the synoptic diagram of another embodiment again of pressure limiting circuit shown in Figure 3.
Embodiment
In instructions and follow-up claims, used some vocabulary to censure specific element.Those skilled in the art should understand, and hardware manufacturer may be called same element with different nouns.This instructions and follow-up claims are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be an open language mentioned " comprising " in the middle of instructions and follow-up claims in the whole text, so should be construed to " comprise but be not limited to ".In addition, " couple " speech and comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to one second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly by other devices or connection means if describe one first device in the literary composition.
Please refer to Fig. 3, Fig. 3 is the forwarder 310 in one embodiment of the invention and the synoptic diagram of a receiver 320.Forwarder 310 can be used for the time schedule controller in the display, and receiver 310 then can be used for the one source pole driver in this display.As shown in Figure 3, forwarder 310 includes a reverser 312 and a plurality of power supply I
1With I
2, wherein reverser 312 includes a P transistor npn npn M
P1With a N transistor npn npn M
N1Current source I
1Supply with one first electric current to the power supply node in the reverser 312, and current source I
2Then supply with one second electric current to another power supply node in the reverser 312.
Receiver 320 includes one first switch M
P2, a second switch M
N2An and pressure limiting circuit 322.In this embodiment, the first switch M
P2Be to realize with a P transistor npn npn, and second switch M
N2Be to realize with a N transistor npn npn; In addition, pressure limiting circuit 322 includes the N transistor npn npn M that a diode mode connects (diode-connected)
N3The P transistor npn npn M that is connected with a diode mode
P3Forwarder 310 is to couple via a single data line and receiver 320, and a resistance R shown in Figure 3
LoadWith a capacitor C
LoadRepresent an equivalent dead resistance and an equivalent stray capacitance of this single data line respectively.
In the middle of the running of forwarder 310 and receiver 320, reverser 312 is at an input node N
IN-- TXLast reception one input signal V
i, and at output node N
OUT-TXLast generation one digital signal V
Dig, and digital signal V
DigThen be sent to an input node N in the receiver 320 via this single data line
IN-RXThe first switch M
P2Based on digital signal V
DigCome optionally an output node N with receiver 320
OUT-RXBe connected to one first reference voltage V
DD-RX, and second switch M
N2Based on digital signal V
DigCome optionally output node N with receiver 320
OUT-RXBe connected to one second reference voltage GND, and output node N
OUT-RXOn can produce a received signal V
OutAt the same time, pressure limiting circuit 322 can limit the input node N of receiver 320
IN-RXVoltage quasi position.
Receiver 320 also optionally (optionally) comprises a reverser 324 with received signal V
OutOppositely to produce a reverse received signal V
Outb, last, the passage in this source electrode driver is just based on reverse received signal V
OutbProduce driving voltage.
For instance, as input signal V
iWhen being in " 0 " logic state (electronegative potential), by forwarder 310 to the current path of receiver 320 by current source I
1Beginning is then through P transistor npn npn M
P1, this single data line, meet the input node N of putting device 320
IN-RX, N transistor npn npn M
N3, N transistor npn npn M
N2, and finally enter a node with second reference voltage GND, and at this moment, the input node N of receiver 320
IN-RXVoltage quasi position be N transistor npn npn M
N3A drain electrode-source voltage V
DSWith N transistor npn npn M
N2A grid-source voltage V
GSSummation, and this voltage quasi position is less than a service voltage V of forwarder 310
DD-TX, in addition, the output node N of receiver 320
OUT-RXCan be in lower voltage quasi position.Transistor M
N3With M
N2Critical voltage (threshold voltage) can be via suitable design so that input node N
IN-RXOn voltage quasi position enough big so that the following transistor M that closes of state at this moment
P2And in order to avoid transistor M
P2With M
N2Be switched on simultaneously.
Similarly, as input signal V
iWhen being in " 1 " logic state (noble potential), by forwarder 310 to the current path of receiver 320 by P transistor npn npn M
P2Beginning, then the output node N of process receiver 320
OUT-RX, P transistor npn npn M
P3, meet the input node N of putting device 320
IN-RX, this single data line, N transistor npn npn M
N1, current source I
2, and finally enter earth terminal (ground), and at this moment, the input node N of receiver 320
IN-RXVoltage quasi position be P transistor npn npn M
P2A drain electrode-source voltage V
DSWith P transistor npn npn M
P3A grid-source voltage V
GSThe summation and the first reference voltage V
DD-RXPoor, and this voltage quasi position is greater than the ground voltage of forwarder 310, in addition, the output node N of receiver 320
OUT-RXCan be in the accurate position of higher voltage.Transistor M
P3With M
P2Critical voltage can be via suitable design so that input node N
IN-RXOn voltage quasi position enough little so that the following transistor M that closes of state at this moment
N2And avoid transistor M
P2With M
N2Be switched on simultaneously.
For instance, suppose V
DD-RXWith V
DD-TXBe all 1.8 volts, when then the amplitude of oscillation of digital signal is about 1 volt among the present invention (0.4V-1.4V), the amplitude of oscillation (0V-1.8V) of digital signal in the TTL interface 100.Therefore, but display proposed by the invention has preferable performance on electromagnetic interference (EMI) and operation frequency, in addition, and owing to receiver 320 is connected with forwarder 310 via this single data line, so fairly simple and uncomplicated on the circuit layout.
In addition, in the middle of circuit 200, the current source I of forwarder 210
S1With I
S2Need the more electric current (about 2 milliamperes) of supply to give these data lines keeping the fixed voltage of these data lines, and in the present invention, this fixed voltage (digital voltage V
DigA medium voltage) itself produced so current source I by forwarder 310 and receiver 320
S1With I
S2Only needing to supply with less current gives these data lines to keep the fixed voltage of these data lines.
It should be noted that in the present invention forwarder 310 is applied in the time schedule controller, yet so design only is the usefulness of explanation, is not the implementation that is used for limiting time schedule controller.For example, forwarder 310 can be implemented between any control circuit and the source electrode driver, and the variation in these designs still belongs within the category of the present invention.
In addition, in the present embodiment, receiver 320 includes reverser 324, and the passage in the source electrode driver can be based on reverse received signal V
OutbProduce driving voltage, yet in other embodiment of the present invention, reverser 324 can remove in receiver 320, and the passage in the source electrode driver is just based on received signal V
OutProduce driving voltage.
Fig. 4 and Fig. 5 are the synoptic diagram of other embodiment of pressure limiting circuit of the present invention.In Fig. 4, pressure limiting circuit 400 includes one the one N transistor npn npn M
N4With one the 2nd N transistor npn npn M
N5, a N transistor npn npn M wherein
N4With the 2nd N transistor npn npn M
N5The input node N that connects and be coupled to receiver 320 in the diode mode
IN-RXWith output node N
OUT-RXBetween, a N transistor npn npn M
N4Grid be connected in the input node N of receiver 320
IN-RX, and the 2nd N transistor npn npn M
N5Grid be connected in the output node N of receiver 320
OUT-RXIn Fig. 5, pressure limiting circuit 500 includes one the one P transistor npn npn M
P4With one the 2nd P transistor npn npn M
P5, a P transistor npn npn M wherein
P4With the 2nd P transistor npn npn M
P5The input node N that connects and be coupled to receiver 320 in the diode mode
IN-RXWith output node N
OUT-RXBetween, a P transistor npn npn M
P4Grid be connected in the input node N of receiver 320
IN-RX, and the 2nd P transistor npn npn M
P5Grid be connected in the output node N of receiver 320
OUT-RX
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claims of the present invention all should belong to covering scope of the present invention.
Claims (15)
1. source electrode driver includes:
One receiver is used for receiving a digital signal to produce a received signal at an output node at an input node, and this receiver includes:
One first switch is in order to optionally to be connected to first reference voltage with this output node of this receiver based on this digital signal;
One second switch is in order to optionally to be connected to second reference voltage with this output node of this receiver based on this digital signal; And
One pressure limiting circuit is coupled between this input node and this output node of this receiver, in order to the voltage quasi position of this input node of limiting this receiver; And
One passage is in order to produce driving voltage based on this received signal.
2. source electrode driver according to claim 1, wherein this receiver also includes:
One reverser is coupled between this output node and this passage.
3. source electrode driver according to claim 1, wherein this pressure limiting circuit includes:
The transistor that one diode mode connects is coupled between this input node and this output node of this receiver.
4. source electrode driver according to claim 1, wherein this pressure limiting circuit includes:
One P transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of this P transistor npn npn is connected to this input node of this receiver; And
One N transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of this N transistor npn npn is connected to this input node of this receiver.
5. source electrode driver according to claim 1, wherein this pressure limiting circuit includes:
One the one N transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of a N transistor npn npn is connected to this input node of this receiver; And
One the 2nd N transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of the 2nd N transistor npn npn is connected to this output node of this receiver.
6. source electrode driver according to claim 1, wherein this pressure limiting circuit includes:
One the one P transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of a P transistor npn npn is connected to this input node of this receiver; And
One the 2nd P transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of the 2nd P transistor npn npn is connected to this output node of this receiver.
7. source electrode driver according to claim 1, wherein this first switch is a P transistor npn npn, this second switch is a N transistor npn npn, and this first reference voltage is greater than this second reference voltage.
8. display includes:
Time schedule controller produces a digital signal in order to receive an input signal, and this time schedule controller includes:
One reverser has an input node that is used for receiving this input signal, and produces this digital signal at an output node;
One first current source is in order to supply first power supply node that one first electric current is given this reverser; And
One second current source is in order to supply the second source node that one second electric current is given this reverser; And
The one source pole driver, it includes a receiver, and it is coupled to this output node of this reverser via a single data line, in order to receive this digital signal via this single data line from this time schedule controller.
9. display according to claim 8, wherein this receiver receives a digital signal producing a received signal at an output node at an input node, and this receiver includes:
One first switch is in order to optionally to be connected to first reference voltage with this output node of this receiver based on this digital signal;
One second switch is in order to optionally to be connected to second reference voltage with this output node of this receiver based on this digital signal; And
One pressure limiting circuit is coupled between this input node and this output node of this receiver, in order to the voltage quasi position of this input node of limiting this receiver;
Wherein this source electrode driver also includes a passage, in order to produce driving voltage based on this received signal.
10. display according to claim 9, wherein this receiver also includes:
One reverser is coupled between this output node and this passage.
11. display according to claim 9, wherein this pressure limiting circuit includes:
The transistor that one diode mode connects is coupled between this input node and this output node of this receiver.
12. display according to claim 9, wherein this pressure limiting circuit includes:
One P transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of this P transistor npn npn is connected to this input node of this receiver; And
One N transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of this N transistor npn npn is connected to this input node of this receiver.
13. display according to claim 9, wherein this pressure limiting circuit includes:
One the one N transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of a N transistor npn npn is connected to this input node of this receiver; And
One the 2nd N transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of the 2nd N transistor npn npn is connected to this output node of this receiver.
14. display according to claim 9, wherein this pressure limiting circuit includes:
One the one P transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of a P transistor npn npn is connected to this input node of this receiver; And
One the 2nd P transistor npn npn is coupled between this input node and this output node of this receiver, and wherein the grid of the 2nd P transistor npn npn is connected to this output node of this receiver.
15. display according to claim 9, wherein this first switch is a P transistor npn npn, and this second switch is a N transistor npn npn, and this first reference voltage is greater than this second reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910140244.9A CN101944315B (en) | 2009-07-09 | 2009-07-09 | Source driver and display employing source driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910140244.9A CN101944315B (en) | 2009-07-09 | 2009-07-09 | Source driver and display employing source driver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101944315A true CN101944315A (en) | 2011-01-12 |
| CN101944315B CN101944315B (en) | 2014-04-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910140244.9A Expired - Fee Related CN101944315B (en) | 2009-07-09 | 2009-07-09 | Source driver and display employing source driver |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI636443B (en) * | 2013-12-05 | 2018-09-21 | 南韓商三星顯示器有限公司 | Trace structure for improved electrical signaling |
| CN111831046A (en) * | 2019-04-16 | 2020-10-27 | 联咏科技股份有限公司 | Output stage circuit and voltage stabilizer thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5621342A (en) * | 1995-10-27 | 1997-04-15 | Philips Electronics North America Corporation | Low-power CMOS driver circuit capable of operating at high frequencies |
| US5929656A (en) * | 1997-05-16 | 1999-07-27 | Motorola, Inc. | Method and apparatus for driving a capacitive display device |
| US20090073148A1 (en) * | 2007-07-03 | 2009-03-19 | Tpo Displays Corp. | Level shifter, interface driver circuit and image display system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2814905B2 (en) * | 1993-12-28 | 1998-10-27 | 日本電気株式会社 | Driver / receiver circuit |
| JP4082398B2 (en) * | 2004-09-07 | 2008-04-30 | セイコーエプソン株式会社 | Source driver, electro-optical device, electronic apparatus, and driving method |
| US7327297B2 (en) * | 2006-06-30 | 2008-02-05 | Himax Technologies Limited | Source driver of liquid crystal display and the driving method |
-
2009
- 2009-07-09 CN CN200910140244.9A patent/CN101944315B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5621342A (en) * | 1995-10-27 | 1997-04-15 | Philips Electronics North America Corporation | Low-power CMOS driver circuit capable of operating at high frequencies |
| US5929656A (en) * | 1997-05-16 | 1999-07-27 | Motorola, Inc. | Method and apparatus for driving a capacitive display device |
| US20090073148A1 (en) * | 2007-07-03 | 2009-03-19 | Tpo Displays Corp. | Level shifter, interface driver circuit and image display system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI636443B (en) * | 2013-12-05 | 2018-09-21 | 南韓商三星顯示器有限公司 | Trace structure for improved electrical signaling |
| CN111831046A (en) * | 2019-04-16 | 2020-10-27 | 联咏科技股份有限公司 | Output stage circuit and voltage stabilizer thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101944315B (en) | 2014-04-02 |
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Granted publication date: 20140402 Termination date: 20200709 |