CN101944003A - Flash memory device operation method and information storage system - Google Patents
Flash memory device operation method and information storage system Download PDFInfo
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- CN101944003A CN101944003A CN2009100545892A CN200910054589A CN101944003A CN 101944003 A CN101944003 A CN 101944003A CN 2009100545892 A CN2009100545892 A CN 2009100545892A CN 200910054589 A CN200910054589 A CN 200910054589A CN 101944003 A CN101944003 A CN 101944003A
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Abstract
The invention discloses a flash memory device operation method and an information storage system. The information storage system comprises a flash memory device which is coupled to a host computer, includes a plurality of operation states and comprises a controller, the controller includes an engine and a temporary storage register array, the engine includes a state machine logic circuit for converting these operation states, the temporary storage register array is used for providing state conversion information, wherein when the host computer receives a command, the engine reads the state conversion information of the temporary storage register array according to a first operation state in order to judge whether the command belongs to a plurality of legal commands corresponding to the first operation state, and the state machine logic circuit determines the conversion of the operation states according to the state conversion information, i.e. from the first operation state to a second operation state, in order to respond to the command.
Description
Technical field
The invention relates to flash memory, particularly relevant for a kind of flash memory device method of operating and data storage system that be applicable to flash memory.
Background technology
Because flash memory can keep the data that has stored under the situation of not power supply, and have advantages such as programming (program) time weak point, low power consumption, therefore, widely as the Storage Media of various electronic products such as mobile phone, digital camera, PDA(Personal Digital Assistant), notebook computer, for example: storage card, dish etc. with oneself.
Generally speaking, when the flash memory device with flash memory (as storage card) was coupled to main frame (as mobile phone), main frame can be operated flash memory device by defined various command in the transmission memory card specifications (specification).That is to say that the controller in the flash memory device is the order that sends according to main frame, changes the mode of operation of flash memory device, in order to carry out operations such as parameter setting or data transmission.Traditionally, can in flash memory device, set up a state machine (state machine), in order to carry out in the specification the conversion process of the various command that defines and respective operations state.Further, can use similarly is the logical circuit that instruments such as Verilog dispose required state machine, and becomes concrete integrated circuit when flow (tape-out).
But, after flow, fixing integrated circuit also can't directly be revised with the memory card specifications change.In in the case, must use Verilog will will revise in the previous logic state machine circuit that disposes of part introducing earlier, and then flow is once again.This inelastic mode not only quite expends time in, and increases the expenditure cost of hardware flow simultaneously.
Therefore, need a kind of flash memory device method of operating and flash memory device design of improvement, can flexibly make amendment, need not rearranging logic circuit and flow in response to the memory card specifications change.
Summary of the invention
One embodiment of the invention provide a kind of flash memory device, and this flash memory device is coupled to a main frame and has a plurality of modes of operation, and this flash memory device comprises a controller, and it has an engine and a working storage array.This engine has a logic state machine circuit, in order to change these modes of operation.This working storage array is in order to provide state exchange information.When receiving an order from this main frame, this engine reads this state exchange information of this working storage array according to one first mode of operation, whether belongs to the pairing a plurality of lawful orders of this first mode of operation in order to judge this order.In addition, this logic state machine circuit is converted to one second mode of operation according to the conversion of this state exchange information decision mode of operation from this first mode of operation, with in response to this order.
On the other hand, in another embodiment, provide a kind of flash memory device method of operating.This flash memory device is coupled to a main frame and has a plurality of modes of operation.This flash memory device method of operating comprises the following steps: to receive an order from this main frame; According to one first mode of operation, read a working storage array with state exchange information, whether belong to the pairing a plurality of lawful orders of this first mode of operation in order to judge this order; And when this order belongs to pairing these lawful orders of this first mode of operation, this state exchange information according to this working storage array, the conversion of the one logic state machine circuit decision mode of operation of this flash memory device, in order to being converted to one second mode of operation, with in response to this order from this first mode of operation.
On the other hand, in another embodiment, provide a kind of data storage system, comprise a main frame and a flash memory device.This main frame transmits a plurality of orders, in order to the access data.This flash memory device is coupled to this main frame and has a plurality of modes of operation.This flash memory device is from this main frame reception one order, according to one first mode of operation, read a working storage array with state exchange information, in order to judge whether this order belongs to the pairing a plurality of lawful orders of this first mode of operation and when this order belongs to pairing these lawful orders of this first mode of operation, one logic state machine circuit of this flash memory device decides the conversion of mode of operation according to this state exchange information of this working storage array, in order to being converted to one second mode of operation, with in response to this order from this first mode of operation.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 is the data storage system calcspar that shows according to the embodiment of the invention.
Fig. 2 is the part mode of operation transition synoptic diagram of the flash memory device of displayed map 1.
Fig. 3 is the employed state exchange information table of the flash memory device of displayed map 1.
Fig. 4 is the flash memory device flow chart that shows according to the embodiment of the invention.
The main element symbol description:
102～main frame; 10～data storage system;
104～flash memory device; 106～controller;
108～engine; 110～working storage array;
112～logic state machine circuit;
114～flash memory; 116～interface;
118～look-at-me; 120～microprocessing unit;
122～control signal; And
SRAM～static RAM.
Embodiment
Fig. 1 is data storage system 10 calcspars that show according to the embodiment of the invention.
As shown in Figure 1, data storage system 10 comprises main frame 102 and flash memory device 104.In an embodiment, main frame 102 can be portable apparatus, mobile phone for example, and the flash memory device 104 that is coupled to main frame 102 can be storage card, for example safe digital card (SD card).According to the specification of storage card, main frame 102 is sent to flash memory device 104 with a plurality of orders, in order to carry out the data transmission with flash memory device 104.Flash memory device 104 has a plurality of modes of operation, for example holding state, transmission data state, reception data state etc.In operation, when flash memory device 104 after main frame 102 receives order, just be converted to corresponding mode of operation.
Further, flash memory device 104 has controller 106 and flash memory 114.In Fig. 1, controller 106 comprises engine 108 and working storage array 110, and flash memory 114 is coupled to controller 106.In this embodiment, engine 108 has a logic state machine circuit 112, changes these modes of operation in order to the state exchange information that is provided according to working storage array 110.In an embodiment, working storage array 110 comprises a plurality of working storage elements (not shown), and sets up the content of these working storage elements in advance according to state exchange information.For example, can when flash memory device 104 electric power startings,, state exchange information be loaded into working storage array 110 from flash memory 114 by interface 116.So, when memory card specifications changes, during for example newly-increased the order, can revise state exchange information stored in the flash memory 114.Afterwards, when next electric power starting, the state exchange information after will upgrading again will further cooperate Fig. 2 and Fig. 3 to be described as follows among being loaded into working storage array 110 again from flash memory 114.
Fig. 2 is the part mode of operation transition synoptic diagram of the flash memory device 104 of displayed map 1.Fig. 3 is the flash memory device 104 employed state exchange information tables of displayed map 1.In an embodiment, the state exchange information table is to be stored in the flash memory 114 of Fig. 1.
With reference to figure 1 and Fig. 2, in this embodiment, flash memory device 104 has 5 kinds of modes of operation, but is not limited thereto, and is respectively holding state STBY, transmits data state DATA, receives data state RCV, transmission state TRAN and programming state PRG.In Fig. 3, state exchange information comprises that present mode of operation is pairing and receives lawful order and in response to next mode of operation of each lawful order.
For example, after flash memory device 104 received an order from this main frame, engine 108 was judged the present mode of operation of flash memory device 104 earlier.Suppose that flash memory device 104 operates among the transmission data state DATA at present, expression microprocessing unit 120 just reads flash memory 114 by interface 116, and the data of reading is temporary among the static RAM SRAM, is resent to main frame 102.Secondly, judge after the transmission data state DATA, engine 108 reads the state exchange information of working storage array 110, index 33 and 34 as shown in Figure 3.Then, engine 108 judges whether the order that is received belongs to the pairing lawful order of transmission data state DATA.That is to say that engine 108 judges whether the order that is received is the lawful order CMD13 of index 33 or the lawful order CMD12 of index 34.
In an embodiment, when the order of being assigned when main frame 102 was incorrect, flash memory device 104 can directly be ignored this order and not further process, and mode of operation remains unchanged.
Otherwise when the order that is received belonged to the pairing lawful order of transmission data state DATA, as the CMD12 of index 34, logic state machine circuit 112 was further according to index 34 next mode of operation of decision.That is, the mode of operation of flash memory device 104 is converted to transmission state TRAN from transmitting data state DATA, in order in response to the lawful order CMD12 that is received, as shown in Figure 2.
In addition, when being converted to transmission state TRAN, controller 106 will be responded to main frame 102 corresponding to the R1B that replys that transmits the data state DATA and the order that receives.In operation, can comply with required dissimilar replying, R1 as shown in Figure 3, R2, the R1B etc. of designing.For example, main frame sends CMD12, with so that flash memory 114 stops the transmission data, needs a period of time processing command CMD12 and reply R1B in order to respond main frame.
After it should be noted that the order that receives main frame 102, engine 108 can directly read the content of this working storage array 110 according to present mode of operation, and need not utilize the address to come the reading state transitional information, so can obtain minimum read waiting time.Thus, can satisfy the response time demand that general memory card specifications allows.Whether moreover these working storage elements in the working storage array 110 can side by side be read, be lawful order in order to the order of judging main frame 102.This one reads in parallel mode and can improve read performance further.
Particularly, at each mode of operation, can reserve extra index and field (reserved) in the state exchange information table of Fig. 3, index 3,25,35 as shown in Figure 3 etc. are to meet the needs of memory card specifications change.In some embodiment, also can flexibly adjust the extra index of reserving and field quantity at different modes of operation, for example the reservation quantity of transmission state TRAN is more.With reference to figure 3, suppose that each index need dispose 3 working storage space, 80 group indexes then need to dispose 240 working storage space.Afterwards,, corresponding working storage element is set again, in order to constitute working storage array 110 according to 240 working storage space requirement.
When conversion operation states, flash memory device 104 can further be carried out an interrupt operation.For example, suppose that flash memory device 104 operates among the transmission state TRAN, and receive the order CMD16 of main frame 102.In this embodiment, CMD16 is in order to set the block length of flash memory 114.With reference to the index 21 of figure 2 and Fig. 3, behind the reception order CMD16, the transmission state TRAN of flash memory device 104 remains unchanged, and engine 108 sends look-at-me 118 to microprocessing unit 120, in order to the setting district block length.In response to look-at-me 118, microprocessing unit 120 can be responded corresponding control signal 122.By way of example, when look-at-me 118 triggered microprocessing unit 120, control signal 122 can be set at busy (busy) state, and after the block length setting was finished, control signal 122 can be set at (ready) state of awaiting orders.In an embodiment, microprocessing unit 120 can be 8051 single-chip processors.
In an embodiment, when memory card specifications changed, for example based on considering and newly-increased pintle hook lock order on the safety, that is newly-increased order CMD39 shown in Figure 2 then needed flash memory 114 stored state exchange information are upgraded.Particularly, newly-increased order is added in the index of being reserved in the state exchange information table of Fig. 3 and field in regular turn.Then, when flash memory device 104 is given electricity again, microprocessing unit 120 first (the in-system programming that from flash memory 114, programme in the extraction system, ISP) sign indicating number, in order to confirming wherein whether to include the state exchange information of renewal, and the state exchange information after will upgrading, by interface 116, again among being loaded into working storage array 110 from flash memory 114, thus the setting state of update mode machine logical circuit 112.Thus, need not reconfigure the logical circuit of configuration state machine, also need not carry out flow again.
Fig. 4 is flash memory device method of operating 40 process flow diagrams that show according to the embodiment of the invention.
As shown in Figure 1, flash memory device 104 is to have a plurality of modes of operation.When flash memory device 104 was coupled to main frame 102, main frame 102 sent a series of access command, in order to carry out the data transmission with flash memory device 104.
Particularly, when flash memory device 104 electric power startings (step S402), controller 106 at first judges whether the state exchange information (step S404) of renewal.
In an embodiment, if state exchange information was modified, controller 106 is written into the state exchange information of having revised again from flash memory 114, in order to upgrade the content (step S406) of working storage array 110.Otherwise, if there is no, the state exchange information that is stored in flash memory 114 changes, then need not upgrade the content of working storage array 110.
Then, when flash memory device 104 receives the access command that main frames 102 are transmitted (step S408), this controller 106 is according to present mode of operation, transmission data state DATA as Fig. 2, read working storage array 110, in order to judge whether this access command belongs to the pairing lawful order of present mode of operation (step S410), as the lawful order CMD13 of index among Fig. 2 33 or the lawful order CMD 12 of index 34.
At this moment, when not belonging to pairing lawful order CMD13 of transmission data state DATA or CMD12 as if this access command, flash memory device 104 is ignored this access command.Otherwise, if this access command is lawful order, CMD12 for example, then logic state machine circuit 112 determines next mode of operation, and carries out corresponding data access operation (step S412) according to the state exchange information of mode of operation and working storage array 110 at present.For example, shown in the 2nd and 3 figure, the present mode of operation of flash memory device 104 is transmission data state DATA, and in response to the access command CMD12 of main frame, next mode of operation of flash memory device 104 is converted to transmission state TRAN.As mentioned above, when being converted to transmission state TRAN, flash memory device 104 can be responded set replying of correspondence to main frame 102.In addition, flash memory device 104 also can be carried out relevant interrupt operation.
After handling the access command CMD12 of main frame, flash memory device 104 judges whether the data transmission finishes (step S414).If desire to proceed the data transmission, then flash memory device 104 receives next access command (step S408) from main frame 102.If the data transmission is finished, then the end operation method 40.
The flash memory device of the embodiment of the invention and method of operating thereof are controlled the logic state machine circuit of flash memory device by the working storage array, thereby promote the design flexibility and the ease for maintenance of flash memory device.When memory card specifications changes, carry out the mode of operation transition of logic state machine circuit by the content of revising the working storage array, need not the rearranging logic circuit and carry out the integrated circuit flow.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (12)
1. flash memory device method of operating, this flash memory device is coupled to a main frame and has a plurality of modes of operation, and this method comprises the following steps:
Receive an order from this main frame;
According to one first mode of operation, read a working storage array with state exchange information, whether belong to the pairing a plurality of lawful orders of this first mode of operation in order to judge this order; And
When this order belongs to pairing these lawful orders of this first mode of operation, this state exchange information according to this working storage array, the conversion of the one logic state machine circuit decision mode of operation of this flash memory device, in order to being converted to one second mode of operation, with in response to this order from this first mode of operation.
2. flash memory device method of operating as claimed in claim 1 is characterized in that, more comprises:
In this state exchange information of a flash memory stores of this flash memory device, in order to upgrade; And
When electric power starting, this state exchange information after upgrading is loaded into this working storage array again from this flash memory.
3. flash memory device method of operating as claimed in claim 1 is characterized in that,, this state exchange information comprises pairing these lawful orders of this first mode of operation and in response to this second mode of operation of each lawful order.
4. flash memory device method of operating as claimed in claim 1, it is characterized in that, this working storage array comprises a plurality of working storage elements, is to be read abreast according to this first mode of operation, whether belongs to pairing these lawful orders of this first mode of operation in order to judge this order.
5. flash memory device method of operating as claimed in claim 3 is characterized in that, when being converted to this second mode of operation, setly replys response to this main frame, this set replying corresponding to this first mode of operation and this order with one.
6. flash memory device method of operating as claimed in claim 3 is characterized in that, when being converted to this second mode of operation, this flash memory device is carried out an interrupt operation.
7. data storage system comprises:
One main frame transmits a plurality of orders, in order to the access data; And
One flash memory device, be coupled to this main frame and have a plurality of modes of operation, this flash memory device receives an order from this main frame, according to one first mode of operation, read a working storage array with state exchange information, in order to judge whether this order belongs to the pairing a plurality of lawful orders of this first mode of operation, and when this order belongs to pairing these lawful orders of this first mode of operation, one logic state machine circuit of this flash memory device decides the conversion of mode of operation according to this state exchange information of this working storage array, in order to being converted to one second mode of operation, with in response to this order from this first mode of operation.
8. data storage system as claimed in claim 7, it is characterized in that this state exchange information is to be stored in a flash memory of this flash memory device, in order to upgrade, and when electric power starting, this state exchange information after upgrading is loaded into this working storage array again from this flash memory.
9. data storage system as claimed in claim 7 is characterized in that, this state exchange information comprises pairing these lawful orders of this first mode of operation, reaches this second mode of operation in response to each lawful order.
10. data storage system as claimed in claim 7, it is characterized in that, this working storage array comprises a plurality of working storage elements, this flash memory device reads these working storage elements abreast according to this first mode of operation, whether belongs to pairing these lawful orders of this first mode of operation in order to judge this order.
11. data storage system as claimed in claim 9 is characterized in that, when being converted to this second mode of operation, this flash memory device is responded set replying to this main frame, this set replying corresponding to this first mode of operation and this order.
12. data storage system as claimed in claim 9 is characterized in that, when being converted to this second mode of operation, this flash memory device is carried out an interrupt operation.
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| CN2009100545892A CN101944003A (en) | 2009-07-09 | 2009-07-09 | Flash memory device operation method and information storage system |
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| CN2009100545892A CN101944003A (en) | 2009-07-09 | 2009-07-09 | Flash memory device operation method and information storage system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11586383B2 (en) * | 2018-10-16 | 2023-02-21 | Micron Technology, Inc. | Command block management |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11586383B2 (en) * | 2018-10-16 | 2023-02-21 | Micron Technology, Inc. | Command block management |
| US11899982B2 (en) | 2018-10-16 | 2024-02-13 | Micron Technology, Inc. | Command block management |
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Application publication date: 20110112 |