CN101943830B - Active matrix displayer and driving method thereof - Google Patents

Abstract

The invention provides an active matrix displayer and a driving method thereof. During the first scanning period, a first scanning line and a second scanning line of the active matrix displayer are at high potential at the same time, a first pixel electrode of the active matrix displayer is electrically connected with a data line of the active matrix displayer, and a second pixel electrode of the active matrix displayer is electrically connected with the first pixel electrode of the active matrix displayer; and during the second scanning period, a second scanning line is at low potential, the first scanning line is at high potential, the first pixel electrode is electrically connected with the data line of the active matrix displayer, and the second pixel electrode and the first pixel electrode are electrically disconnected.

Description

Active matrix displayer and driving method thereof

Technical field

The present invention relates to a kind of display panel, and relate in particular to a kind of display panel with high aperture.

Background technology

At present general liquid crystal display is used active matrix (active matrix) driving circuit to control display panel mostly, so that its show image.How improveing driving circuit and driving method thereof, to improve resolution and the aperture opening ratio (Aperture Ratio) of display panel, can reduce manufacturing cost again, reduce the shared volume of driving circuit device, is one of problem of industry effort always.

Please refer to Fig. 1 and Fig. 2, Fig. 1 is the partial circuit figure of traditional active matrix displayer 40, the wiring diagram of the active matrix displayer 40 that Fig. 2 is Fig. 1.On active matrix displayer 40, there are a plurality of pixels 42 with array format.On active matrix displayer 40, be also provided with active matrix driving circuit, in order to control the action of each pixel 42 on display panel.Above-mentioned active matrix driving circuit is by sweep trace (scan line) S of many orthogonal arrangements _n～S _n+3and data line (dataline) D _m～D _m+5institute forms, and each pixel 42 all has a thin film transistor (TFT) (Thin FilmTransistor, TFT) Q as switch.

General thin film transistor (TFT) Q is N-shaped or p-type field effect thin film transistor (TFT) (Field EffectTransistor, FET), and have three electrodes, be respectively: grid (gate), the first source electrode (source)/drain electrode (drain) and the second source/drain.Wherein, the thin film transistor (TFT) Q of each pixel 42, its grid and the first source/drain couple with a pair of orthogonal sweep trace and data line respectively.The pixel 42 in the upper left corner of take is example, the grid of its thin film transistor (TFT) Q and the sweep trace S on display panel _ncouple, and the first source/drain of its thin film transistor (TFT) Q and the data line D on display panel _mcouple, and the pixel electrode 44 of the second drain/source of its thin film transistor (TFT) Q and the pixel capacitance Cp of pixel 42 couples.As depicted in figs. 1 and 2, between the pixel 42 of every two row, be provided with a sweep trace S _n～S _n+3, and between the pixel 42 of every two row, be provided with a data line D _m～D _m+5.Under such wiring, the aperture opening ratio of display panel can decline because of too much data line.

In addition, the people such as Manabu has disclosed another prior art in the 1236th page to 1239 pages papers of delivering of Society for Information Display (SID) DIGEST periodical " Display ElectronicsRequired for AMLCDs with Pixel Level Data-Line Multiplexing " in 2003.Please refer to Fig. 3 and Fig. 4, the equivalent circuit diagram of the array of display that the people such as Fig. 3 is Manabu is disclosed, Fig. 4 is the sequential chart of control signal of the array of display of control chart 3.Wherein, a storage capacitors Cs of each pixel A 1～D2 collocation, and three transistor T 1～T3 of average every two pixel A 1～D2 configuration.Two pixel A 1 and the B1 in the upper left corner of take is example, and pixel A 1 and B1 are couple to data line D (m) by transistor T 1 and T3 respectively.Wherein, the grid of transistor T 1 is couple to the first source/drain of transistor T 2, and the grid of transistor T 2 and T3 is couple to sweep trace G (n+1), and the second source/drain of transistor T 2 is coupled to next sweep trace G (n+2) by wire 32.As shown in Figure 4, the voltage of each sweep trace G (n)～G (n+3) can time to time change, with turn-on transistor T1～T3 in time, so that the data voltage of data line D (m), D (m+1) is applied to pixel A 1～D2 in special time.For instance, during t1, the voltage of data line D (m) can be applied to pixel A 1 and B1; During t2, the voltage of data line D (m) is applied to pixel B 1; During t3, the voltage of data line D (m) is applied to pixel C1 and D1; And during t4, the voltage of data line D (m) is applied to pixel D1.

Although, the pixel of its every two row of array of display that the people such as Manabu are disclosed shares a data line, and the number of its total data line is reduced, but because such technology still must connect the transistor T 2 on each sweep trace by wire 32, therefore the aperture opening ratio of its display panel still cannot improve.In addition, disclosed average every two pixels of array of display of the people such as Manabu need three transistor T 1～T3, and too much transistor also can make the aperture opening ratio of its panel decline.

Summary of the invention

The invention provides a kind of active matrix displayer, it has higher aperture opening ratio.

The invention provides a kind of driving method, in order to drive above-mentioned active matrix displayer.

The present invention proposes a kind of active matrix displayer.Described active matrix displayer comprises the first pixel electrode, the second pixel electrode, data line, the first sweep trace and the second sweep trace.Wherein said the first sweep trace is in order to control being electrically connected between the first pixel electrode and data line, and described the second sweep trace is in order to control being electrically connected between the first pixel electrode and the second pixel electrode.

The present invention proposes a kind of method that drives active matrix displayer, in order to upgrade the first pixel electrode of active matrix displayer and the pixel voltage of the second pixel electrode.Said method comprises: within the first scan period, by making the first sweep trace and second sweep trace of active matrix displayer, it is noble potential simultaneously, and make the first pixel electrode be electrically connected on a data line of active matrix displayer, and make the second pixel electrode be electrically connected on the first pixel electrode; And, within the second scan period, by making the second sweep trace, be electronegative potential to make the first sweep trace be noble potential, and make the first pixel electrode be electrically connected on the data line of active matrix displayer, and make the second pixel electrode electrically separated with the first pixel electrode.

In one embodiment of this invention, above-mentioned active matrix displayer also comprises the first transistor and transistor seconds.Wherein, when the first sweep trace is noble potential, the first transistor of active matrix displayer is understood conducting, and when the second sweep trace is noble potential, the transistor seconds of active matrix displayer can conducting.The source electrode of the first transistor and drain electrode are coupled to the first pixel electrode and data line, the grid of the first transistor is coupled to the first sweep trace, the source electrode of transistor seconds and drain electrode are coupled to the first pixel electrode and the second pixel electrode, and the grid of transistor seconds is coupled to the second sweep trace.

In one embodiment of this invention, the first above-mentioned pixel electrode and the second pixel electrode are located between the first sweep trace and the second sweep trace.

In one embodiment of this invention, the first above-mentioned pixel electrode and the second pixel electrode are located at the not homonymy of the second sweep trace.

In one embodiment of this invention, above-mentioned active matrix displayer includes a plurality of the first described pixel electrodes and a plurality of the second described pixel electrode, and a plurality of the first pixel electrode and a plurality of the second pixel electrode are arranged in the mode of upset pixel (flip pixel).

In one embodiment of this invention, the first above-mentioned pixel electrode has different pixel voltages from the second pixel electrode.

In one embodiment of this invention, the first above-mentioned pixel electrode and the second pixel electrode have the area of different sizes.

In one embodiment of this invention, the polarity of above-mentioned data line was only switched once every a frame period.

In one embodiment of this invention, the polarity of above-mentioned data line was switched once every two scan periods.

In one embodiment of this invention, the first above-mentioned pixel electrode has identical polarity with the second pixel electrode.

In one embodiment of this invention, the first above-mentioned pixel electrode has different polarity from the second pixel electrode.

In one embodiment of this invention, the first above-mentioned pixel electrode and the second pixel electrode are covered by the filter layer of same color.

In one embodiment of this invention, the first above-mentioned pixel electrode and the second pixel electrode are covered by the filter layer of different colours.

In one embodiment of this invention, the second above-mentioned scan period was less than for the first scan period.

In one embodiment of this invention, when the first pixel electrode is electrically connected on data line, and the second pixel electrode and data line are electrical when separated, and the voltage of the first sweep trace is one first noble potential.When the first pixel electrode and the second pixel electrode are all electrically connected on data line, the voltage of the first sweep trace and the second sweep trace is one second noble potential, and the second noble potential is less than the first noble potential.

In one embodiment of this invention, within each frame period, the first sweep trace and the second sweep trace all can be down to the first electronegative potential by noble potential, then are down to the second electronegative potential by the first electronegative potential.When the first sweep trace is during in the first electronegative potential or the second electronegative potential, the first pixel electrode is electrically separated with data line.When the second sweep trace is during in the first electronegative potential or the second electronegative potential, the second pixel electrode is electrically separated with data line.

The present invention mainly utilizes the first pixel electrode that same column is adjacent and the second pixel electrode to share the type of drive of a data line, the second pixel electrode can be electrically connected to data line by the first pixel electrode, and each pixel only utilizes a switch to control start, to reduce number and the number of switches of data line simultaneously, and then reach and reduce costs and the object that increases aperture opening ratio.

For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate appended graphicly, be described in detail below.

Accompanying drawing explanation

Fig. 1 is the partial circuit figure of traditional active matrix displayer;

Fig. 2 is the wiring diagram of the active matrix displayer of Fig. 1;

Fig. 3 is the equivalent circuit diagram of the disclosed array of display of the people such as Manabu;

Fig. 4 is the sequential chart of the control signal of Fig. 3 array of display;

Fig. 5 is the wiring diagram of the active matrix displayer of one embodiment of the invention;

Fig. 6 is the circuit diagram of the active matrix displayer of Fig. 5;

Fig. 7 is the circuit diagram in order to the type of drive of the active matrix displayer of key diagram 5;

Fig. 8 is the sequential chart of control signal of sweep trace of the active matrix displayer of Fig. 7;

Fig. 9 is the circuit diagram of the active matrix displayer of another embodiment of the present invention;

Figure 10 is the wiring diagram of the active matrix displayer of another embodiment of the present invention;

Figure 11 is the wiring diagram of the active matrix displayer of another embodiment of the present invention;

Figure 12 is the wiring diagram of the active matrix displayer of another embodiment of the present invention;

Figure 13 is the circuit diagram of the active matrix displayer of Figure 11;

Figure 14 is in order to illustrate the circuit diagram of type of drive of the active matrix displayer of Figure 13;

Figure 15 is the sequential chart of control signal of sweep trace of the active matrix displayer of Figure 11;

Figure 16 is the sequential chart of control voltage of sweep trace of the active matrix displayer of one embodiment of the invention;

Figure 17 is the sequential chart of control voltage of sweep trace of the active matrix displayer of one embodiment of the invention;

Figure 18 is the partial circuit figure of the active matrix displayer of one embodiment of the invention;

Figure 19 is the sequential chart of scanning voltage of each sweep trace of Figure 18;

Figure 20 is the sequential chart of the scanning voltage of each sweep trace in another embodiment of the present invention;

Figure 21 is the circuit diagram of the active matrix displayer of one embodiment of the invention;

Figure 22 is the wiring diagram of the active matrix displayer of Figure 21;

Figure 23 is the control signal sequential chart of the active matrix displayer of Figure 21;

Figure 24 is the wiring diagram of the active matrix displayer of one embodiment of the invention;

Figure 25 is the circuit diagram of the active matrix displayer of Figure 24;

Figure 26 is the control signal sequential chart of the active matrix displayer of Figure 24;

Figure 27 is the control signal sequential chart of active matrix displayer in Fig. 5;

Figure 28 illustrates the polarity of pixel electrode of the active matrix displayer of Fig. 5;

Figure 29 is the control signal sequential chart of active matrix displayer in Figure 12; And

Figure 30 illustrates the polarity of pixel electrode of the active matrix displayer of Figure 12.

[main element symbol description]

32: wire

40,50,90,100,110,120,210,240: active matrix displayer

42: pixel

44: pixel electrode

60: the first sub-pixs

62: the second sub-pixs

64,66: pixel

242: redundant area

A: the first pixel electrode

B: the second pixel electrode

A1, A2, B1, B2, C1, C2, D1, D2: pixel

C _gd: gate/drain electric capacity

C _gs: gate/source electric capacity

C _sa: the first storage capacitors

C _sb: the second storage capacitors

C _p: pixel capacitance

C _s: storage capacitors

C _lca: the first pixel capacitance

C _lcb: the second pixel capacitance

COM: common voltage

D _m～D _m+5, D (m), D (m+1): data line

G (n)～G (n+3): sweep trace

M1: the first transistor

M2: transistor seconds

Q: thin film transistor (TFT)

Q1～Q8: transistor

S _n～S _n+4, S _x-1, S _x: sweep trace

T1～t4, T _a～T _n: scan period

Ta: the first scan period

Tb: the second scan period

V1～v8: sub-pix

V _a2, V _b2: pixel voltage

V _h1: the first noble potential

V _h2: the second noble potential

V _h3: third high current potential

V _l: electronegative potential

V _l1: the first electronegative potential

V _l2: the second electronegative potential

: positive polarity

: negative polarity

Embodiment

Please refer to Fig. 5 and Fig. 6, the wiring diagram of the active matrix displayer 50 that Fig. 5 is one embodiment of the invention, the circuit diagram of the active matrix displayer 50 that Fig. 6 is Fig. 5.Active matrix displayer 50 includes a plurality of the first sub-pixs (first sub-pixel) 60, a plurality of the second sub-pix (secondsub-pixel) 62, a plurality of the first transistor M1, a plurality of transistor seconds M2, many data line D _m～D _m+2and multi-strip scanning line S _n～S _n+4.It should be noted that, the number of the data line illustrating in Fig. 5 and Fig. 6, sweep trace and pixel is only used as exemplary illustration, and the present invention is as limit, and application is when of the present invention, can, according in fact required resolution, increase or reduce the number of data line, sweep trace and pixel.In addition, if when active matrix displayer is a liquid crystal display, generally have the variation that many capacitor storage beam (not drawing in Fig. 5) produce to reduce the stored current potential due to leakage current of liquid crystal pixel, a liquid crystal pixel is except the capacitor C of itself _lcoutside, also comprise the storage capacitors C between pixel electrode and capacitor storage beam _s.As shown in the figure, each the first sub-pix 60 is coupled to the first transistor M1 of a correspondence, and has the first pixel capacitance C _lcawith the first storage capacitors C _sa; And each second sub-pix 62 is coupled to the transistor seconds M2 of a correspondence, and there is the second pixel capacitance C _lcbwith the second storage capacitors C _sb.The first pixel capacitance C _lcathere is the first pixel electrode A that is coupled to corresponding the first transistor M1, and the second pixel capacitance C _lcbthere is the second pixel electrode B that is coupled to corresponding transistor seconds M2.The first storage capacitors C _sawith the first pixel capacitance C _lain order to preserve the required electric charge of the first sub-pix 60 show images.Relative, the second storage capacitors C _sbwith the second pixel capacitance C _sbto preserve the required electric charge of the second sub-pix 62 show images.

The grid of each the first transistor M1 is coupled to a corresponding sweep trace S _n～S _n+4, and the first source/drain of the first transistor M1 is coupled to a corresponding data line D _m～D _m+2, and its second source/drain is coupled to the first source/drain of the transistor seconds M2 of the first corresponding sub-pix 60 and correspondence.In addition, the grid of transistor seconds M2 is coupled to a corresponding sweep trace S _n～S _n+4, and the second source/drain of transistor seconds M2 is coupled to the second corresponding sub-pix 62.The first transistor M1 and the transistor seconds M2 that is arranged in Fig. 5 and the upper left corner of Fig. 6 of take is example, and its grid of the first transistor M1 in the upper left corner is coupled to sweep trace S _n+1, and its first source/drain is coupled to data line D _m, and its second source/drain is coupled to the first source/drain of first sub-pix 60 in the upper left corner and the transistor seconds M2 in the upper left corner.As for the transistor seconds M2 that is positioned at the upper left corner of Fig. 5 and Fig. 6, its grid is coupled to sweep trace S _n, and its second source/drain is coupled to second sub-pix 62 in the upper left corner.In other words, the first transistor M1 mutually coupling and two grids of transistor seconds M2 are coupled to respectively two adjacent sweep traces (as S _nand S _n+1).The voltage of sweep trace can be promoted to noble potential in good time, to control the unlatching opportunity of the first transistor M1 and transistor seconds M2, and then makes data line D _m～D _m+2voltage be applied to the first sub-pix 60 and the second sub-pix 62.Wherein, when the first transistor M1 coupling and transistor seconds M2 unlatching, data line D _m～D _m+2voltage can be applied to the second sub-pix 62 by the first sub-pix 60.Therefore, every a line first sub-pix 60 of active matrix displayer 50 and the wherein shared same data line D of the second sub-pix 62 of a line _m～D _m+2, therefore compared to active matrix displayer of the prior art, the active matrix displayer 50 in the present embodiment has larger aperture opening ratio.

The type of drive of active matrix displayer 50 for convenience of description, at this first by the component symbol layout further again of the first sub-pix 60, the second sub-pix 62, the first transistor M1 and the transistor seconds M2 of each row of active matrix displayer 50, hereby to distinguish.As shown in Figure 7, in Fig. 6, the second sub-pix 62 of first row, secondary series, the 3rd row and the 4th row is called sub-pix v1, v3, v5 and v7, and the first sub-pix 60 of first row, secondary series, the 3rd row and the 4th row is called sub-pix v2, v4, v6 and v8.In addition, the transistor seconds M2 of first row, secondary series, the 3rd row and the 4th row is called transistor Q1, Q3, Q5 and Q7, and the first transistor M1 of first row, secondary series, the 3rd row and the 4th row is called transistor Q2, Q4, Q6 and Q8.Please refer to Fig. 5, Fig. 7 and Fig. 8, wherein Fig. 8 is the sequential chart of control signal of the sweep trace of active matrix displayer 50.With a plurality of scan period T _g～T _lfor example, at scan period T _g, sweep trace S _n+1and S _n+2control signal be noble potential, and make transistor Q2, Q3, Q4 and Q5 conducting, data line D _m～D _m+2data voltage can be sent to sub-pix v2, v3 and v4, data line D wherein _m～D _m+2data voltage by the first pixel electrode A of sub-pix v4, be applied to the second pixel electrode B of sub-pix v3.In addition, at scan period T _g, because of not conducting of transistor Q5 conducting transistor Q6, thus the electric charge meeting intercommunication in sub-pix v5 and v6, and the voltage difference between sub-pix v5 and v6 is reduced.

At scan period T _h, only have sweep trace S _n+1control signal be noble potential, now transistor Q2 and Q3 conducting, data line D _m～D _m+2data voltage can be sent to sub-pix v2.In addition, because the current potential of pixel electrode B of sub-pix v3 and the current potential of the pixel electrode A of sub-pix v4 are at scan period T _gtime balance and equating, therefore sub-pix v3 is at scan period T _hshown data can not be affected because of the conducting of transistor Q3.Hence one can see that, and within a frame period (frame period), the pixel voltage of sub-pix v3 and sub-pix v2 can be respectively at scan period T _gand T _hinside complete renewal, and sub-pix v4 is at scan period T _gcan be by pre-charged.

Similarly, at scan period T _i, sweep trace S _n+2and S _n+3control signal be noble potential, and make transistor Q4, Q5, Q6 and Q7 conducting, data line D _m～D _m+2data voltage be sent to sub-pix v4, v5 and v6, data line D wherein _m～D _m+2data voltage by the first pixel electrode A of sub-pix v6, be applied to the second pixel electrode B of sub-pix v5.In addition, at scan period T _i, because of not conducting of transistor Q7 conducting transistor Q8, thus the electric charge meeting intercommunication in sub-pix v7 and v8, and the voltage difference between sub-pix v7 and v8 is reduced.At scan period T _j, only have sweep trace S _n+2control signal be noble potential, now transistor Q4 and Q5 conducting, data line D _m～D _m+2data voltage be sent to sub-pix v4.In addition, because the current potential of pixel electrode B of sub-pix v5 and the current potential of the pixel electrode A of sub-pix v6 are at scan period T _itime balance and equating, therefore sub-pix v5 is at scan period T _ishown data can not be affected because of the conducting of transistor Q5.Hence one can see that, and the pixel voltage of sub-pix v5 and sub-pix v4 can be respectively at scan period T _iand T _jinside complete renewal, and sub-pix v6 is at scan period T _ican be by pre-charged.In like manner, at scan period T _kand T _l, by gated sweep line S _n+3and S _n+4current potential, can be by data line D _m～D _m+2data voltage be sent to sub-pix v7 and v6, to upgrade the current potential of sub-pix v7 and v6 its pixel electrode B and A, and then change the anglec of rotation and the light transmittance of its liquid crystal.

Except the above-mentioned aperture opening ratio that improves display panel, further application of the invention can be used to improve colo(u)r bias (color shift) phenomenon of liquid crystal display.Generally speaking, because phasic difference value (Retardation) difference that the incident light of different angles, in liquid crystal layer, produces, so the light transmittance that liquid crystal display is faced when to liquid crystal display side-looking is not identical.Therefore,, when viewing angle is different, the suffered deviation coefficient of light is not identical, causes penetrance different yet.So different visual angles can cause the brightness of shown light different.And for example, when different color light (red light, green light and blue light) is being faced from side-looking each with different brightness ratio colour mixtures after, can produce and face the colo(u)r bias phenomenon that the color shown with side-looking is not identical.Generally speaking, the degree size of the colo(u)r bias causing because of side-looking is that blue light is greater than green light, and green light is greater than red light.How reducing the colo(u)r bias while facing with side-looking liquid crystal display, is one of problem of endeavouring of industry.

Colo(u)r bias while facing with side-looking liquid crystal display for reducing, the present invention is integrated into pixel 64 by the first above-mentioned sub-pix 60 and the second sub-pix 62.Please refer to Fig. 9, the circuit diagram of the active matrix displayer 90 that Fig. 9 is another embodiment of the present invention.The circuit structure of active matrix displayer 90 is the same with active matrix displayer 50, at this, repeats no more.In the present embodiment, the first sub-pix 60 of same pixel 64 and the second sub-pix 62 are in order to show identical color, and two adjacent pixels 64 show different colors.For instance, in one embodiment of this invention, the first sub-pix 60 of same pixel 64 and the second sub-pix 62 are covered by the filter layer of same color, to show identical color; And two adjacent pixels 64 are covered by the filter layer of different colours, to show different colors.In addition, in the present invention, by making the first sub-pix 60 of same pixel 64 show different GTG values with the second sub-pix 62, improve colo(u)r bias phenomenon.For instance, in one embodiment of this invention, for one of them pixel 64 is shown, be equivalent to the effect that GTG value equals 125, the corresponding GTG value of its first sub-pix 60 is made as 140, and the corresponding GTG value of the second sub-pix 62 is made as 115.Cause the first sub-pix 60 and the second sub-pix 62 show respectively different brightness, thus under different viewing angles, can reach the effect of vision complementation, and the degree of colo(u)r bias is reduced.In addition, it should be noted that, when processing colo(u)r bias, the first sub-pix 60 and the corresponding GTG value of the second sub-pix 62 can adjust according to actual conditions, for example: foundation the first sub-pix 60 and the pixel electrode A of the second sub-pix 62 and the area ratio of B are adjusted, or the first sub-pix 60 and the corresponding pixel value of the second sub-pix 62 are exchanged.

In Fig. 5, pixel electrode A and pixel electrode B are roughly the same in shape and size, and in one embodiment of this invention, the shape of pixel electrode A is different from pixel electrode B with size.Please refer to Figure 10, the wiring diagram of the active matrix displayer 100 that Figure 10 is another embodiment of the present invention.The circuit structure of active matrix displayer 100 and type of drive are identical with the active matrix displayer 50 in Fig. 5, and difference is between the two shape and the size of its pixel electrode A and pixel electrode B.In the present embodiment, the area of pixel electrode A is less than the area of pixel electrode B, and both shapes are also different.Yet it should be noted that, the present invention is not as limit, for example: pixel electrode A and pixel electrode B can be the identical but quadrilateral that width is not identical of length.

In the above-described embodiments, transistor seconds M2 is in order to together with being coupled in the first pixel electrode A that is positioned at same the first sub-pix 60 listing and the second sub-pix 62 with the second pixel electrode B.Yet in another embodiment of the present invention, transistor seconds M2 is for together with the first pixel electrode A that is positioned at two adjacent the first sub-pixs 60 that list and the second sub-pix 62 is coupled in the second pixel electrode B.Please refer to Figure 11, the wiring diagram of the active matrix displayer 110 that Figure 11 is another embodiment of the present invention.Wherein, each transistor seconds M2 is by a corresponding sweep trace S _n～S _n+4together with the first pixel electrode A of both sides is coupled in the second pixel electrode B.In addition, although the first pixel electrode A that Figure 11 illustrates and the second pixel electrode B are different in shape and size, yet the present invention is not as limit, for example: the first pixel electrode A and the second pixel electrode B can have roughly the same shape and size.Please refer to Figure 11 and Figure 12, the wiring diagram of the active matrix displayer 120 that Figure 12 is one embodiment of the invention.Connected mode between active matrix displayer 120 each elements is identical with active matrix displayer 110, and both difference are only shape and the size of the first pixel electrode A and the second pixel electrode B.

Please refer to Figure 13 while with reference to figure 9, the circuit diagram of the active matrix displayer 110 that wherein Figure 13 is Figure 11.As seen from the figure, the electric connection mode in active matrix displayer 110 between each element substantially with each element in active matrix displayer 90 between electric connection mode be identical, and both difference are only the setting position of the second sub-pix 62.In addition, as shown in figure 13, each first sub-pix 60 can be integrated into pixel 66 with second sub-pix 62 with listing, so active matrix displayer 110 also has the function of above-mentioned reduction colo(u)r bias.

Substantially, the type of drive of active matrix displayer 110 is consistent with the type of drive of active matrix displayer 50 and 90, and the type of drive of active matrix displayer 110 for convenience of description, at this equally first by the component symbol layout further again of the first sub-pix 60, the second sub-pix 62, the first transistor M1 and the transistor seconds M2 of each row of active matrix displayer 110, hereby to distinguish.As shown in figure 14, in Figure 13, by transistor seconds M2, be coupled to sweep trace S _n, S _n+1, S _n+2and S _n+3the second sub-pix 62 be called sub-pix v1, v3, v5 and v7, and be coupled to sweep trace S by the first transistor M1 _n+1, S _n+2, S _n+3and S _n+4the first sub-pix 60 be called sub-pix v2, v4, v6 and v8.In addition, the transistor seconds M2 of first row, secondary series, the 3rd row and the 4th row is called transistor Q1, Q3, Q5 and Q7, and the first transistor M1 of first row, secondary series, the 3rd row and the 4th row is called transistor Q2, Q4, Q6 and Q8.Please refer to Figure 14 and Figure 15, Figure 15 is the sequential chart of control signal of the sweep trace of active matrix displayer 110.Wherein, identical with active matrix displayer 50 and 90, the shown gray scale states of sub-pix v3, v2, v5, v4, v7 and the v6 of active matrix displayer 110 is respectively at scan period T _g, T _h, T _i, T _j, T _k, and T _lcomplete renewal.Wherein, in each frame period, the first pixel electrode A that the second pixel electrode B of sub-pix v1, v3, v5 and v7 can couple transistor Q1, Q3, Q5, Q7 and sub-pix v2, v4, v6 and v8 by it respectively, is electrically connected to data line D _m～D _m+2, and the pixel voltage of the second pixel electrode B of sub-pix v1, v3, v5 and v7 is updated.

In the above-described embodiment, each second pixel electrode B all needs the transistor seconds M2 and the first pixel electrode A that by it, couple, is electrically connected to corresponding data line D _m～D _m+2.Therefore, when the first transistor M1 between the second pixel electrode B and data line and transistor seconds M2 are during conducting, impedance meeting between the second pixel electrode B and data line is greater than the impedance between the first pixel electrode A and data line, and such situation may make the pixel voltage of the second pixel electrode B of part cannot complete renewal within the predetermined time.For guaranteeing that the pixel voltage of each pixel electrode B all can complete renewal within the predetermined time, the present invention separately provides several modes to reach such object.Wherein a kind of mode is to adjust pixel electrode A and corresponding the first scan period of pixel electrode B and the second scan period.Please refer to Figure 16, the sequential chart of the control voltage of the sweep trace of the active matrix displayer that Figure 16 is one embodiment of the invention.Each scan period (T for example _g～T _l) can be divided into the first scan period Ta and the second scan period Tb according to the unlatching situation of corresponding the first transistor M1 and transistor seconds M2.Wherein, in each second scan period Tb, article two, the voltage of adjacent sweep trace is noble potential, and understand conducting with the first transistor M1 and transistor seconds M2 that these two adjacent scanning lines couple, and then make the pixel voltage of its corresponding first pixel electrode A and the second pixel electrode B all obtain renewal; And in each first scan period Ta, the voltage that only has a sweep trace can be noble potential, now only have the first pixel electrode A of a certain row can be electrically connected to data line.Hence one can see that, the total charging time of the first pixel electrode A (Ta+Tb) can be long compared with the total charging time of the second pixel electrode B (Tb), therefore can be by the mode that shortens the first scan period Ta and extend the second scan period Tb, or make the second scan period Tb be greater than the first scan period Ta, guarantee that each first pixel electrode A and each second pixel electrode B can complete the action of upgrading its pixel voltage within the predetermined scan period.

In addition, another kind of the present invention guarantees that pixel voltage can complete the mode of renewal within the predetermined scan period, is by the second pixel electrode B precharge is reached.Please refer to Figure 17 while with reference to figure 8, the sequential chart of the control voltage of the sweep trace of the active matrix displayer that Figure 17 is one embodiment of the invention.In the present embodiment, each sweep trace S _n～S _n+4voltage except meeting within scan period as shown in Figure 8 in noble potential, also can be pre-charged to the second pixel electrode B within the scan period representing with oblique line block.For instance, for sub-pix v3, as sweep trace S _n+1and S _n+2voltage while being all noble potential, its second pixel electrode B can be recharged because being electrically connected to data line.Therefore, except at scan period T _goutside original charging procedure, sub-pix v3 the second pixel electrode B is at another scan period T _dalso can be recharged.In like manner, sub-pix v5 the second pixel electrode B can be at scan period T _fbe precharged, and at scan period T _icomplete the more new element of pixel voltage.As for the precharge mode of the second pixel electrode B of other the second sub-pixs, can the rest may be inferred.Because the second pixel electrode B of each the second sub-pix can be precharged, therefore can guarantee that the pixel voltage of the second pixel electrode B can complete renewal within the predetermined scan period.

At known active matrix displayer, conventionally have so-called feedthrough phenomenon (feed througheffect) and produce, cause the main cause of this phenomenon to be there is parasitic gate/drain capacitor C between the thin film transistor (TFT) of active matrix displayer and sweep trace _gdand gate/source capacitor C _gsevent.When the voltage of sweep trace changes to some extent, the voltage of the pixel electrode that it couples can be affected and change, yet if inconsistent words are measured in the change of the voltage of each pixel electrode, the shown brightness of active matrix displayer have inhomogeneous situation, and then reduce its image quality.

Minimum for feedthrough phenomenon is down to for the impact of image quality, by controlling each sweep trace in the waveform of the scanning voltage of each scan period, the voltage change amount of pixel electrode is reached unanimity, to guarantee its image quality in one embodiment of this invention.Please refer to Figure 18 and Figure 19, the partial circuit figure of the active matrix displayer that Figure 18 is one embodiment of the invention, each sweep trace S that Figure 19 is Figure 18 _n～S _n+4the sequential chart of scanning voltage.Event for convenience of description, the circuit diagram of Figure 18 has only illustrated a data line D _m, and persons skilled in the art should be understood in the middle of the active matrix displayer that the method disclosed in the present embodiment can be applicable to many data lines.In the present embodiment, by transistor Q1, Q3, Q5, Q7, be coupled to sweep trace S _n～S _n+3the second sub-pix be denoted as respectively v1, v3, v5, v7, and be coupled to sweep trace S by transistor Q2, Q4, Q6, Q8 _n+1～S _n+4the first sub-pix be denoted as respectively v2, v4, v6, v8.Each transistor Q1～Q8 all has gate/drain capacitor C _gdand gate/source capacitor C _gs, be coupled to corresponding sweep trace S _n～S _n+4.As sweep trace S _n～S _n+4in electronegative potential V _ltime, the not conducting of transistor Q1～Q8 that it couples.When having the voltage of two adjacent sweep traces to be noble potential in same scan period, its magnitude of voltage is the first noble potential V _h1; And when same scan period only has the voltage of single sweep trace to be noble potential, its magnitude of voltage is the second noble potential V _h2, the second noble potential V wherein _h2be greater than the first noble potential V _h1.In addition, after each scan period, when the voltage of sweep trace is from the first noble potential V _h1or the second noble potential V _h2be down to electronegative potential V _ltime, its magnitude of voltage can be first down to third high current potential V _h3after, then be down to electronegative potential V _l.Third high current potential V wherein _h3be less than the first noble potential V _h1and be greater than electronegative potential V _l.With scan period T _gfor example, sweep trace S _n+1and S _n+2voltage be first thus lifted to the first noble potential V _h1, and make to be connected to sweep trace S _n+1and S _n+2transistor Q2, Q3, Q4 and Q5 conducting, and then make sub-pix v3 and v4 by data line D _mcharging.Afterwards, as sweep trace S _n+2voltage by the first noble potential V _h1be down to electronegative potential V _lbefore, sweep trace S _n+2voltage can first be down to third high current potential V _h3, to dwindle the gate/drain capacitor C of transistor Q4 _gdand gate/source capacitor C _gsthe pressure reduction at two ends, and then the pixel electrode of the first electrode A of sub-pix v4 is reduced because of the pressure drop of closing transistor Q4 and causing, and then reduce feedthrough phenomenon.In addition, at scan period T _hwhen transistor Q4 closes, because transistor Q3 now still opens, and make the voltage of the pixel electrode B of sub-pix v3 can be subject to the impact of the pixel electrode A pressure drop of sub-pix v4, and be to reduce to cause the change of pixel electrode B on voltage, sweep trace S because of such impact _n+1voltage can be by the first noble potential V _h1rise to the second noble potential V _h2, so that sweep trace S _n+1lifting on voltage, for the impact of sub-pix v3 pixel electrode B, balances out sweep trace S _n+2decline on voltage is for the impact of sub-pix v3 pixel electrode B.Thus, as sweep trace S _n+1voltage rise to the second noble potential V _h2and sweep trace S _n+2lower voltage to electronegative potential V _ltime, the variation of the pixel electrode B of sub-pix v3 on voltage can equal or convergence zero.Afterwards, as sweep trace S _n+1voltage by the second noble potential V _h2be down to electronegative potential V _lbefore, sweep trace S _n+1voltage can first be down to third high current potential V _h3, to dwindle the gate/drain capacitor C of transistor Q3 _gdwith gate/source capacitor C _gsthe pressure reduction at two ends, and then the pixel electrode of the second electrode B of sub-pix v3 is reduced because of the pressure drop of closing transistor Q3 and causing, and then reduce feedthrough phenomenon.Cause is at scan period T _gand T _hwhile closing to an end, sweep trace S _n+2and S _n+1voltage all respectively from third high current potential V _h3be down to electronegative potential V _ltherefore sub-pix v3 and v4 are because of sweep trace S _n+1and S _n+2pressure drop and on pixel voltage, formed variable quantity can be consistent, and make active matrix displayer have preferably image quality.

Except reducing in the above described manner the impact of feedthrough phenomenon for image quality, in one embodiment of this invention, disclosed another kind of method to reduce feedthrough phenomenon for the impact of image quality.Please refer to Figure 20 while with reference to Figure 18, Figure 20 is each sweep trace S in another embodiment of the present invention _n～S _n+4the sequential chart of scanning voltage.Within each frame period, each sweep trace S _n～S _n+4can be by the second electronegative potential V _l2be promoted to noble potential V _h, and after through a scan period again by noble potential V _hbe down to the first electronegative potential V _l1, the first electronegative potential V wherein _l1higher than the second electronegative potential V _l2, and the second electronegative potential V _l2for negative voltage.When the scanning voltage of arbitrary sweep trace equals the first electronegative potential V _l1or the second electronegative potential V _l2time, the transistor that sweep trace couples can be closed.As each sweep trace S _n～S _n+4voltage maintain the first electronegative potential V _l1after the scan period, can be by the first electronegative potential V _l1be promoted to noble potential V _h, and in noble potential V _hmaintain after two scan periods, then by noble potential V _hbe down to the first electronegative potential V _l1.Afterwards, for example, after a Preset Time (three scan periods), the voltage of sweep trace can be by the first electronegative potential V _l1be down to the second electronegative potential V _l2.With sweep trace S _n+1for example, at scan period T _eto～T _kother scan periods in addition, its voltage is the second electronegative potential V _l2; At scan period T _e, T _gand T _h, its voltage is noble potential V _h; And at scan period T _f, T _i, T _jand T _k, its voltage is noble potential the first electronegative potential V _l1.For the feature of the present embodiment is clearly described, below by the pixel voltage V with sub-pix v2 _a2pixel voltage V with sub-pix v3 _b2illustrate.At scan period T _g, sweep trace S _n+1and S _n+2voltage be respectively noble potential V _h, and make transistor Q2, Q3, Q4 and Q5 meeting conducting, and then make pixel voltage V _a2and V _b2be promoted to respectively data line D _mvoltage.When scan period is by T _gswitch to T _htime, sweep trace S _n+1voltage still maintain noble potential V _h, and sweep trace S _n+2voltage from noble potential V _hbe switched to the first electronegative potential V _l1therefore, transistor Q2 and Q3 meeting conducting, and transistor Q4 and Q5 can be closed, and because of the feedthrough phenomenon of transistor Q4, and cause pixel voltage V _b2produce Δ V ₁pressure drop, Δ V wherein ₁with following formula, represent:

${\mathrm{\ΔV}}_1=(V_H-V_{L1})\×\frac{C_{\mathrm{gs}}}{(C_{\mathrm{gs}}+C_{\mathrm{sa}}+C_{1\mathrm{ca}})+(C_{\mathrm{gd}}+C_{\mathrm{gs}}+C_{\mathrm{sb}}+C_{\mathrm{lcb}})}$

When scan period is by T _hswitch to T _itime, sweep trace S _n+1voltage from noble potential V _hbe switched to the first electronegative potential V _l1, because of the feedthrough phenomenon of transistor Q2 and Q3, and cause pixel voltage V _a2and V _b2produce respectively Δ V ₄with Δ V ₂pressure drop, Δ V wherein ₄with Δ V ₂with following formula, represent respectively:

When scan period is by T _iswitch to T _jtime, sweep trace S _nvoltage from the first electronegative potential V _l1be switched to the second electronegative potential V _l2, because of the feedthrough phenomenon of transistor Q1, and cause pixel voltage V _a2produce Δ V ₅pressure drop, Δ V wherein ₅with following formula, represent:

$\mathrm{\Δ}{V}_5=(V_{L1}-V_{L2})\×\frac{C_{\mathrm{gs}}}{C_{\mathrm{gd}}+C_{\mathrm{gs}}+C_{\mathrm{sb}}+C_{\mathrm{lcb}}}$

When scan period is by T _kswitch to T _ltime, sweep trace S _n+1voltage from the first electronegative potential V _l1be switched to the second electronegative potential V _l2, because of the feedthrough phenomenon of transistor Q2 and Q5, and cause pixel voltage V _a2and V _b2produce respectively Δ V ₆with Δ V ₃pressure drop, Δ V wherein ₆with Δ V ₃with following formula, represent respectively:

In one embodiment of this invention, by adjusting the first electronegative potential V _l1and the second electronegative potential V _l2, and make (Δ V ₁+ Δ V ₂+ Δ V ₃) equal (Δ V ₄+ Δ V ₅+ Δ V ₆).In other words, the pixel voltage V of sub-pix v2 and v3 _a2and V _b2the total pressure drop causing because of feedthrough phenomenon can equate, therefore the brightness meeting of sub-pix v2 and v3 is consistent.

Please refer to Figure 21 while with reference to figure 7, the circuit diagram of the active matrix displayer 210 that Figure 21 is one embodiment of the invention.Different from the active matrix displayer 50 of Fig. 7 is, active matrix displayer 210 adopts the arrangement mode of upset pixel (flip pixel), and wherein the first transistor in the even column of active matrix displayer 210 (being transistor Q4 and Q8) is coupled to the later data line D of second _m+1～D _m+3, the first transistor in its odd column (being transistor Q2 and Q6) is the same with the coupling mode of active matrix displayer 50.In detail, in active matrix displayer 210, the first source/drain of the transistor Q2 of the first row of first row, the second row and the third line is coupled to respectively data line D _m, D _m+1and D _m+2; The first source/drain of the transistor Q4 of the first row of secondary series, the second row and the third line is coupled to respectively data line D _m+1, D _m+2and D _m+3; The first source/drain of the transistor Q6 of tertial the first row, the second row and the third line is coupled to respectively data line D _m, D _m+1and D _m+2; And the first source/drain of the transistor Q8 of the first row, the second row and the third line of the 4th row is coupled to respectively data line D _m+1, D _m+2and D _m+3.In addition, in another embodiment of the present invention, by the first transistor on the odd column of active matrix displayer 210 and even column and data line D _m～D _m+3connected mode swap left and right.That is the first transistor in its odd column (being transistor Q2 and Q6) is coupled to the later data line D of second _m+1～D _m+3, the first transistor in its even column (being transistor Q4 and Q8) is the same with the coupling mode of active matrix displayer 50.In detail, in such embodiments, the first source/drain of the transistor Q2 of the first row of first row, the second row and the third line is coupled to respectively data line D _m+1, D _m+2and D _m+3; The first source/drain of the transistor Q4 of the first row of secondary series, the second row and the third line is coupled to respectively data line D _m, D _m+1and D _m+2; The first source/drain of the transistor Q6 of tertial the first row, the second row and the third line is coupled to respectively data line D _m+1, D _m+2and D _m+3; And the first source/drain of the transistor Q8 of the first row, the second row and the third line of the 4th row is coupled to respectively data line D _m, D _m+1and D _m+2.

When active matrix displayer adopts the arrangement mode of above-mentioned upset pixel, it is conducive to the control of its pixel polarity.In detail, adopt can reverse by the row Polarity Control mode of (column inversion) of the active matrix displayer of above-mentioned upset Pixel arrangement mode, reach an effect for reversion (dotinversion).Please refer to Figure 22 and Figure 23, Figure 22 is the wiring diagram of active matrix displayer 210, and Figure 23 is the control signal sequential chart of active matrix displayer 210.Wherein, with its polarity of the pixel electrode indicating is being for just, and with its polarity of the pixel electrode indicating is for negative.In the present embodiment, in the same frame period, its polarity of the data line of odd-numbered line is identical, and its polarity of the data line of even number line is identical, and the frame period of being often separated by, and its polarity can convert once.For instance, within a certain frame period, if data line D _mand D _m+2polarity for just, and data line D _m+1and D _m+3polarity for negative, within the next frame period, data line D _mand D _m+2polarity can be for negative, and data line D _m+1and D _m+3polarity can be for just; Otherwise also same.As shown in figure 23, within the same frame period, data line D _mpolarity for just, and data line D _m+1polarity for negative, the voltage quasi position that is wherein denoted as COM is the common voltage of the common electrode of active matrix displayer 210.Can be expectedly, at next frame period, data line D _mpolarity can be for negative, and data line D _m+1polarity for just.That is, in the next frame period, data line D _mdata voltage can be lower than common voltage COM, and data line D _m+1data voltage can be higher than common voltage COM.In addition the sweep trace S in Figure 23, _n～S _n+3sequential and the sweep trace S that illustrates of Fig. 8 _n～S _n+3sequential consistent, be all in order in order to the charging of the first sub-pix and the second sub-pix, at this, repeat no more.

Please refer to Figure 24 while with reference to Figure 22, the wiring diagram of the active matrix displayer 240 that Figure 24 is one embodiment of the invention.Active matrix displayer 240 is also the arrangement mode that adopts upset pixel.Yet, different from active matrix displayer 210 is, transistor seconds M2 in active matrix displayer 210 is the first pixel electrode A and the second pixel electrode B connecting in same column, and the transistor seconds M2 in active matrix displayer 240 is in order to connect the first pixel electrode A and the second pixel electrode B in colleague.In addition, active matrix displayer 240 separately includes redundant area 242, is positioned at the first pixel electrode A and the second pixel electrode B of the previous column of redundant area 242 in order to assistive drive.In addition, as shown in figure 24, in same row, the first pixel electrode A of each data line both sides can be identical with the polarity of the second pixel electrode B for the polarity of each pixel of active matrix displayer 240; And with in a line, the polarity of each the first pixel electrode A can be different from the polarity of the second pixel electrode B adjacent with it.

Please refer to Figure 25 and Figure 26, Figure 25 is the circuit diagram of active matrix displayer 240, and Figure 26 is the control signal sequential chart of active matrix displayer 240.In the present embodiment, the Polarity Control mode of active matrix displayer 240 adopts the type of drive of biserial reversion (two-line inversion), wherein data line D _m～D _m+1the polarity of data voltage can be every the conversion of two scan periods once.For example,, at scan period T ₃and T ₄in, data line D _mthe polarity of data voltage for just, data line D _m+1the polarity of data voltage for negative; And at scan period T ₅and T ₆in, data line D _mthe polarity of data voltage for negative, data line D _m+1the polarity of data voltage for just.

Please refer to Figure 27 and Figure 28, Figure 27 is the control signal sequential chart of active matrix displayer 50 in Fig. 5, and Figure 28 is in order to illustrate the polarity of the pixel electrode of active matrix displayer 50.Same, the Polarity Control mode of active matrix displayer 50 adopts the type of drive of biserial reversion, wherein data line D _m～D _m+2the polarity of data voltage can be every the conversion of two scan periods once.Each data line D _m～D _m+2data voltage polarity can with adjacent data line D _m～D _m+2the polarity of data voltage different.In addition, the polarity of the first pixel electrode A and the second pixel electrode B is arranged alternately.The polarity of each the first pixel electrode A can be different from the polarity of the second pixel electrode B adjacent in same column, and can from go together in the polarity of adjacent the first pixel electrode A different.Relatively, the polarity of each the second pixel electrode B can be different from the polarity of the first pixel electrode A adjacent in same column, and can from go together in the polarity of adjacent the second pixel electrode B different.

Please refer to Figure 29 and Figure 30, Figure 29 is the control signal sequential chart of active matrix displayer 120 in Figure 12, and Figure 30 is in order to illustrate the polarity of the pixel electrode of active matrix displayer 130.The Polarity Control mode of active matrix displayer 120 also adopts the type of drive of biserial reversion, wherein data line D _m～D _m+2the polarity of data voltage can be every the conversion of two scan periods once.Each data line D _m～D _m+2data voltage polarity can with adjacent data line D _m～D _m+2the polarity of data voltage different.In addition, at two adjacent data line D _m～D _m+2in the middle of, same column and adjacent its polarity of the first pixel electrode A and the second pixel electrode B can be identical, and colleague and adjacent two first pixel electrode A or its polarity of the second pixel electrode B can be different.

In sum, the present invention mainly utilizes the first pixel electrode that same column is adjacent and the second pixel electrode to share the type of drive of a data line, the second pixel electrode can be electrically connected to data line by the first pixel electrode, and each pixel only utilizes a switch to control start, to reduce number and the number of switches of data line simultaneously, and then reach and reduce costs and the object that increases aperture opening ratio.

Although the present invention discloses as above with preferred embodiment; but it is not in order to limit the present invention; persons skilled in the art without departing from the spirit and scope of the present invention; can carry out various modifications and changes to the present invention, so protection scope of the present invention should be as the criterion with the scope that appending claims was defined.

Claims (30)

1. an active matrix displayer, comprising:

One first pixel electrode;

One second pixel electrode;

One data line;

One first sweep trace, in order to control being electrically connected between described the first pixel electrode and described data line; And

One second sweep trace, in order to control being electrically connected between described the first pixel electrode and described the second pixel electrode,

Wherein within each frame period, described the first sweep trace and described the second sweep trace all can be down to one first electronegative potential by a noble potential, by described the first electronegative potential, be down to one second electronegative potential again, when described the first sweep trace is during in described the first electronegative potential or described the second electronegative potential, described the first pixel electrode is electrically separated with described data line, when described the second sweep trace is during in described the first electronegative potential or described the second electronegative potential, described the second pixel electrode is electrically separated with described data line.

2. active matrix displayer as claimed in claim 1, also comprises:

One the first transistor, its source electrode and drain electrode are coupled to described the first pixel electrode and described data line, and its grid is coupled to described the first sweep trace; And

One transistor seconds, its source electrode and drain electrode are coupled to described the first pixel electrode and described the second pixel electrode, and its grid is coupled to described the second sweep trace.

3. active matrix displayer as claimed in claim 1, wherein said the first pixel electrode and described the second pixel electrode are located between described the first sweep trace and described the second sweep trace.

4. active matrix displayer as claimed in claim 1, wherein said the first pixel electrode and described the second pixel electrode are located at the not homonymy of described the second sweep trace.

5. active matrix displayer as claimed in claim 1, a plurality of described the first pixel electrode that the mode of its pixel (flip pixel) that includes to overturn is arranged and a plurality of described the second pixel electrode of arranging in the mode of upset pixel.

6. active matrix displayer as claimed in claim 1, wherein said the first pixel electrode has different pixel voltages from described the second pixel electrode.

7. active matrix displayer as claimed in claim 1, wherein said the first pixel electrode and described the second pixel electrode have the area of different sizes.

8. active matrix displayer as claimed in claim 1, the polarity of wherein said data line was only switched once every a frame period.

9. active matrix displayer as claimed in claim 1, the polarity of wherein said data line was switched once every two scan periods.

10. active matrix displayer as claimed in claim 1, wherein said the first pixel electrode has identical polarity with described the second pixel electrode.

11. active matrix displayers as claimed in claim 1, wherein said the first pixel electrode has different polarity from described the second pixel electrode.

12. active matrix displayers as claimed in claim 1, wherein said the first pixel electrode and described the second pixel electrode are covered by the filter layer of same color.

13. active matrix displayers as claimed in claim 1, wherein said the first pixel electrode and described the second pixel electrode are covered by the filter layer of different colours.

14. active matrix displayers as claimed in claim 1, wherein within one first scan period, described the first pixel electrode is electrically connected on described data line, and described the second pixel electrode is electrically separated with described data line, and within one second scan period, described the first pixel electrode and described the second pixel electrode are all electrically connected on described data line, and described the second scan period is greater than described the first scan period.

15. 1 kinds of active matrix displayers, comprising:

One first pixel electrode;

One second pixel electrode;

One data line;

One first sweep trace, in order to control being electrically connected between described the first pixel electrode and described data line; And

One second sweep trace, in order to control being electrically connected between described the first pixel electrode and described the second pixel electrode,

Wherein when described the first pixel electrode is electrically connected on described data line, and described the second pixel electrode and described data line are electrical when separated, the voltage of described the first sweep trace is one first noble potential, and when described the first pixel electrode and described the second pixel electrode are all electrically connected on described data line, the voltage of described the first sweep trace and described the second sweep trace is one second noble potential, and described the second noble potential is less than described the first noble potential.

16. 1 kinds of methods that drive an active matrix displayer, in order to upgrade one first pixel electrode of described active matrix displayer and the pixel voltage of one second pixel electrode, described method comprises:

Within one first scan period, by making one first sweep trace and one second sweep trace of described active matrix displayer, it is noble potential simultaneously, and make described the first pixel electrode be electrically connected on a data line of described active matrix displayer, and make described the second pixel electrode be electrically connected on described the first pixel electrode; And

Within one second scan period, by making described the second sweep trace, it is electronegative potential to make described the first sweep trace be noble potential, and make described the first pixel electrode be electrically connected on described data line, and make described the second pixel electrode electrically separated with described the first pixel electrode

Wherein within each frame period, described the first sweep trace and described the second sweep trace all can be down to one first electronegative potential by noble potential, by described the first electronegative potential, be down to one second electronegative potential again, when described the first sweep trace is during in described the first electronegative potential or described the second electronegative potential, described the first pixel electrode is electrically separated with described data line, when described the second sweep trace is during in described the first electronegative potential or described the second electronegative potential, described the second pixel electrode is electrically separated with described data line.

17. methods as claimed in claim 16, wherein when described the first sweep trace is noble potential, one the first transistor meeting conducting of described active matrix displayer, and when described the second sweep trace is noble potential, one transistor seconds meeting conducting of described active matrix displayer, the source electrode of described the first transistor and drain electrode are coupled to described the first pixel electrode and described data line, the grid of described the first transistor is coupled to described the first sweep trace, the source electrode of described transistor seconds and drain electrode are coupled to described the first pixel electrode and described the second pixel electrode, and the grid of described transistor seconds is coupled to described the second sweep trace.

18. methods as claimed in claim 16, wherein said the first pixel electrode and described the second pixel electrode are located between described the first sweep trace and described the second sweep trace.

19. methods as claimed in claim 16, wherein said the first pixel electrode and described the second pixel electrode are located at the not homonymy of described the second sweep trace.

20. methods as claimed in claim 16, wherein said active matrix displayer include to overturn a plurality of described the first pixel electrode that the mode of pixel (flip pixel) arranges and a plurality of described the second pixel electrode of arranging in the mode of upset pixel.

21. methods as claimed in claim 16, wherein said the first pixel electrode has different pixel voltages from described the second pixel electrode.

22. methods as claimed in claim 16, wherein said the first pixel electrode and described the second pixel electrode have the area of different sizes.

23. methods as claimed in claim 16, the polarity of wherein said data line was only switched once every a frame period.

24. methods as claimed in claim 16, the polarity of wherein said data line was switched once every two scan periods.

25. methods as claimed in claim 16, wherein said the first pixel electrode has identical polarity with described the second pixel electrode.

26. methods as claimed in claim 16, wherein said the first pixel electrode has different polarity from described the second pixel electrode.

27. methods as claimed in claim 16, wherein said the first pixel electrode and described the second pixel electrode are covered by the filter layer of same color.

28. methods as claimed in claim 16, wherein said the first pixel electrode and described the second pixel electrode are covered by the filter layer of different colours.

29. methods as claimed in claim 16, wherein said the second scan period is less than described the first scan period.

30. 1 kinds of methods that drive an active matrix displayer, in order to upgrade one first pixel electrode of described active matrix displayer and the pixel voltage of one second pixel electrode, described method comprises:

Within one first scan period, by making one first sweep trace and one second sweep trace of described active matrix displayer, it is noble potential simultaneously, and make described the first pixel electrode be electrically connected on a data line of described active matrix displayer, and make described the second pixel electrode be electrically connected on described the first pixel electrode; And

Within one second scan period, by making described the second sweep trace, it is electronegative potential to make described the first sweep trace be noble potential, and make described the first pixel electrode be electrically connected on described data line, and make described the second pixel electrode electrically separated with described the first pixel electrode

Wherein when described the first pixel electrode is electrically connected on described data line, and described the second pixel electrode and described data line are electrical when separated, the voltage of described the first sweep trace is one first noble potential, and when described the first pixel electrode and described the second pixel electrode are all electrically connected on described data line, the voltage of described the first sweep trace and described the second sweep trace is one second noble potential, and described the second noble potential is less than described the first noble potential.